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I used the ISE 9.2 MIG to create a DDR2 mem controller for 267MHz memory chips, and it included a DCM to generate the 267MHz clock at 0 and 90 degrees, from an external 267MHz input. In my app, I have a 100MHz external input clock (low jitter), and I need four internal clocks: CLK0: 100MHz with zero skew re the input clock CLK1: 200MHz for IDELAYCTRL CLK2: 267MHz 0 degrees for DDR2 CLK3: 267MHz 90 degrees for DDR2 It seems that I can generate all of these with one PLL. The V5 User's Guide UG190 seems to recommend routing CLKFBOUT through a BUFG to CLKFBIN (fig 3-10). Or I think I could use the CLK0 BUFG output as the CLKFBIN signal, and save a BUFG by not using CLKFBOUT. Is there any reason to prefer CLKFBOUT over CLK0 to get zero skew? Are CLK2 and CLK3 going to be fine for the MIG DDR2 controller? Is the PLL's 90 degree difference just as accurate as that of a DCM? Thanks, BarryArticle: 124176
I have used genmcs.pl for single processor implementations but I have had no success in a multiprocessor device. My design runs perfectly through gdb/xmd but when I try and build the mcs file to allow it to boot from cache when programmed from the PROM I get nothing. This process works absolutely fine on a single processor device. Any ideas anyone?Article: 124177
Hi everybody, I'm using EDK 9.1i and in my design I use a Microblaze core (v 6.00.b). The device is a xc2v1000-4 (in a 2VMB1000 board from Memec Design). In every system that I create, the maximum clocking that I can acheive is about 80MHz because of DCACHE_FSL_OUT_CLK signal. Looking in the time information of the design report i see that the maximum clock for such signal is never more than 80.270MHz and if I try to use an higher clocking, the microcontroller doesn't start. In the past I have already programmed the same device (of the same board) but with previous versions of microblaze I acheived up to 120MHz. In my design I don't use cache so that the DCACHE_FSL_OUT_CLK is useless, but even if it is not used by the design it limits the clocking. I don't have time constraints in my ucf file. Is it possible to workaround this problem? The device is capable to reach higher clocking but with this version of Microblaze core it seems limited.... surely I'm missing something but I don't understand what... Any idea? Thank's a lot, Andrea.Article: 124178
On 13 Set, 14:21, "MJ Pearson" <mjp...@york.ac.uk> wrote: > Hello, > > I am using the xilinx virtex II development board xupv2p. I have built an > expansion board that connects to the high speed expansion port, and > delivers information from a camera. In ISE, I have produced what I think > is a working piece of vhdl to synchronise the camera data (there will be 2 > data sets incoming) to the FPGA clock. > > What I would like to do is just read out this incoming data so I can check > it. My idea was to use a microblaze processor - I will need one to do some > processing at a later stage, and just do a printf to write the data to > hyper-terminal. > > I used the create / import peripheral wizard, and have been hacking the > user_logic file to incorporate my synchronization design. I am a bit > unsure of ports though - do I have any user ports - are these the input > pins??? I have altered the UCF file to assign the pins of the expansion > port to my inputs in my vhdl file. Should I write this data to a slave > register?? > > Then in my C file, is it just a simple read and printf procedure. > > Any help / ideas I'd be grateful, > > Thanks > > Marc. Hi, I don't know if I have understood your point but it seems to me that you want to print data coming from a camera. If so, you should create a peripheral (like you have already done) with some SW registers. This registers are the interface between the peripheral and the microcontroller. The additional ports of your peripheral will be the interface between the peripheral itself and the camera. So your IP, once acquired the desired data, should write something to a register so that you can read it from the microprocessor. Probably you also need to write a simple driver (in C language) to find if there's someting new in the register, read the register and so on (the driver isn't strictly necessary). Googoling around you'll find all the details. Hope this help a little. AndreaArticle: 124179
If you add a TIG timing constraint to your UCF (see your constraints guid for details) for the specific path that's failing timing, you may be able to get improved timing. "Andrea05" <cispa@email.it> wrote in message news:1189702350.794190.111550@22g2000hsm.googlegroups.com... > Hi everybody, > I'm using EDK 9.1i and in my design I use a Microblaze core (v > 6.00.b). The device is a xc2v1000-4 (in a 2VMB1000 board from Memec > Design). > > In every system that I create, the maximum clocking that I can acheive > is about 80MHz because of DCACHE_FSL_OUT_CLK signal. Looking in the > time information of the design report i see that the maximum clock for > such signal is never more than 80.270MHz and if I try to use an higher > clocking, the microcontroller doesn't start. > > In the past I have already programmed the same device (of the same > board) but with previous versions of microblaze I acheived up to > 120MHz. > > In my design I don't use cache so that the DCACHE_FSL_OUT_CLK is > useless, but even if it is not used by the design it limits the > clocking. I don't have time constraints in my ucf file. > > Is it possible to workaround this problem? The device is capable to > reach higher clocking but with this version of Microblaze core it > seems limited.... surely I'm missing something but I don't understand > what... > > Any idea? > > Thank's a lot, > Andrea. >Article: 124180
"Alan Nishioka" <alan@nishioka.com> wrote in message news:1189692355.310776.149490@k79g2000hse.googlegroups.com... > On Sep 12, 7:12 pm, "cpope" <cep...@nc.rr.com> wrote: > > I have 4 user I/O pins on my V4FX12 device attached to my JTAG scan chain. I > > want to drive these lines to reprogram the XCF32P prom which my fpga boots > > from. I am running Linux on the PPC inside the FX12 so I'm thinking I can > > just cross compile some existing programmer and replace some low level > > functions (set tdo, read tdi, set/clear tms). > > > > Does anyone have something like this? Or can suggest what programmer code is > > most likely to work in this application? > > > That is what xsvf and svf are for > http://www.xilinx.com/bvdocs/appnotes/xapp503.pdf > > You download a little source code from xilinx, modify the low level > code to twiddle the tdi, tdi, tms and tck correctly and replay the > programming sequence generated by impact. > > xsvf is simply a binary coded svf to save some space. > > jdrive is similar software, but much more bloated C++ code. > > On Altera, you do the same thing with jam player. > http://www.altera.com/support/devices/tools/jam/tls-jam.html > > Alan Nishioka > Thanks. So you don't recommend using the jdrive code?Article: 124181
On Sep 13, 12:17 pm, "cpope" <cep...@nc.rr.com> wrote: > "Alan Nishioka" <a...@nishioka.com> wrote in message > > news:1189692355.310776.149490@k79g2000hse.googlegroups.com... > > > > > On Sep 12, 7:12 pm, "cpope" <cep...@nc.rr.com> wrote: > > > I have 4 user I/O pins on my V4FX12 device attached to my JTAG scan > chain. I > > > want to drive these lines to reprogram the XCF32P prom which my fpga > boots > > > from. I am running Linux on the PPC inside the FX12 so I'm thinking I > can > > > just cross compile some existing programmer and replace some low level > > > functions (set tdo, read tdi, set/clear tms). > > > > Does anyone have something like this? Or can suggest what programmer > code is > > > most likely to work in this application? > > > That is what xsvf and svf are for > >http://www.xilinx.com/bvdocs/appnotes/xapp503.pdf > > > You download a little source code from xilinx, modify the low level > > code to twiddle the tdi, tdi, tms and tck correctly and replay the > > programming sequence generated by impact. > > > xsvf is simply a binary coded svf to save some space. > > > jdrive is similar software, but much more bloated C++ code. > > > On Altera, you do the same thing with jam player. > >http://www.altera.com/support/devices/tools/jam/tls-jam.html > > > Alan Nishioka > > Thanks. So you don't recommend using the jdrive code? No. I tried it and it seems to work at a higher level than svf. It knows more about the JTAG protocol and reads BSDL files, whereas impact handles this when it creates an svf. But svf is simpler to use and implement and I use it exclusively. Alan NishiokaArticle: 124182
On Sep 13, 10:02 am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > "Hal Murray" <hal-use...@ip-64-139-1-69.sjc.megapath.net> wrote in message > > news:2q-dnXHQf72ryHXbnZ2dnUVZ_tninZ2d@megapath.net... > > > > > Gray code makes sure you only write something to either the > > old address or the new address. You also have to make sure > > that the new data doesn't get written to the old address. > > (or probably worse, part of the new data gets written > > on top of the old data) > > > How about > > 1: change address > > 2: wait for address to settle and data hold time > > 3: write new data > > Hal, > > If you were using an FPGA to do this you could clock the address > out on the rising edge of the clock, the data out on the falling > edge. If setup and hold times were met this would get you one > write per clock. > > Nial. I'm assuming from all this, that we're talking about interfacing to async memory. If so, then what you suggest will possibly fail timing because of a race condition between the write strobe going inactive and the address starting to change. So just exactly when would you be strobing the write signal itself? In order to do as you say the write pulse would need to be some time after the rising edge (after address settle max) but prior to or roughly coincident with the rising edge of the next clock (i.e. prior to address change min). It can be done, but from your post it seems like you're suggesting it would all be done simply with flops and run at the clock rate that clocks the flops at one write per clock....or am I missing something here? The general sequence of events to write to async SRAM is... 1. Setup address 2. Enable write and put out data to be written 3. Disable write 4. Allow address and data to do whatever. KJArticle: 124183
"cpope" <cepope@nc.rr.com> writes: > from. I am running Linux on the PPC inside the FX12 so I'm thinking How do you get the bitstream (xsvf or whatever) into the FX12? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 124184
>The general sequence of events to write to async SRAM is... >1. Setup address Wait address setup time >2. Enable write and put out data to be written Wait max of data setup time min write pulse width >3. Disable write Wait address/data hold time >4. Allow address and data to do whatever. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124185
Can anyone suggest a tutorial for MicroBlaze? I have googled it and found many tutorials, however, most seem to emphasize the software end of things, whereas I already have an evolved hardware system built from Project Navigator that needs to be folded into the design. I followed one EDK 7.1 MicroBlaze Tutorial in Spartan 3 as a partial guide (I'm actually on an ML402) and came up with these questions: 1) In this tutorial there seems to be a XPS directory and a separate Proj Nav directory. I tried to open both tools in one directory and it failed. What is the best strategy for maintaining directories? 2) I attempted to add a MicroBlaze uP with only the UART enabled in the Studio Wizard. I then followed steps to incorporate the system_stub into the Proj Navigator. I then had two top level designs in Proj Navigator. Since the Microblaze was new and short, I decided to wrap the system_stub into the top of my hardware by declaring the system_stub as a component, and instantiating it once in the top layer. This elaborated into a single project. I also cut and paste the IOs into the top.ucf file. Some IOs, the sys_clk_in and sys_rst_in repeat. The TX and RX signals were added into the ucf file and also added to the top entity. I now have this synthesize error: "Port is connected to input buffer and following ports: Port IO of instance reset 1 in unit top with type LUT1." I think I can fudge around this but isn't there a better way to handle UCF edits? 3) In general, can I share inputs with top and system_stub? 4) If system_stub and top want an output is there a way to switch or mux from one to the other? 5) I think the ideal tutorial would have a simple hardware algorithm and the MicroBlaze would be added to change some parameters within that algorithm or exchange data. Perhaps, a dual ported BRAM with one side going to the MicroBlaze and another to the top layer. 6) What clock frequency does system_stub need? Thanks for your advice, Brad Smallridge Ai VisionArticle: 124186
Xilinx posts gerber file in *.pho format on their website for all of the evaluation boards. Does anyone no how to import these into cadence OrCad? or what tool they used to design them in? Thanks,Article: 124187
>> How about >> 1: change address >> 2: wait for address to settle and data hold time >> 3: write new data >If you were using an FPGA to do this you could clock the address >out on the rising edge of the clock, the data out on the falling >edge. If setup and hold times were met this would get you one >write per clock. I think that would work, but the RAM only gets a half cycle to do the write so you probably need a faster RAM. (or a slower cycle time on the FPGA) As always, check the fine print in the data sheet. With something like this, check again. (Or better yet, get somebody else to double check your work, not just the arithmetic, but the reading of the data sheet.) -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124188
Hi Brad, My recommendation is when getting started with MicroBlaze, just stick with the XPS (platform studio) tool, and the Base System Builder wizard. Build your EDK systems as the top level, and don't do any of that silly "Import to ProjNav" stuff. I really have no idea why this complicated flow is pushed in introductory documents - it makes no sense until you have specific reasons to do so. One of my students put together a nice walkthrough for the ML401, it might be useful to you: http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf You can ignore the uClinux-specific software stuff if that's not what you're after. Regards, John Brad Smallridge wrote: > Can anyone suggest a tutorial for MicroBlaze? > > I have googled it and found many tutorials, > however, most seem to emphasize the software end > of things, whereas I already have an evolved hardware > system built from Project Navigator that needs to > be folded into the design. > > I followed one EDK 7.1 MicroBlaze Tutorial in Spartan > 3 as a partial guide (I'm actually on an ML402) and > came up with these questions: > > 1) In this tutorial there seems to be a XPS directory > and a separate Proj Nav directory. I tried to open > both tools in one directory and it failed. What is > the best strategy for maintaining directories? > > 2) I attempted to add a MicroBlaze uP with only the > UART enabled in the Studio Wizard. I then followed > steps to incorporate the system_stub into the Proj > Navigator. I then had two top level designs in Proj > Navigator. Since the Microblaze was new and short, > I decided to wrap the system_stub into the top of my > hardware by declaring the system_stub as a component, > and instantiating it once in the top layer. This > elaborated into a single project. I also cut and paste > the IOs into the top.ucf file. Some IOs, the sys_clk_in > and sys_rst_in repeat. The TX and RX signals were added > into the ucf file and also added to the top entity. I > now have this synthesize error: "Port is connected to > input buffer and following ports: Port IO of > instance reset 1 in unit top with type LUT1." I think > I can fudge around this but isn't there a better way to > handle UCF edits? > > 3) In general, can I share inputs with top and system_stub? > > 4) If system_stub and top want an output is there a way to > switch or mux from one to the other? > > 5) I think the ideal tutorial would have a simple hardware > algorithm and the MicroBlaze would be added to change some > parameters within that algorithm or exchange data. Perhaps, > a dual ported BRAM with one side going to the MicroBlaze and > another to the top layer. > > 6) What clock frequency does system_stub need? > > Thanks for your advice, > > Brad Smallridge > Ai Vision > > >Article: 124189
Dolphin wrote: > I know that it is possible to overload operators like 'and', 'or', > '+',... by using a function with the name "and", "or", "+",... . > Is it also possible to overload the attribute operators like: 'high, > 'left, 'low, ..? Is it possible to create your own attributes? I doubt it - I don't think the ' is an operator as such.. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 124190
Hi All, I've been doing some development work over the past year or so on the Atmel FPSLIC platform. I've run out of time on the license for the Mentor software that came with the dev kit, and am wondering if there are any open-source projects that can handle VHDL design for the FPSLIC. I've looked at Slipway, and that looks promising for the backend, but as far as I can tell it only supports Icarus Verilog entry? Porting my design to Verilog isn't something I'd like to do, so any suggestions would be greatly appreciated. Thanks! Jonathan Krauss -- Low:SNR Engineering http://www.lowsnr.comArticle: 124191
Hi, If you provided with your settings of MicroBlaze from the .mhs file, I can have a look at see if there is something that can be trimmed. Göran "Andrea05" <cispa@email.it> wrote in message news:1189702350.794190.111550@22g2000hsm.googlegroups.com... > Hi everybody, > I'm using EDK 9.1i and in my design I use a Microblaze core (v > 6.00.b). The device is a xc2v1000-4 (in a 2VMB1000 board from Memec > Design). > > In every system that I create, the maximum clocking that I can acheive > is about 80MHz because of DCACHE_FSL_OUT_CLK signal. Looking in the > time information of the design report i see that the maximum clock for > such signal is never more than 80.270MHz and if I try to use an higher > clocking, the microcontroller doesn't start. > > In the past I have already programmed the same device (of the same > board) but with previous versions of microblaze I acheived up to > 120MHz. > > In my design I don't use cache so that the DCACHE_FSL_OUT_CLK is > useless, but even if it is not used by the design it limits the > clocking. I don't have time constraints in my ucf file. > > Is it possible to workaround this problem? The device is capable to > reach higher clocking but with this version of Microblaze core it > seems limited.... surely I'm missing something but I don't understand > what... > > Any idea? > > Thank's a lot, > Andrea. >Article: 124192
On Sep 13, 10:02 pm, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > "Hal Murray" <hal-use...@ip-64-139-1-69.sjc.megapath.net> wrote in message > > news:2q-dnXHQf72ryHXbnZ2dnUVZ_tninZ2d@megapath.net... > > > > > Gray code makes sure you only write something to either the > > old address or the new address. You also have to make sure > > that the new data doesn't get written to the old address. > > (or probably worse, part of the new data gets written > > on top of the old data) > It depends on the application of course. When I first encountered this technique it was on a video sampling hardware. As such it didn't matter much if the intended data happened to appear one pixel to the left. I guess back then memory was fast but logic was slow especially since in that specific case it was a bunch of 74xx TTL logic chips.Article: 124193
Hi, Is the post place&route simulation so important? IMHO doing post synthesis (or post translate) simulation for verifying behavior than doing a post place and route static timing analysis is sufficient and less resource consuming than doing a timing simulation. Moreover if errors are found during timing simulations (by errors I mean X or false results) they are almost always (for my cases) difficultly traceable. MehdiArticle: 124194
>From the above assembly code can do the same with the MTDCR and MFDCR instructions? Or the logic of writting the assembly is totally different? I am asking because i have added a DCR IP in my design. Also another question is that the "S_bramenable" signal. Who i can set when i want to enable to reade from the Slave or not? regards xenixArticle: 124195
> I'm assuming from all this, that we're talking about interfacing to > async memory. If so, then what you suggest will possibly fail timing > because of a race condition between the write strobe going inactive > and the address starting to change. So just exactly when would you be > strobing the write signal itself? You wouldn't, if you'd read the thread you'd have seen that the write strobe is being held active and the (grey coded) address change is being used to action the write.... Addr X ADR1 X ADR2 X ADR3 X ADR4 X Data X D1 X D2 X D3 X D4 X I've never tried this in anger because no sram data sheet that I could find had any information on whether this mechanism would work, it was just an idea on how to stream data into an external SRAM faster. Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883 32/12 Hardengreen Business Park Fax: +44 131 663 8771 Dalkeith, Midlothian EH22 3NX www.nialstewartdevelopments.co.ukArticle: 124196
Hi all, I'm wondering if anybody synthesized the Xilinx GSRD reference design with any 3rd party synthesizer. I'd like to compare the fitting report with the one produced by ISE. Anybody can help me? TIA, llandreArticle: 124197
CPLDs and FPGAs both make (or made) use of "non-standard" implementation of digital circuits, namely wired-OR and pass-transistors. Both techniques are much more difficult to use in standard cell ASICs or gate arrays. Therefore, one could argue that the use of these methods reduced the area and speed overhead induced by the programmability. So while many ASICs that have been replaced by FPGAs would not have used the methods, the CPLDs/FPGAs did. How strong do you think was and is this effect? Would FPGAs have been successfull, if they had been implemented with vanilla CMOS gates and latches? Or better, how much smaller the success story of FPGAs would have been without the use of pass transistors in LUTs and routing? AndreasArticle: 124198
Hi All, I'm designing a circuit for configuring 4 Spartan-3E FPGA from an Atmel AVR microcontroller. I want to configure the FPGA in slave serial mode. Because of the difference in the supply voltages, there are some different logic voltages, some 2.5V, some 3.3V AVR 3.3V FPGA VCC0 3.3V FPGA VCCAUX 2.5V http://www.xilinx.com/bvdocs/appnotes/xapp453.pdf Xapp453 states that CCLK needs to be driven with 2.5V logic, however, the Spartan-3E datasheet states (Page 68) that CCLK is powered by VCC0_2 which will be 3.3V. I'm guessing that the contradiction is due to XAPP453 being for Spartan-3, not Spartan-3E. I just need to know if CCLK needs the logic level changing as well the PROG_B signal. Could someone just check the following for me: PROG_B driven by AVR needs to be 2.5V logic DIN driven by AVR 3.3V logic (I think) CCLK driven by AVR 3.3V logic INIT_B driven by FPGA 3.3V logic DONE driven by FPGA 2.5V logic DOUT driven by FPGA 3.3V logic Many thanks AndyArticle: 124199
On Sep 14, 3:57 am, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi, > Is the post place&route simulation so important? > IMHO doing post synthesis (or post translate) simulation for verifying > behavior than doing a post place and route static timing analysis is > sufficient and less resource consuming than doing a timing simulation. Once one is sufficiently skilled I would agree....at least for FPGA designs. For ASICs where the cost for fixing an error is much, much higher one might have a different opinion. > Moreover if errors are found during timing simulations (by errors I > mean X or false results) they are almost always (for my cases) > difficultly traceable. Which sounds like you're maybe not quite there on the 'sufficiently skilled' front since you still get 'X' or false results. Definitely a pain in the rear to trace back to the root cause through the post- route sim I agree. KJ
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