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Hi, I am working on a Xilinx Virtex5 design. I generated a pin lock file (ucf) and have a top level verilog file. Top level verilog file does not have any code, but it has only IO declarations.And I want to generate the pad file out of this. The issue is that since it is an empty design, I get the following error message, " NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper. " I tried -u options in MAP, and I have also enable add IO buffer options in XST, but it still gives the same error. I know I can write some dummy logic and generate the pad file, but was wondering if there is any easier method of doing this? Does anyone know how can I give this SAVE attribute as mentioned in the error above? Or is there any way to generate the pad file. Regards, Goli

I would like to know which round,fix and floor algorithm would be best to be implemented on an FPGA. I am working on a DSP project. I want to write funtions in VHDL which can be called and would return the round, fix and floor value of integers. Does VHDL have pre defined functions which could do this like in C,C+ +. If not, which would be the best way to do this. Please help

Brian Davis wrote: > [1] close in DDS phase noise artifacts: > http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350 Thanks for this link, this was an interesting discussion. I really like the idea using a DAC for creating a sine output and a comparator for creating a square wave, because then you are using more bits of the accumulator and you can avoid wandering, if you want to generate 1.000....0001 * fclock. I think this could be implemented with low bit counts for the DAC, if you feed it to a good analog band pass filter and if you use very good comparators for low jitter. And it should be possible to use a fixed filter and then feed it back into a PLL for producing a wide range of output frequencies. For very high precision you could use a VCXO to synchronize the reference clock to GPS or easier to use time bases, like DCF77 in Germany or one of the other many time and frequency stations in other countries: http://www.ac6v.com/standard.htm -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:8ikon35hsoitj6gkbq9k3fu8oevju1f7dm@4ax.com... > On Wed, 2 Jan 2008 18:41:13 -0000, "Symon" <symon_brewer@hotmail.com> >> >> http://www.emcesd.com/tt2002/tt120102.htm >> > > > For Pete's sake, he used WIRES. He couldn't even afford an x-acto > knife. > Hi John, Thanks for your response. I guess you don't think his experiment is equivalent to your suggestion? Perhaps you would describe exactly what experiment you envisage? N.B. I understand we're getting away from the OP's system with two planes here. That said... In Mr. Smith's experiment, the wire crosses a slit in the power plane. I guess he cut the slit with a knife, which I bet he can afford, considering they are cheaper than a Agilent 54845a 'scope! This is a way to get the signal close to a copper-clad plane to simulate the effect of a trace on an adjacent PCB layer to a plane. If the trace is on the opposite face of the copper clad to the plane, the loop area between signal and plane is considerably larger even without the slit, so the slit won't be as big a problem, for a given characteristic impedance of the signal. >> >>There are further experiments here:- >> http://www.emcesd.com/tt2003/tt010103.htm John, I think you might have missed this link, but this experiment shows where the current flows. It shows the return current in black and white. (Or maybe yellow!) I'd be especially interested in your comments about this experiment. It shows the signal does not capacitively couple across the slit to any great degree. >> >> http://www.emcesd.com/tt2003/tt020103.htm >> > > Not too surprising, 20 cm away from what appears to be a kilovolt > spark gap. It's difficult to make any sort of quantitative > extrapolation from this to real circuits. > > John > This demonstrates susceptibility to electrostatic discharge (ESD). As I'm sure you know, these discharges can easily exceed 1kV. It's important to understand that signals that cross breaks in ground planes are particularly susceptible to ESD. Thanks, Symon.

<FPGA23@gmail.com> wrote in message news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.com... >I would like to know which round,fix and floor algorithm would be best > to be implemented on an FPGA. I am working on a DSP project. I want to > write funtions in VHDL which can be called and would return the round, > fix and floor value of integers. > > Does VHDL have pre defined functions which could do this like in C,C+ > +. If not, which would be the best way to do this. > > Please help > In the ieee.math_real lib you'll find all three: ceil, floor and round KJ

"Symon" <symon_brewer@hotmail.com> wrote in message news:flidms$1j2$1@aioe.org... >>> >>>There are further experiments here:- >>> http://www.emcesd.com/tt2003/tt010103.htm > > John, I think you might have missed this link, but this experiment shows > where the current flows. It shows the return current in black and white. > (Or maybe yellow!) I'd be especially interested in your comments about > this experiment. It shows the signal does not capacitively couple across > the slit to any great degree. > Hmm, thinking harder about it, it doesn't necessarily show the lack of current across the gap. But it does show that not all of it couples across. Further experimentation and/or calculation would be necessary to show where the majority of current goes, but the fact that at least some of it follows the path around the slit shows the problem with increased inductance and EMI. Cheers, Syms.

<FPGA23@gmail.com> wrote in message news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.com... >I would like to know which round,fix and floor algorithm would be best > to be implemented on an FPGA. I am working on a DSP project. I want to > write funtions in VHDL which can be called and would return the round, > fix and floor value of integers. > I'm missing something. How do you 'round' or 'floor' an integer? They already are, aren't they? Cheers, Syms.

Frank Buss wrote: > > Thanks for this link, this was an interesting discussion. I really like the > idea using a DAC for creating a sine output and a comparator for creating a > square wave, because then you are using more bits of the accumulator and > you can avoid wandering, if you want to generate 1.000....0001 * fclock. > Using a DAC with hard limiting will reduce their level vs. a single bit DDS, but the bothersome truncation/quantization artifacts are still there in a conventional DDS. Veering back onto discussing single bit DDS's, given a high rate serializer to press into use, there are a variety of fractional-N or noise shaping techniques that should work well, e.g. [4],[5] Brian [4] HP single-bit fractional-N: "A Multiple Modulator Fractional Divider", Miller/Conley, 1990 http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=177545 (also reprinted in Kroupa's DDFS book) http://www.google.com/patents?id=6PMaAAAAEBAJ&dq=5038117 [5] bandpass delta-sigma modulator: http://lib.tkk.fi/Diss/2007/isbn9789512288090/article6.pdf

Hi all ! I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with iverilog and testbench associated. Waveforms with gtkwave looks good. I have been trying to synthetise a simple 8bit counter within WebPack ISE 9.2 edition. The "Translate" phase failed : .... Writing NGD file "counter.ngd" ... Writing NGDBUILD log file "counter.bld"... NGDBUILD done. Process "Translate" failed ... What's wrong with this ? PS : /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ `timescale 1ns / 1ps module counter(in, out, clk, reset, load); input [7:0] in; input clk; input reset; input load; output reg[7:0] out; /* Chargement synchrone par load */ always @(posedge clk) begin out<=out+1; if (reset==1) out[7:0] <= 0; else if(load==1) out[7:0] <= in[7:0]; end endmodule Here the test_bench associated module test(); reg [7:0] bin ; wire [7:0] bout ; reg clk, reset, load; // wire s, cout; counter counter_en_test(bin, bout, clk, reset, load); initial begin bin = 4'b00010111; clk = 0; load = 0; reset = 0; #5; clk = 1; load = 1; #5; clk = 0; load=0; #5; clk = 1; #5; clk = 0; #5; clk = 1; #5; clk = 0; load = 1; #5; clk = 1; #5; clk = 0; #5; clk = 1; end // initial begin initial begin $dumpfile ("counter.vcd"); $dumpvars; end initial begin $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); end endmodule // test -- HBV

Habib Bouaziz-Viallet wrote: > Hi all ! > > I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with > iverilog and testbench associated. Waveforms with gtkwave looks good. > > I have been trying to synthetise a simple 8bit counter within WebPack ISE > 9.2 edition. > > The "Translate" phase failed : > .... > Writing NGD file "counter.ngd" ... > Writing NGDBUILD log file "counter.bld"... > NGDBUILD done. > Process "Translate" failed > > ... > > What's wrong with this ? Did it give you any specific errors ? (click on 'Errors' tab at the bottom). > > > PS : > /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ > `timescale 1ns / 1ps > module counter(in, out, clk, reset, load); > input [7:0] in; > input clk; > input reset; > input load; > output reg[7:0] out; > > /* Chargement synchrone par load */ > always @(posedge clk) > begin > out<=out+1; > if (reset==1) > out[7:0] <= 0; > else if(load==1) > out[7:0] <= in[7:0]; > end You're doing two assignments to 'out' in the same clock cycle. Try: always @(posedge clk) begin if (reset==1) out[7:0] <= 0; else if(load==1) out[7:0] <= in[7:0]; else out<=out+1; end > > endmodule > > Here the test_bench associated > > > module test(); > > reg [7:0] bin ; > wire [7:0] bout ; > reg clk, reset, load; // wire s, cout; > > counter counter_en_test(bin, bout, clk, reset, load); > > initial > begin > > bin = 4'b00010111; > clk = 0; > load = 0; > reset = 0; > > #5; > clk = 1; > load = 1; > > > #5; > clk = 0; > load=0; > > #5; > clk = 1; > > #5; > clk = 0; > > #5; > clk = 1; > > #5; > clk = 0; > load = 1; > > #5; > clk = 1; > > #5; > clk = 0; > > #5; > clk = 1; > > > end // initial begin > > initial > begin > $dumpfile ("counter.vcd"); > $dumpvars; > end > > initial > begin > $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); > $monitor("%d \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); > end > > endmodule // test > > >

Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: > Habib Bouaziz-Viallet wrote: >> Hi all ! >> >> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >> iverilog and testbench associated. Waveforms with gtkwave looks good. >> >> I have been trying to synthetise a simple 8bit counter within WebPack ISE >> 9.2 edition. >> >> The "Translate" phase failed : >> .... >> Writing NGD file "counter.ngd" ... >> Writing NGDBUILD log file "counter.bld"... >> NGDBUILD done. >> Process "Translate" failed >> >> ... >> >> What's wrong with this ? > > Did it give you any specific errors ? (click on 'Errors' tab at the bottom). > No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. (In Warnings TAB) > > >> >> PS : >> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >> `timescale 1ns / 1ps >> module counter(in, out, clk, reset, load); >> input [7:0] in; >> input clk; >> input reset; >> input load; >> output reg[7:0] out; >> >> /* Chargement synchrone par load */ >> always @(posedge clk) >> begin >> out<=out+1; >> if (reset==1) >> out[7:0] <= 0; >> else if(load==1) >> out[7:0] <= in[7:0]; >> end > > You're doing two assignments to 'out' in the same clock cycle. That's right but i'm not sur that this is an issue in that case. I'm learning Verilog at the moment. Thanks. > > Try: > > always @(posedge clk) > begin > if (reset==1) > out[7:0] <= 0; > else if(load==1) > out[7:0] <= in[7:0]; > else > out<=out+1; > end > > > >> endmodule >> >> Here the test_bench associated >> >> >> module test(); >> >> reg [7:0] bin ; >> wire [7:0] bout ; >> reg clk, reset, load; // wire s, cout; >> >> counter counter_en_test(bin, bout, clk, reset, load); >> >> initial >> begin >> >> bin = 4'b00010111; >> clk = 0; >> load = 0; >> reset = 0; >> >> #5; >> clk = 1; >> load = 1; >> >> >> #5; >> clk = 0; >> load=0; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> load = 1; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> >> #5; >> clk = 1; >> >> >> end // initial begin >> >> initial >> begin >> $dumpfile ("counter.vcd"); >> $dumpvars; >> end >> >> initial >> begin >> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >> end >> >> endmodule // test >> >> >> -- HBV

Habib Bouaziz-Viallet wrote: > Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: > >> Habib Bouaziz-Viallet wrote: >>> Hi all ! >>> >>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>> >>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>> 9.2 edition. >>> >>> The "Translate" phase failed : >>> .... >>> Writing NGD file "counter.ngd" ... >>> Writing NGDBUILD log file "counter.bld"... >>> NGDBUILD done. >>> Process "Translate" failed >>> >>> ... >>> >>> What's wrong with this ? >> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >> > No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable > for this technology. (In Warnings TAB) >> >>> PS : >>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>> `timescale 1ns / 1ps >>> module counter(in, out, clk, reset, load); >>> input [7:0] in; >>> input clk; >>> input reset; >>> input load; >>> output reg[7:0] out; >>> >>> /* Chargement synchrone par load */ >>> always @(posedge clk) >>> begin >>> out<=out+1; >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> end >> You're doing two assignments to 'out' in the same clock cycle. > That's right but i'm not sur that this is an issue in that case. I'm > learning Verilog at the moment. Thanks. >> Try: >> >> always @(posedge clk) >> begin >> if (reset==1) >> out[7:0] <= 0; >> else if(load==1) >> out[7:0] <= in[7:0]; >> else >> out<=out+1; >> end >> I tried this counter module in ISE Webpack 9.2 in Linux, and it builds fine. The test bench contains constructs that aren't synthesizable, such as the delays, $display() calls, and the fact that it doesn't have any I/O signals. >> >> >>> endmodule >>> >>> Here the test_bench associated >>> >>> >>> module test(); >>> >>> reg [7:0] bin ; >>> wire [7:0] bout ; >>> reg clk, reset, load; // wire s, cout; >>> >>> counter counter_en_test(bin, bout, clk, reset, load); >>> >>> initial >>> begin >>> >>> bin = 4'b00010111; >>> clk = 0; >>> load = 0; >>> reset = 0; >>> >>> #5; >>> clk = 1; >>> load = 1; >>> >>> >>> #5; >>> clk = 0; >>> load=0; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> load = 1; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> >>> #5; >>> clk = 1; >>> >>> >>> end // initial begin >>> >>> initial >>> begin >>> $dumpfile ("counter.vcd"); >>> $dumpvars; >>> end >>> >>> initial >>> begin >>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>> end >>> >>> endmodule // test >>> >>> >>> > > >

On Jan 3, 4:22 am, Goli <tog...@gmail.com> wrote: > Hi, > > I am working on a Xilinx Virtex5 design. I generated a pin lock file > (ucf) and have a top level verilog file. Top level verilog file does > not have any code, but it has only IO declarations.And I want to > generate the pad file out of this. > > The issue is that since it is an empty design, I get the following > error message, > " > NCD was not produced. All logic was removed from design. This > is usually due to having no input or output PAD connections in the > design and > no nets or symbols marked as 'SAVE'. You can either add PADs or > 'SAVE' > attributes to the design, or run 'map -u' to disable logic trimming > in the > mapper. > " > > I tried -u options in MAP, and I have also enable add IO buffer > options in XST, but it still gives the same error. > > I know I can write some dummy logic and generate the pad file, but was > wondering if there is any easier method of doing this? > > Does anyone know how can I give this SAVE attribute as mentioned in > the error above? Or is there any way to generate the pad file. > > Regards, > Goli What info do you want to save to this PAD file? You can give ADEPT (http://home.comcast.net/%7Ejimwu88/tools/adept/) a try to see if it may do what you want. If it doesn't, please let me know and I will see if I can help. Cheers, Jim

Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: > Habib Bouaziz-Viallet wrote: > >> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>>> Hi all ! >>>> >>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>> >>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>> 9.2 edition. >>>> >>>> The "Translate" phase failed : >>>> .... >>>> Writing NGD file "counter.ngd" ... >>>> Writing NGDBUILD log file "counter.bld"... >>>> NGDBUILD done. >>>> Process "Translate" failed >>>> >>>> ... >>>> >>>> What's wrong with this ? >>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>> >> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >> for this technology. (In Warnings TAB) >>> >>>> PS : >>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>> `timescale 1ns / 1ps >>>> module counter(in, out, clk, reset, load); >>>> input [7:0] in; >>>> input clk; >>>> input reset; >>>> input load; >>>> output reg[7:0] out; >>>> >>>> /* Chargement synchrone par load */ >>>> always @(posedge clk) >>>> begin >>>> out<=out+1; >>>> if (reset==1) >>>> out[7:0] <= 0; >>>> else if(load==1) >>>> out[7:0] <= in[7:0]; >>>> end >>> You're doing two assignments to 'out' in the same clock cycle. >> That's right but i'm not sur that this is an issue in that case. I'm >> learning Verilog at the moment. Thanks. >>> Try: >>> >>> always @(posedge clk) >>> begin >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> else >>> out<=out+1; >>> end >>> > > I tried this counter module in ISE Webpack 9.2 in Linux, and it builds > fine. waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux. > > The test bench contains constructs that aren't synthesizable, such as > the delays, $display() calls, and the fact that it doesn't have any I/O > signals. That's right. the test bench is here only for getting readeable results with iverilog(or cver) and gtkwave > > > >>>> endmodule >>>> >>>> Here the test_bench associated >>>> >>>> >>>> module test(); >>>> >>>> reg [7:0] bin ; >>>> wire [7:0] bout ; >>>> reg clk, reset, load; // wire s, cout; >>>> >>>> counter counter_en_test(bin, bout, clk, reset, load); >>>> >>>> initial >>>> begin >>>> >>>> bin = 4'b00010111; >>>> clk = 0; >>>> load = 0; >>>> reset = 0; >>>> >>>> #5; >>>> clk = 1; >>>> load = 1; >>>> >>>> >>>> #5; >>>> clk = 0; >>>> load=0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> load = 1; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> >>>> end // initial begin >>>> >>>> initial >>>> begin >>>> $dumpfile ("counter.vcd"); >>>> $dumpvars; >>>> end >>>> >>>> initial >>>> begin >>>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>>> end >>>> >>>> endmodule // test >>>> >>>> >>>> >> >> >> Many thanks Arlet ! -- HBV

Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: > Habib Bouaziz-Viallet wrote: > >> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>>> Hi all ! >>>> >>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>> >>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>> 9.2 edition. >>>> >>>> The "Translate" phase failed : >>>> .... >>>> Writing NGD file "counter.ngd" ... >>>> Writing NGDBUILD log file "counter.bld"... >>>> NGDBUILD done. >>>> Process "Translate" failed >>>> >>>> ... >>>> >>>> What's wrong with this ? >>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>> >> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >> for this technology. (In Warnings TAB) >>> >>>> PS : >>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>> `timescale 1ns / 1ps >>>> module counter(in, out, clk, reset, load); >>>> input [7:0] in; >>>> input clk; >>>> input reset; >>>> input load; >>>> output reg[7:0] out; >>>> >>>> /* Chargement synchrone par load */ >>>> always @(posedge clk) >>>> begin >>>> out<=out+1; >>>> if (reset==1) >>>> out[7:0] <= 0; >>>> else if(load==1) >>>> out[7:0] <= in[7:0]; >>>> end >>> You're doing two assignments to 'out' in the same clock cycle. >> That's right but i'm not sur that this is an issue in that case. I'm >> learning Verilog at the moment. Thanks. >>> Try: >>> >>> always @(posedge clk) >>> begin >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> else >>> out<=out+1; >>> end >>> > > I tried this counter module in ISE Webpack 9.2 in Linux, and it builds > fine. > > The test bench contains constructs that aren't synthesizable, such as > the delays, $display() calls, and the fact that it doesn't have any I/O > signals. > >>> >>> >>>> endmodule >>>> >>>> Here the test_bench associated >>>> >>>> >>>> module test(); >>>> >>>> reg [7:0] bin ; >>>> wire [7:0] bout ; >>>> reg clk, reset, load; // wire s, cout; >>>> >>>> counter counter_en_test(bin, bout, clk, reset, load); >>>> >>>> initial >>>> begin >>>> >>>> bin = 4'b00010111; >>>> clk = 0; >>>> load = 0; >>>> reset = 0; >>>> >>>> #5; >>>> clk = 1; >>>> load = 1; >>>> >>>> >>>> #5; >>>> clk = 0; >>>> load=0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> load = 1; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> >>>> end // initial begin >>>> >>>> initial >>>> begin >>>> $dumpfile ("counter.vcd"); >>>> $dumpvars; >>>> end >>>> >>>> initial >>>> begin >>>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>>> end >>>> >>>> endmodule // test >>>> >>>> >>>> >> >> >> The problem was that some files in ../bin/lin/ have not executing perms. i made this : chmod +x winds* or something ... and it compiles fine now ! Many thank ! -- HBV

Habib Bouaziz-Viallet wrote: > Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: > >> Habib Bouaziz-Viallet wrote: >> >>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>> >>>> Habib Bouaziz-Viallet wrote: >>>>> Hi all ! >>>>> >>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>> >>>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>>> 9.2 edition. >>>>> >>>>> The "Translate" phase failed : >>>>> .... >>>>> Writing NGD file "counter.ngd" ... >>>>> Writing NGDBUILD log file "counter.bld"... >>>>> NGDBUILD done. >>>>> Process "Translate" failed >>>>> >>>>> ... >>>>> >>>>> What's wrong with this ? >>>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>>> >>> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >>> for this technology. (In Warnings TAB) yeah, I get those warnings all the time too. >>>>> PS : >>>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>>> `timescale 1ns / 1ps >>>>> module counter(in, out, clk, reset, load); >>>>> input [7:0] in; >>>>> input clk; >>>>> input reset; >>>>> input load; >>>>> output reg[7:0] out; >>>>> >>>>> /* Chargement synchrone par load */ >>>>> always @(posedge clk) >>>>> begin >>>>> out<=out+1; >>>>> if (reset==1) >>>>> out[7:0] <= 0; >>>>> else if(load==1) >>>>> out[7:0] <= in[7:0]; >>>>> end >> I tried this counter module in ISE Webpack 9.2 in Linux, and it builds >> fine. > waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux. Ubuntu (Edgy), so it's debian based. I had to install the open motif libs, but that's it. What device are you targetting ?

Le Thu, 03 Jan 2008 15:45:58 +0100, Arlet Ottens a écrit: > Habib Bouaziz-Viallet wrote: >> Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>> >>>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>>> >>>>> Habib Bouaziz-Viallet wrote: >>>>>> Hi all ! >>>>>> >>>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>>> >>>>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>>>> 9.2 edition. >>>>>> >>>>>> The "Translate" phase failed : >>>>>> .... >>>>>> Writing NGD file "counter.ngd" ... >>>>>> Writing NGDBUILD log file "counter.bld"... >>>>>> NGDBUILD done. >>>>>> Process "Translate" failed >>>>>> >>>>>> ... >>>>>> >>>>>> What's wrong with this ? >>>>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>>>> >>>> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >>>> for this technology. (In Warnings TAB) > > yeah, I get those warnings all the time too. > >>>>>> PS : >>>>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>>>> `timescale 1ns / 1ps >>>>>> module counter(in, out, clk, reset, load); >>>>>> input [7:0] in; >>>>>> input clk; >>>>>> input reset; >>>>>> input load; >>>>>> output reg[7:0] out; >>>>>> >>>>>> /* Chargement synchrone par load */ >>>>>> always @(posedge clk) >>>>>> begin >>>>>> out<=out+1; >>>>>> if (reset==1) >>>>>> out[7:0] <= 0; >>>>>> else if(load==1) >>>>>> out[7:0] <= in[7:0]; >>>>>> end > >>> I tried this counter module in ISE Webpack 9.2 in Linux, and it builds >>> fine. >> waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux. > > Ubuntu (Edgy), so it's debian based. I had to install the open motif > libs, but that's it. Open motif ?? I have download this morning the huge file (1.7G) from Xilinx and just type ./setup as the promise and do weird thing as download ServicePack or something and ... finally it works (almost ... see my post) > > What device are you targetting ? Oh just CPLD's for the moment 'cause i'm trying to speak Verilog as well i speak C/C++. -- HBV

On Jan 3, 7:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > <FPG...@gmail.com> wrote in message > > news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.com...>I would like to know which round,fix and floor algorithm would be best > > to be implemented on an FPGA. I am working on a DSP project. I want to > > write funtions in VHDL which can be called and would return the round, > > fix and floor value of integers. > > I'm missing something. How do you 'round' or 'floor' an integer? They > already are, aren't they? > Cheers, Syms. For integers, I think it should be approached as round(), ceil() or floor() of a ratio of two integers, since rational numbers (including rational approximations of non-rational numbers) are the primary issue, not integers. Unsigned integer division uses floor anyway. I've implemented unsigned ceil(n/d) before as (n + d - 1) / d, used for constants only (no synthesized hardware created). I haven't tried it, but I suppose something like (n + d / 2) / d would work for unsigned round()? It makes my head hurt to think about signed versions of these... In hardware, bit operations are probably more efficient (i.e. perform a fixed point division, and add one if the fraction msb is set for round(), or if any fraction bits are set for ceil(), then truncate the fraction. Anyone looked at the fixed point package to see how they do it? Andy

Hello, I've some issues hooking up some external components (camera link based cameras) to my XUPV2P board. I've built a PCB which connects the high speed expansion port of the XUPV2P to the outputs of the National Chip DS90CR288A. I've two cameras running simultaneously, so thats two chips on the PCB. On the high speed expansion port of the XUPV2P there's a clock input, but because I've got two external clocks (one from each chip), I decided to attach them to the 'regular' FPGA pins. Sorry if this makes no sense! The other high speed expansion port connections are connected to the data signals, and data-valid signals from the chips. I've created a peripheral which samples the camera data according to these clock signals, and then sampled again using the Bus2IP clock. I use a microblaze processor just to output various data. On the scope, my clock signals seem to have a period of 16ns, is this too fast for what I want to do? The voltage swing is about 600mV. My design doesn't seem to be working! Just wondered if anyone had any suggestions comments on how best to debug and proceed.

On Jan 3, 9:57=A0am, Andy <jonesa...@comcast.net> wrote: > On Jan 3, 7:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > <FPG...@gmail.com> wrote in message > > >news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.com...= >Iwould like to know which round,fix and floor algorithm would be best > > > to be implemented on an FPGA. I am working on a DSP project. I want to= > > > write funtions in VHDL which can be called and would return the round,= > > > fix and floor value of integers. > > > I'm missing something. How do you 'round' or 'floor' an integer? They > > already are, aren't they? > > Cheers, Syms. > > For integers, I think it should be approached as round(), ceil() or > floor() of a ratio of two integers, since rational numbers (including > rational approximations of non-rational numbers) are the primary > issue, not integers. Unsigned integer division uses floor anyway. I've > implemented unsigned ceil(n/d) before as (n + d - 1) / d, used for > constants only (no synthesized hardware created). I haven't tried it, > but I suppose something like (n + d / 2) / d would work for unsigned > round()? It makes my head hurt to think about signed versions of > these... > > In hardware, bit operations are probably more efficient (i.e. perform > a fixed point division, and add one if the fraction msb is set for > round(), or if any fraction bits are set for ceil(), then truncate the > fraction. Anyone looked at the fixed point package to see how they do > it? > > Andy I want to implement Round Half Up algorithm in FPGA's. The inputs are in the form unsigned_logic_vector having a bit width "bw1". Output is return unsigned_logic_vector of width "bw2". I would like to know how to implement this. I am not sure, but i guess I have to add a '10' after the decimal point. But I dont understand one thing. How would I know where the decimal point is in a string of '1' and '0' in the input.

Do you mean binary point rather than decimal point? http://en.wikipedia.org/wiki/Binary_point Cheers, Syms.

On Jan 3, 9:29 am, FPG...@gmail.com wrote: > On Jan 3, 9:57 am, Andy <jonesa...@comcast.net> wrote: > > > > > On Jan 3, 7:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > > <FPG...@gmail.com> wrote in message > > > >news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.com...>Iwouldlike to know which round,fix and floor algorithm would be best > > > > to be implemented on an FPGA. I am working on a DSP project. I want to > > > > write funtions in VHDL which can be called and would return the round, > > > > fix and floor value of integers. > > > > I'm missing something. How do you 'round' or 'floor' an integer? They > > > already are, aren't they? > > > Cheers, Syms. > > > For integers, I think it should be approached as round(), ceil() or > > floor() of a ratio of two integers, since rational numbers (including > > rational approximations of non-rational numbers) are the primary > > issue, not integers. Unsigned integer division uses floor anyway. I've > > implemented unsigned ceil(n/d) before as (n + d - 1) / d, used for > > constants only (no synthesized hardware created). I haven't tried it, > > but I suppose something like (n + d / 2) / d would work for unsigned > > round()? It makes my head hurt to think about signed versions of > > these... > > > In hardware, bit operations are probably more efficient (i.e. perform > > a fixed point division, and add one if the fraction msb is set for > > round(), or if any fraction bits are set for ceil(), then truncate the > > fraction. Anyone looked at the fixed point package to see how they do > > it? > > > Andy > > I want to implement Round Half Up algorithm in FPGA's. The inputs are > in the form unsigned_logic_vector having a bit width "bw1". Output is > return unsigned_logic_vector of width "bw2". I would like to know how > to implement this. I am not sure, but i guess I have to add a '10' > after the decimal point. But I dont understand one thing. How would I > know where the decimal point is in a string of '1' and '0' in the > input. Using std_logic_vector, signed or unsigned types, you just have to keep track of the binary point yourself. That's the beauty of the fixed point package and sfixed or ufixed types: bit 0 is always lsb of integer, bit -1 is msb of fraction. Positive bit indexes are the integer, and negative ones are the fraction. Andy

Habib Bouaziz-Viallet <habib@rigel.systems> wrote: ... > >>>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter Please edit your quote to keep it readable -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Jan 3, 10:37=A0am, Andy <jonesa...@comcast.net> wrote: > On Jan 3, 9:29 am, FPG...@gmail.com wrote: > > > > > > > On Jan 3, 9:57 am, Andy <jonesa...@comcast.net> wrote: > > > > On Jan 3, 7:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > > > <FPG...@gmail.com> wrote in message > > > > >news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.co= m...>Iwouldliketo know which round,fix and floor algorithm would be best > > > > > to be implemented on an FPGA. I am working on a DSP project. I wan= t to > > > > > write funtions in VHDL which can be called and would return the ro= und, > > > > > fix and floor value of integers. > > > > > I'm missing something. How do you 'round' or 'floor' an integer? The= y > > > > already are, aren't they? > > > > Cheers, Syms. > > > > For integers, I think it should be approached as round(), ceil() or > > > floor() of a ratio of two integers, since rational numbers (including > > > rational approximations of non-rational numbers) are the primary > > > issue, not integers. Unsigned integer division uses floor anyway. I've= > > > implemented unsigned ceil(n/d) before as (n + d - 1) / d, used for > > > constants only (no synthesized hardware created). I haven't tried it, > > > but I suppose something like (n + d / 2) / d would work for unsigned > > > round()? It makes my head hurt to think about signed versions of > > > these... > > > > In hardware, bit operations are probably more efficient (i.e. perform > > > a fixed point division, and add one if the fraction msb is set for > > > round(), or if any fraction bits are set for ceil(), then truncate the= > > > fraction. Anyone looked at the fixed point package to see how they do > > > it? > > > > Andy > > > I want to implement Round Half Up algorithm in FPGA's. The inputs are > > in the form unsigned_logic_vector having a bit width "bw1". Output is > > return unsigned_logic_vector of width "bw2". I would like to know how > > to implement this. I am not sure, but i guess I have to add a '10' > > after the decimal point. But I dont understand one thing. How would I > > know where the decimal point is in a string of '1' and '0' in the > > input. > > Using std_logic_vector, signed or unsigned types, you just have to > keep track of the binary point yourself. > > That's the beauty of the fixed point package and sfixed or ufixed > types: bit 0 is always lsb of integer, bit -1 is msb of fraction. > Positive bit indexes are the integer, and negative ones are the > fraction. > > Andy- Hide quoted text - > > - Show quoted text - It's always helped me to comment my code where I use a fixed-point numbers, showing where the binary point is I describe the number as "Qx.y", where x is the umber of integral bits (including sign), and y is the number of fractional bits. Something like: signal x : signed(15 downto 0); -- Q1.15 signal y : signed(15 downto 0); -- Q1.15 signal z : signed(31 downto 0); -- Q2.30 signal a : signed(16 downto 0); -- Q2.15 =2E.. z <=3D x * y; -- Q1.15 * Q1.15 =3D Q2.30 a <=3D x + y; -- Q1.15 + Q1.15 =3D Q2.15 (to avoid overflow) Dave

On Jan 3, 10:58=A0am, Dave <dhsch...@gmail.com> wrote: > On Jan 3, 10:37=A0am, Andy <jonesa...@comcast.net> wrote: > > > > > > > On Jan 3, 9:29 am, FPG...@gmail.com wrote: > > > > On Jan 3, 9:57 am, Andy <jonesa...@comcast.net> wrote: > > > > > On Jan 3, 7:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > > > > <FPG...@gmail.com> wrote in message > > > > > >news:360692c0-6368-485b-bb36-42c9d33a8204@h11g2000prf.googlegroups.= com...>Iwouldliketoknow which round,fix and floor algorithm would be best > > > > > > to be implemented on an FPGA. I am working on a DSP project. I w= ant to > > > > > > write funtions in VHDL which can be called and would return the = round, > > > > > > fix and floor value of integers. > > > > > > I'm missing something. How do you 'round' or 'floor' an integer? T= hey > > > > > already are, aren't they? > > > > > Cheers, Syms. > > > > > For integers, I think it should be approached as round(), ceil() or > > > > floor() of a ratio of two integers, since rational numbers (includin= g > > > > rational approximations of non-rational numbers) are the primary > > > > issue, not integers. Unsigned integer division uses floor anyway. I'= ve > > > > implemented unsigned ceil(n/d) before as (n + d - 1) / d, used for > > > > constants only (no synthesized hardware created). I haven't tried it= , > > > > but I suppose something like (n + d / 2) / d would work for unsigned= > > > > round()? It makes my head hurt to think about signed versions of > > > > these... > > > > > In hardware, bit operations are probably more efficient (i.e. perfor= m > > > > a fixed point division, and add one if the fraction msb is set for > > > > round(), or if any fraction bits are set for ceil(), then truncate t= he > > > > fraction. Anyone looked at the fixed point package to see how they d= o > > > > it? > > > > > Andy > > > > I want to implement Round Half Up algorithm in FPGA's. The inputs are > > > in the form unsigned_logic_vector having a bit width "bw1". Output is > > > return unsigned_logic_vector of width "bw2". I would like to know how > > > to implement this. I am not sure, but i guess I have to add a '10' > > > after the decimal point. But I dont understand one thing. How would I > > > know where the decimal point is in a string of '1' and '0' in the > > > input. > > > Using std_logic_vector, signed or unsigned types, you just have to > > keep track of the binary point yourself. > > > That's the beauty of the fixed point package and sfixed or ufixed > > types: bit 0 is always lsb of integer, bit -1 is msb of fraction. > > Positive bit indexes are the integer, and negative ones are the > > fraction. > > > Andy- Hide quoted text - > > > - Show quoted text - > > It's always helped me to comment my code where I use a fixed-point > numbers, showing where the binary point is =A0I describe the number as > "Qx.y", where x is the umber of integral bits (including sign), and y > is the number of fractional bits. Something like: > > signal x : signed(15 downto 0); -- Q1.15 > signal y : signed(15 downto 0); -- Q1.15 > signal z : signed(31 downto 0); -- Q2.30 > signal a : signed(16 downto 0); -- Q2.15 > > ... > > z <=3D x * y; -- Q1.15 * Q1.15 =3D Q2.30 > a <=3D x + y; -- Q1.15 + Q1.15 =3D Q2.15 (to avoid overflow) > > Dave- Hide quoted text - > > - Show quoted text - I am still under confusion. I understand binary point. What I dont understand is if I get an input whose bit width is different than the bit width of ouptut, how will I know where the bianry point of the inout is. I am trying to write a function for floor, ceiling and round in VHDL. All these functions would have variable input and output bit widths. How will I know where the binary point of the output is? Thanks

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