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"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:60u3ffF1sialiU1@mid.individual.net... > Tony Burch schrieb: > >> http://www.burched.com/BurchED_Single_Top_Tips.pdf > Nice. But what about nr. six? > > A can't agree. AFAIK the ASIC guys do a Post Place & Route Simulation to > check for possible errors of the compiler (wrong logic optimization, maybe > wrong automatich pipeline modification etc.) But for a FPGA . . . > In many cases, a real time test is much faster and more valueable for > verification (including stress tests). > > Regards > Falk Thanks Falk! I don't disagree with you! But where the emphasis on verification is depends partly on which company you are working for. I have worked in ASIC where verification with timing simulation is "everything". You can't sign-off or tape-out untill every block has been ticked. But having said that, real time FPGA prototyping in that process is also essential to success & a better chip. I have also worked in a company that was doing only FPGA but there was a large emphasis on timing simulation. And I worket for yet another company where the primary emphasis was on real-time verification, and very little on timing simulation. I wonder if others have had similar experiences of different emphasis in different companies? I thought about what you said and I will make additions and changes to Tip Number 6 in Revision 1.1 of this the document. Thanks again. Kind regards, Anthony http://www.BurchED.com

IMHO under following assumptions, timing sim on placed and routed gatelevel netlist adds little value with great effort : [1] Design passes RTL functional sim. [2] Routed design is well constrained via static timing analysis. Note : Look at static timing analysis tool for ability to flag unconstrained paths. Xilinx trace uses -u option. Then go back and add constraints for any paths which have slipped thru crack, and rerun trace with -u option. [3] Synchronous design practices have been observed with excruciating care. In theory, the above applies to both FPGA and ASIC, but obviously the cost of any error in an ASIC is tremendous, so go thru the extra effort with an ASIC. (mostly to cover butt ... and that is the defacto standard for ASIC flow). I would be overwelmingly comfortable shipping quantity of FPGA based systems where above have been followed, and the system has undergone thermal testing. Problems with timing simulations are they run very slow, take lots of effort to set up rigorously, and (once again IMHO) have a low probability of catching errors. What type of error would a timing sim catch that have passed thru the above 3 wickets? -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant phone : 303.926.0068 email : jretta@rtc-inc.com web : www.rtc-inc.com

Hi Kyprianos, Your best bet will be to go for EAPR with ISE 9.1i SP2. I do research in partial reconfiguration and when I was at a Xilinx Partial Reconfiguration workshop in TU Delft in the Netherlands last year, the Xilinx presenter alluded to the fact that Virtex-5 FPGAs are being supported in 9.1i. PlanAhead is the front-end to EAPR and ISE, so all it really does it give you a graphical, user-friendly interface, generate the constraints files and execute the tools for you rather than using your own scripts. Austin, thanks for your reply and I believe Kyprianos did ask if which versions of the ISE and EAPR tools support Virtex-5. Apart from that, I do believe that the old Virtex (first generation) family does have some problems regarding glitchless reconfiguration? It would be great to talk to you to obtain more definitive answers from Xilinx! Were you at TU Delft (FPL2007) last August? Cheers, Shannon On Feb 7, 4:25 am, austin <aus...@xilinx.com> wrote: > Kyprianos, > > Have you read: > > http://www.xilinx.com/products/design_tools/logic_design/advanced/par... > > ? > > All Virtex parts (original through V5) "support" partial reconfiguration > (able to load new partial bitstreams while continuing to run) in > hardware. Is your question more one of what tools and what is the > recommended flow? > > Austin

It has been a while (like more than a decade ago), but I've done it in 3100 and 4000 series Xilinx FPGAs, worked perfectly all the time. Make sure you have the timing correct (it is critical as I recall), the i/o type set up correctly on the FPGA pin, and that the pull-up is correct.

FPGA wrote: > I would like some guidline on writing a function or process to > generate a sine wave and cosine wave. I want to include this into my > library. Each time this function/process is called, I would like sine > and cosines wave generated. > > Are there any functions in VHDL which would help us do so. I know > there is a function UNIFORM to generate random numbers, not sure if > there is anything available for sine and cosine. > > Your comments are appreciated. > > > Anuja what frequency? what resolution? synthesizable or testbench? andraka.com has a good cordic article on it among other things. -Jeff

austin wrote: > http://www.xilinx.com/products/design_resources/dsp_central/grouping/index.htm > > > It depends. If the processing requirement can be met with the use of a > DSP uC (like TI's family of DSP micros), then those microprocessor based > DSP engines are lower power, and lower cost. ^^^^^^^^^^^ My experience is that for a given data rate, the FPGA solution will use about 20% of the power of a microprocessor solution. That is mainly because all of the control and unused data path overhead of the microprocessor is stripped out for the unrolled pipeline used in an FPGA. That assumes the FPGA fabric is being used efficiently, which means closer to the top end of the clock envelope so that the smallest FPGA that can practically handle the task is used. That keeps the static dissipation from eating your power savings. My general guideline to customers is that if it can be done with a single microprocessor, do it there because the parts are cheaper, the design tools are more mature, and the talent required to program them is far more plentiful and cheaper. When your process starts to exceed the capacity of a single microprocessor, the FPGA starts to become more attractive.

On Feb 6, 10:05=A0pm, Jeff Cunningham <j...@sover.net> wrote: > FPGA wrote: > > I would like some guidline on writing a function or process to > > generate a sine wave and cosine wave. I want to include this into my > > library. Each time this function/process is called, I would like sine > > and cosines wave generated. > > > Are there any functions in VHDL which would help us do so. I know > > there is a function UNIFORM to generate random numbers, not sure if > > there is anything available for sine and cosine. > > > Your comments are appreciated. > > > Anuja > > what frequency? > what resolution? > synthesizable or testbench? > > andraka.com has a good cordic article on it among other things. > > -Jeff has to be synthesizable. No restriction on frequency or resolution as such.

On Feb 6, 10:05=A0pm, Jeff Cunningham <j...@sover.net> wrote: > FPGA wrote: > > I would like some guidline on writing a function or process to > > generate a sine wave and cosine wave. I want to include this into my > > library. Each time this function/process is called, I would like sine > > and cosines wave generated. > > > Are there any functions in VHDL which would help us do so. I know > > there is a function UNIFORM to generate random numbers, not sure if > > there is anything available for sine and cosine. > > > Your comments are appreciated. > > > Anuja > > what frequency? > what resolution? > synthesizable or testbench? > > andraka.com has a good cordic article on it among other things. > > -Jeff has to be synthesizable. No restriction on frequency or resolution.

FPGA wrote: > I would like some guidline on writing a function or process to > generate a sine wave and cosine wave. I want to include this into my > library. Each time this function/process is called, I would like sine > and cosines wave generated. > > Are there any functions in VHDL which would help us do so. I know > there is a function UNIFORM to generate random numbers, not sure if > there is anything available for sine and cosine. > > Your comments are appreciated. > > > Anuja Is this for a testbench or for sometihng that is going into hardware? If for a testbench, just use the math_real sin and cos functions, converting the resulting reals to the format you need to drive your hardware. If it is to be synthesized into hardware, the math_real library isn't going to help you much, as reals don't map directly into synthesizable hardware.

On Feb 6, 11:42=A0pm, Ray Andraka <r...@andraka.com> wrote: > FPGA wrote: > > I would like some guidline on writing a function or process to > > generate a sine wave and cosine wave. I want to include this into my > > library. Each time this function/process is called, I would like sine > > and cosines wave generated. > > > Are there any functions in VHDL which would help us do so. I know > > there is a function UNIFORM to generate random numbers, not sure if > > there is anything available for sine and cosine. > > > Your comments are appreciated. > > > Is this for a testbench or for sometihng that is going into hardware? > If for a testbench, just use the math_real sin and cos functions, > converting the resulting reals to the format you need to drive your > hardware. =A0If it is to be synthesized into hardware, the math_real > library isn't going to help you much, as reals don't map directly into > synthesizable hardware. Using the math_real library can do for now. I have had a look at the sin and cos functions there. I am also aware on how to conver the real format to the format I want. I intend to generate a wave. sin and cos in math_real would just generate a value for a particular input. How can i generate a sine or cos waveform. I wish to make this function parametrized as follows (not sure if this should go into a function or process) function sin (x: signed, bw : integer) return signed is x: signed input with variable bit width bw : desired bit width of output I can convert signed to real and then use "sin" function in math_real. I am still not sure on how I would generate a wave for each call. Your comments would be appreciated

I can hardly beleive, that when a single FPGA may cost up to 2000$, there is no space for a few hundred kilo- maybe megabytes of information in an age, when a terabyte costs around a few 100$s. Or does it generate such a big traffic, without return o investment? Someone tell me please the mail address of the marketing and financial freaks at Xilinx! I would like to donate them my PC and a portion of my 512kpbs bandwith for the purpuse...

On Feb 4, 7:22 pm, posedg...@yahoo.com wrote: > > I myself was confronted with such a situation and I asked this > > > question on this forum, and was contacted by S3 group who later sent > > me the tool. I used it and found it an excellent tool. > > HTH > > Seems the unmodified tool is still missing on the S3 site:http://www.s3group.com/system_ic/gnat/download_gnat/ > > Could you upload it somewhere? Hi, I had a correspondence with S-3 group and they allowed me to freely distribute Gnat tool with a comment that they don't support this tool any more. So, Any one who need this tool may contact me directly. /MH

Also worth noting that the SMPTE-292 spec is for 10 bit video, so while the SDI standards are generally 8 bit, some of the HD standards have 10 bit.

You need to run a count or phase accumulation to feed into the sin/cos function. signal phase: real; constant scale: real:= 2.0**bw; for n in 0 to 10000 loop sig <= std_logic_vector(to_signed(integer(scale*sin(phase)),bw); phase <= phase + phase_increment; wait until clk='1'; end loop; FPGA wrote: > On Feb 6, 11:42 pm, Ray Andraka <r...@andraka.com> wrote: > >>FPGA wrote: >> >>>I would like some guidline on writing a function or process to >>>generate a sine wave and cosine wave. I want to include this into my >>>library. Each time this function/process is called, I would like sine >>>and cosines wave generated. >> >>>Are there any functions in VHDL which would help us do so. I know >>>there is a function UNIFORM to generate random numbers, not sure if >>>there is anything available for sine and cosine. >> >>>Your comments are appreciated. >> >> >>Is this for a testbench or for sometihng that is going into hardware? >>If for a testbench, just use the math_real sin and cos functions, >>converting the resulting reals to the format you need to drive your >>hardware. If it is to be synthesized into hardware, the math_real >>library isn't going to help you much, as reals don't map directly into >>synthesizable hardware. > > > Using the math_real library can do for now. I have had a look at the > sin and cos functions there. I am also aware on how to conver the real > format to the format I want. I intend to generate a wave. sin and cos > in math_real would just generate a value for a particular input. How > can i generate a sine or cos waveform. I wish to make this function > parametrized as follows (not sure if this should go into a function or > process) > > function sin (x: signed, bw : integer) return signed is > > x: signed input with variable bit width > bw : desired bit width of output > > I can convert signed to real and then use "sin" function in math_real. > I am still not sure on how I would generate a wave for each call. > > Your comments would be appreciated

Bresenhams algorithm provides better results with far less accumulator bits compared to a phase accumulator. Also, the input parameters (M waves in N cycles) are very convenient in many cases. If the OP wants a sine, one option that avoids the sine computation is an oscillator: next_sin <= cos*k; next_cos <= sin*k; The constant k determines the frequency. Kolja Sulimma On 7 Feb., 09:00, Ray Andraka <r...@andraka.com> wrote: > You need to run a count or phase accumulation to feed into the sin/cos > function. > > signal phase: real; > constant scale: real:= 2.0**bw; > > for n in 0 to 10000 loop > sig <= std_logic_vector(to_signed(integer(scale*sin(phase)),bw); > phase <= phase + phase_increment; > wait until clk='1'; > end loop;

Hi NG. I would like to know if it would be possible to shutdown (cut the power) from some parts of the core logic on an FPGA while other parts are still running? Like, could I have an internal timer turning the power on/off to some calculus-logic in given time periods? So parts of my question is what happens if not all the VCC (core) pins on the chip is supplied? Is it intuitive to know which power-rails these inputs serve? Has anybody any experience with doing stuff like this and could you give my some advice/suggestions? Best Regards HG

H G schrieb: > I would like to know if it would be possible to shutdown (cut the power) > from some parts of the core logic on an FPGA while other parts are still > running? AFAIk this is not possible. When you want to save power, use a clock MUX to disable the clock. > So parts of my question is what happens if not all the VCC (core) pins on > the chip is supplied? Is it intuitive to know which power-rails these > inputs serve? They are connected internally. Regards Falk

Well FPGAs *do* hold up to megabytes of memory... configuration memory, that is. Do you want more BRAM? On Feb 7, 6:30=A0pm, fbv...@gmail.com wrote: > I can hardly beleive, that when a single FPGA may cost up to 2000$, > there is no space for a few hundred kilo- maybe megabytes of > information in an age, when a terabyte costs around a few 100$s. Or > does it generate such a big traffic, without return o investment? > Someone tell me please the mail address of the marketing and financial > freaks at Xilinx! I would like to donate them my PC and a portion of > my 512kpbs bandwith for the purpuse...

>> I can hardly beleive, that when a single FPGA may cost up to 2000$, >> there is no space for a few hundred kilo- maybe megabytes of >> information in an age, when a terabyte costs around a few 100$s. Or >> does it generate such a big traffic, without return o investment? >> Someone tell me please the mail address of the marketing and financial >> freaks at Xilinx! I would like to donate them my PC and a portion of >> my 512kpbs bandwith for the purpuse... >Well FPGAs *do* hold up to megabytes of memory... configuration >memory, that is. > >Do you want more BRAM? I think (insofar as one can make out what he's on about at all) it's a complaint about some information missing from the Xilinx web site. Mike

Hi again, Paul Boven wrote: > I'm running Webpack ISE 9.2i (just updated to 9.2.04i/J40) on Suse10.1. > However, trying to actually simulate the design returns "Simulator error > > Parsing "counter_beh.prj": 0.02 > Building counter_isim_beh.exe > ERROR:Simulator:607 - ISE Simulator is unable to elaborate this design > due to specific coding constructs used in the design. Xilinx is actively > working on reducing the number of conditions where this error occurs. > For more information on this error, please consult Answer Record 24067 > in Answers Database at http://www.xilinx.com/support. Follow up: I've installed the same ISE9.2i on Ubuntu (Gutsy Gibbon) on my laptop, and here simulation does work as expected. But the laptop doesn't have a parallel port, so I'm still interested in getting everything working on just one system. Regards, Paul Boven.

On Feb 7, 9:46=A0pm, MikeShepherd...@btinternet.com wrote: > >> I can hardly beleive, that when a single FPGA may cost up to 2000$, > >> there is no space for a few hundred kilo- maybe megabytes of > >> information in an age, when a terabyte costs around a few 100$s. Or > >> does it generate such a big traffic, without return o investment? > >> Someone tell me please the mail address of the marketing and financial > >> freaks at Xilinx! I would like to donate them my PC and a portion of > >> my 512kpbs bandwith for the purpuse... > >Well FPGAs *do* hold up to megabytes of memory... configuration > >memory, that is. > > >Do you want more BRAM? > > I think (insofar as one can make out what he's on about at all) it's a > complaint about some information missing from the Xilinx web site. > > Mike Ah I see that could be a more viable interpretation! Heh heh. Reminds me of something a certain someone said during a keynote in FPL2008... hmm.

On Feb 7, 12:08=A0am, "Tony Burch" <t...@burched.com.au> wrote: > Hi all, > I thought I would share this report that I just wrote called "Single Top > FPGA Tips".http://www.burched.com/BurchED_Single_Top_Tips.pdf > > It's a bit different to your normal "Top Ten Tips" or "Favourite Recipes" > because I tried to write a single tip for each level of FPGA designer, rig= ht > through from "not yet started" to "experienced". > > I hope you enjoy it! > Kind regards, > Anthony Burch Very informative..! Thanks Tony. Slightly off topic, but what's going on with BurchEd? I've been wanting to get one of your boards for some time...

On Feb 6, 10:24 pm, hemulli...@aol.com wrote: > Hey guys, > Be careful when using Virtex5 for SONET. The RocketIO tile only > has 1 PLL used for transmit and receive on both bidirectional ports. > This PLL is normally sync'd to the local reference so the transmit > data is on the local clock rather than the network clock (recovered > clock). This architecture leads to all sorts of problems. Xilinx is > recommending that a crystal controlled VCO oscillator be used for the > local reference per XAPP649 (old Virtex2 app note) but this entails > designing a phase comparator and analog filter. Even if you do this, > your stuck with the second transmitter sync'd to the recovered clock > of the first port. In our application we would like to use the second > port for Ethernet in a POS application (can't be done). In order to > make this work, the application software has to keep track of where > the recovered clock is coming from and the clocks from several ports > need to be muxed to select which recovered clock is used for the VCO > reference. See what I mean? I think you are correct to some extent. I have used Virtex5, for SDH/Sonet application successfully for OC3/ OC12/OC48. And in general clocking is very complicated for SDH Sonet networks. You need to transmit each interface at system clock, which needs to have stratum3 (or 3E) specifications, with all the holdover capability. So you do need to use external PLL, which can satisfy all this specs. (i.e Zarlink). So once you have this PLL, then you can give this clock to transmit PLL of GTP. I know the Transmit PLL sharing makes it little difficult, especially if you want to enable loopback, but I guess you can find work arounds for it. It has advantages because PLL being shared, saves power which can be a big factor in doing multiple interfaces designs. Also another thing to note is that, since SONET/SDH does not require 8B/10B encoding, you could just do the receive part using the GTP, but the transmit part can be implemented using normal IOs for up to OC12 interface. -- Goli

On Feb 7, 11:00=A0am, Ray Andraka <r...@andraka.com> wrote: > You need to run a count or phase accumulation to feed into the sin/cos > function. > > signal phase: real; > constant scale: real:=3D 2.0**bw; > > for n in 0 to 10000 loop > =A0 =A0 =A0 =A0 sig <=3D std_logic_vector(to_signed(integer(scale*sin(phas= e)),bw); > =A0 =A0 =A0 =A0 phase <=3D phase + phase_increment; > =A0 =A0 =A0 =A0 wait until clk=3D'1'; > end loop; > That's good, but in math_real library sin/cos generate by Tailor formula. And type real have very small size. All of this get not good sin. These can give that noise of your system will grow.

Hi everybody I had the intention to buy an ML410 board but the local Xilinx reseller told me that there is a problem concerning the ALi M1535D+ - there is no documentation given with the board. But in the documentation (ug085.pdf - ML410 Embedded Development Platform User Guide (v1.7) September 28, 2007) is stated that the datasheet is located on the documentation CDROM accompanying the board. Unfortunately this datasheet is not published on the internet (ie. under NDA). My questiion is: does this problem really exist or the resseller is wrong? if the problem exists is it possible to contact ALi (nowadays NVidia I think) to get the datasheet? Thanks in advance for answer Mehdi

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