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On Feb 11, 3:37 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > But the ROM read operation introduces a 1-clock pipeline > delay, and the state machine is written to take account > of that. If you add the ROM address and data to your > waveform view you will probably see what's going on. > > I am not terribly proud of the way my ROM-reader state > machine deals with this - the pipeline delay is handled > in a rather non-uniform way across the various states - > but as you say, it *does* work. It could be more cleanly > coded, for sure. Left as an exercise for the student... > I believe, confirmed: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap17_jb02_rom_data_delay.png testbench seems to show that 1-clock delay, and if I'm understanding the timing correctly it goes like this: rising edge clock pulse 1) gen_state goes to fetch, pc changes from 0 to 1, but AT THAT EXACT CLOCK PULSE synchronous_rom_model process would of processed with pc at 0 so rom_data is still the 84. rising edge clock pulse 2) operation goes to rom_data value 84(op_delay), gen_state goes to decode and AT THE SAME EXACT CLOCK PULSE, synchronous_rom_model will then update rom_data to the the_rom(1) value of 200. Is that how it works?Article: 138276
Regarding your clock enable fan out problem, in theory your toolchain should resolve that for you. In practice, we've been bitten by this and have gotten into the habit of creating a manual fanout through something like this: signal clk_en : std_logic_vector(5 downto 0); signal clk_en_source : std_logic; attribute ... (preserve/don't optimise attributes as required by your toolchain) clk_en <= (others =>clk_en_source); foo : entity work.my_module1 port map (ce <= clken(1)); foo2 : entity work.my_module2 port map (ce <= clken(2)); Any large modules get their own clock enables, most are shared. In a large design we have about 6 elements in our manual fanout, seems to work. ChrisArticle: 138277
WilliamGibb@gmail.com wrote: > http://www.computer-engineering.org/ps2protocol/ is a good reference > for the PS2 interface. And there's plenty of freely available PS2 cores around... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 138278
On Feb 9, 4:27=A0pm, g00dmin...@yahoo.com wrote: > Has anyone come across this problem when and XPS project is opened: > > WARNING: MDT -- Use of reposritory located at C:\Xilinx > \10.1\edk_user_repository\ is now deprecated. > It is recommended that you use Gloabl Search Path preference to > specify search paths that apply to > all projects. > > I've gone into Edit->Preference and set Global Search Path to the > project directory but I got an error saying that > the directory must be 2 levels above the drivers folder. =A0 I also > tried to set it to the edk_user_repository but got > an error message saying > > system.make:215: *** multiple target patterns. Stop. > > Thanks I set mine to C:\work\projects\EDK_repository that contains \MyProcessorIPLib\drivers \MyProcessorIPLib\pcores which is 2 levels above the drivers directory. It works OK for meArticle: 138279
On Feb 11, 3:49=A0pm, Rich Webb <bbew...@mapson.nozirev.ten> wrote: > On Wed, 11 Feb 2009 10:45:30 +0100, "GiuseppeMarullo" > > > > > > <giuseppe.maru...@nospam.iname.com> wrote: > >Hi, > >I am going to buy/build a LogicAnalyzer, I need some help > >to properly select some features. > > >My requirements: > >- absolute minimum 16 channels > >- state analysis 100 MHz minimum > >- variable theresold (TTL/3.3V absolute minimum variable is > >better) > >- memory (don't know what to search for, 32Kbit/ch minimum?) > >- UART, SPI. I2C AND 1-Wire > >- export capabilities > > >- expandable (nice to have, custom plugins) > > >So far, there are these contenders: > > >- Intronix (http://www.pctestinstruments.com/) > > =A0389USD + 120USD customs + 30USD shipping =3D 539USD! =3D > >423.794 EUR! > > =A0Probably the best, highly priced (hobbyst and customs!), > >many channels, speediest and very few memory. No 1-Wire (It > >may come in the future), no additional plugins, not > >expandable > > They may have Euro-zone resellers. Guessing that based on their having > German and French versions of the help files; a quick Google search > turns up a Swiss site, at least. Try e-mailing the Intronix support line > for info on who may be a reseller on that side of the pond. > > Note that the Intronix also includes a CAN interpreter. CANbus is pretty > useful for control and monitoring apps. > > -- > Rich Webb =A0 =A0 Norfolk, VA- Hide quoted text - > > - Show quoted text - Rich, thanks but I did my homework already, including VAT it is still in a whopping 500 EUR range, I do not question the value of the tool, by still my pockets are not that deep for a LA now. I just need something that will allow me to debug stuff with more than 8 wires and see 5 samples of a 25MHz signals, or I would have solved with Sealea or Usbee at 150USD. GiuseppeArticle: 138280
Hi 2 small problems: 1) if the Stack is left to EDK default 0x400 then transmit will always fail at 12 packets from the last packet in the TX BD ringbuffer. stack overwrite into the top of the ring. just increase the stack (make sure it is sufficient) 2) main loop makes rxFrames--, interrupt handler makes rxFrames++ nice? Well Xilinx assumes that the rxFrames++ is atomic operation on PPC? They cant be that xxx well if the problem is not fixed, you will get random freeze of the ping responder. because the interrupt will happen "in between" the rxFrames-- and the counter value will be incorrect, this will have the effect that the main loop freezes. Just disable/enable interrupts, or use other safe flaging method. Hope this may help others to save some development headache. Antti PS the Base1000-X ref design will NOT work with most SFP's with the default hard coded TEMAC setting, TIECFG bits are wrong, there are 2 solutions: 1) decrypt and patch the IP code sources (what i did) 2) wait for ISE 11.1 if your project deadline allows that (in my case this is not an option)Article: 138281
hello, I am trying to configure my Virtex 5 through Select map and I don't know how to set the Bus width. thank you .Article: 138282
>I was not clear on what I want advice on. In the Virtex4, DCMs, >according to the data sheet, need to be held in reset for 250ms. Is this an external reset, e.g. from a power supply supervisor IC?Article: 138283
On Feb 11, 7:17=A0pm, Mark McDougall <ma...@vl.com.au> wrote: > WilliamG...@gmail.com wrote: > >http://www.computer-engineering.org/ps2protocol/is a good reference > > for the PS2 interface. > > And there's plenty of freely available PS2 cores around... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 If anyone actually read the original post, they might realize he already hooked up a PS2 core to his embedded processor and wants help with the C code. He'll probably get more help on the Xilinx EDK forum.Article: 138284
On Feb 11, 11:12=A0am, naughty.z...@gmail.com wrote: > I was not clear on what I want advice on. =A0In the Virtex4, DCMs, > according to the data sheet, need to be held in reset for 250ms. =A0For > this reset that is large, what is the best way to implement that - or > is there a better way around this? =A0I'm assuming a counter would not > be a good method, as a counter for that would be large. =A0In the other > portions of the design, I was looking at using small counters to > locally reset the logic in each area rather than using one giant > global reset circuit. =A0 =A0In the DDR2 controller, it needs to not do > anything until init_done is asserted, which will then also enable > another section of the design. =A0That would be enabling a lot of logic, > which I want to know if I need to perform any specific constructs in > my code to reduce the fanout, or if the synthesis tools are actually > smart enough to handle this. I routinely use counters that are as large as you would need. The carry chain logic makes large counters fairly easy to accomplish. Of course this counter would ideally use a clock that doesn't use a DCM, but does use a BUFGMUX. In years past when I didn't have big FPGA's and needed long timeouts I used LFSR's. In a CPLD where global routing and product terms are dear, the LFSR greatly reduces the interconnect and product term usage. You can also go as far as to use a separate state machine that looks at the LFSR output serially to decode the final state. There isn't much advantage to this approach in a Virtex 4, which can easily make a 28 bit counter at 200 MHz. to get your 250 ms. As far as fanout from the init_done, the tools should handle this just fine, probably by register duplication. Regards, GaborArticle: 138285
On 12 f=E9v, 11:04, giuseppe.maru...@iname.com wrote: > On Feb 11, 3:49=A0pm, Rich Webb <bbew...@mapson.nozirev.ten> wrote: > > > > > On Wed, 11 Feb 2009 10:45:30 +0100, "GiuseppeMarullo" > > > <giuseppe.maru...@nospam.iname.com> wrote: > > >Hi, > > >I am going to buy/build a LogicAnalyzer, I need some help > > >to properly select some features. > > > >My requirements: > > >- absolute minimum 16 channels > > >- state analysis 100 MHz minimum > > >- variable theresold (TTL/3.3V absolute minimum variable is > > >better) > > >- memory (don't know what to search for, 32Kbit/ch minimum?) > > >- UART, SPI. I2C AND 1-Wire > > >- export capabilities > > > >- expandable (nice to have, custom plugins) > > > >So far, there are these contenders: > > > >- Intronix (http://www.pctestinstruments.com/) > > > =A0389USD + 120USD customs + 30USD shipping =3D 539USD! =3D > > >423.794 EUR! > > > =A0Probably the best, highly priced (hobbyst and customs!), > > >many channels, speediest and very few memory. No 1-Wire (It > > >may come in the future), no additional plugins, not > > >expandable > > > They may have Euro-zone resellers. Guessing that based on their having > > German and French versions of the help files; a quick Google search > > turns up a Swiss site, at least. Try e-mailing the Intronix support lin= e > > for info on who may be a reseller on that side of the pond. > > > Note that the Intronix also includes a CAN interpreter. CANbus is prett= y > > useful for control and monitoring apps. > > > -- > > Rich Webb =A0 =A0 Norfolk, VA- Hide quoted text - > > > - Show quoted text - > > Rich, > thanks but I did my homework already, including VAT it is still in a > whopping 500 EUR range, I do not question the value of the tool, by > still my pockets are not that deep for a LA now. I just need something > that will allow me to debug stuff with more than 8 wires and see 5 > samples of a 25MHz signals, or I would have solved with Sealea or > Usbee at 150USD. > > Giuseppe I've been using the Sump Logic Analyzer for some time now, and it is really nice (I already owned the Spartan-3 Starter Board).. The trigger system is fine, and the client software is OK. Everything is released under the GNU GPL, so you have access to source code. I've added to the client software an export to VHDL source, so I can view it in ModelSim, and use analyzer result as a testbench. One drawback is that it uses the RS232 serial port, but well, replacing it with an USB connection using something like FTDI245 USB FIFO could be done easily. Another one is that you need to protect the FPGA inputs, in my case I used a few resistors and zener diodes to clamp the input levels. My 2 cents GregArticle: 138286
Thanks for the response and input everyone.Article: 138287
Yes, this project is very interesting, I could end up using it, the only "problem" is that I don't have the board and should port it to mine, oh I am not a big fan of Java but if the client is good enough, at that price... I could add the protection stuff, could you please share your design? I think is the usual serie resistor with a double fat zeners to clip to a tolerable level the input. Parts used? Giuseppe giuseppe.marullo@NOSPAMiname.com On Feb 12, 5:04=A0pm, Gregory Estrade <gregory.estr...@gmail.com> wrote: > On 12 f=E9v, 11:04, giuseppe.maru...@iname.com wrote: > > > > > > > On Feb 11, 3:49=A0pm, Rich Webb <bbew...@mapson.nozirev.ten> wrote: > > > > On Wed, 11 Feb 2009 10:45:30 +0100, "GiuseppeMarullo" > > > > <giuseppe.maru...@nospam.iname.com> wrote: > > > >Hi, > > > >I am going to buy/build a LogicAnalyzer, I need some help > > > >to properly select some features. > > > > >My requirements: > > > >- absolute minimum 16 channels > > > >- state analysis 100 MHz minimum > > > >- variable theresold (TTL/3.3V absolute minimum variable is > > > >better) > > > >- memory (don't know what to search for, 32Kbit/ch minimum?) > > > >- UART, SPI. I2C AND 1-Wire > > > >- export capabilities > > > > >- expandable (nice to have, custom plugins) > > > > >So far, there are these contenders: > > > > >- Intronix (http://www.pctestinstruments.com/) > > > > =A0389USD + 120USD customs + 30USD shipping =3D 539USD! =3D > > > >423.794 EUR! > > > > =A0Probably the best, highly priced (hobbyst and customs!), > > > >many channels, speediest and very few memory. No 1-Wire (It > > > >may come in the future), no additional plugins, not > > > >expandable > > > > They may have Euro-zone resellers. Guessing that based on their havin= g > > > German and French versions of the help files; a quick Google search > > > turns up a Swiss site, at least. Try e-mailing the Intronix support l= ine > > > for info on who may be a reseller on that side of the pond. > > > > Note that the Intronix also includes a CAN interpreter. CANbus is pre= tty > > > useful for control and monitoring apps. > > > > -- > > > Rich Webb =A0 =A0 Norfolk, VA- Hide quoted text - > > > > - Show quoted text - > > > Rich, > > thanks but I did my homework already, including VAT it is still in a > > whopping 500 EUR range, I do not question the value of the tool, by > > still my pockets are not that deep for a LA now. I just need something > > that will allow me to debug stuff with more than 8 wires and see 5 > > samples of a 25MHz signals, or I would have solved with Sealea or > > Usbee at 150USD. > > > Giuseppe > > I've been using the Sump LogicAnalyzerfor some time now, and it is > really nice (I already owned the Spartan-3 Starter Board).. > The trigger system is fine, and the client software is OK. Everything > is released under the GNU GPL, so you have access to source code. > I've added to the client software an export to VHDL source, so I can > view it in ModelSim, and useanalyzerresult as a testbench. > One drawback is that it uses the RS232 serial port, but well, > replacing it with an USB connection using something like FTDI245 USB > FIFO could be done easily. > Another one is that you need to protect the FPGA inputs, in my case I > used a few resistors and zener diodes to clamp the input levels. > > My 2 cents > Greg- Hide quoted text - > > - Show quoted text -Article: 138288
Folks, I have been debugging this issue where the EPC16 device I use does not configure the EP2C35 (Cyclone II) device - at slightly high temperature. I can make it configure by cooling down both devices using freeze spray. This is the most fascinating and ridiculous part of the problem - how could the temperature be influencing the basic config cycle?? I am using the Passive Serial mode of configuration. The programming files are proven good. I see the nCONFIG going high followed shortly by nSTATUS and after that ... nothing. The DCLK/DATA0 lines are flatlined (DATA0 continues to remain high and DCLK continues to remain low). Obviously in this case, the CONF_DONE signal does not go high at all. See waveforms below - Ch1 =96 Yellow =96 nCONFIG Ch2 =96 Blue =96 nSTATUS Ch3 =96 Purple =96 CONF_DONE Ch4 =96 Green =96 INIT_DONE This is a bad config cycle. http://i41.tinypic.com/23ib0pl.jpg On a good config cycle (same board, freezing cold ICs)... http://i43.tinypic.com/1evt07.jpg I verified the power up sequence - the VCCIO (3.3V) powers up first (t0). The FPGA-VCCINT (1.2V) powers up at (t0 + 69.2ms). The EPC16 is set to have a POR of 100ms. So I am assuming this powers up at (t0 + 100ms). This meets the spec. I have tried 1K & 10K pullups on the INIT_CONF signal with no luck. I am seeing this on 4-5 of 30 boards. On some boards the issue is a lot more aggravated than the others. One board in particular fails at room temperature. Other boards only seem to fail @ 45-55C. I have checked to verify that the EPC16 is revC silicon. Any ideas?? PA: I have posted on some other forums without much luck - I am just casting the net wider. Thanks for your inputs. -VArticle: 138289
Hi, I am trying to use a microblaze processor to do some data processing in an FPGA application. I have had no experience with uB or embedded processors before. I have created the hardware I will need, all mapped to my dev board, and I wanted to start practicing accessing a FIFO memory/LEDs etc. just to get the feel, but I am struggling to find documentation. I don't know any of the calls to functions that need to be made to read/ write to the FIFO or access GPIO etc. Is there any non-assembly reference guide or sample code I can use to get the gist of all this? I have all the addresses mapped but don't know where to start to actually get any code written. Thanks GintsArticle: 138290
On 2$B7n(B8$BF|(B, $B>e8a(B9$B;~(B32$BJ,(B, Muzaffer Kal <k...@dspia.com> wrote: > On Sat, 7 Feb 2009 17:14:38 -0800 (PST), hartono.seti...@gmail.com > wrote: > > >Hi, I have lots (thousands) of Altera EPX880 (FlashLogic). This device > >is obsolete and the only software I know that can be used to design it > >is PLDShell Plus V5.1. Anybody know where to download it please...??? > >I contacted Altera they said they don't have it anymore... > > There seems to be a downloadable copy of version 4.0 here:http://www.pads.uwaterloo.ca/~wdbishop/ece324/PLDshell.html > > -- Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com I also have the EPX880 device and want to find the PLDshell V5.1 for development. ^-^Article: 138291
On Feb 12, 9:59=A0pm, reganirel...@gmail.com wrote: > Hi, > > I am trying to use a microblaze processor to do some data processing > in an FPGA application. I have had no experience with uB or embedded > processors before. > > I have created the hardware I will need, all mapped to my dev board, > and I wanted to start practicing accessing a FIFO memory/LEDs etc. > just to get the feel, but I am struggling to find documentation. I > don't know any of the calls to functions that need to be made to read/ > write to the FIFO or access GPIO etc. Is there any non-assembly > reference guide or sample code I can use to get the gist of all this? > I have all the addresses mapped but don't know where to start to > actually get any code written. > > Thanks > Gints http://www.xilinx.com/support/documentation/tutorials/EDK_91_MB_Tutorial.pd= f Page 30 briefly talks about Build all user applications. One can look at and modify the source code mentioned to get the gist. Writing and reading memory mapped IO can be accomplished with the use of pointers. Look up pointers in a C-Language book for more information.Article: 138292
On 12 f=E9v, 21:39, giuseppe.maru...@iname.com wrote: > Yes, > this project is very interesting, I could end up using it, the only > "problem" is that I don't have the board and should port it to mine, > oh I am not a big fan of Java but if the client is good enough, at > that price... > > I could add the protection stuff, could you please share your design? > I think is the usual serie resistor with a double fat zeners to clip > to a tolerable level the input. Parts used? > > Giuseppe > > giuseppe.maru...@NOSPAMiname.com > On Feb 12, 5:04=A0pm, Gregory Estrade <gregory.estr...@gmail.com> wrote: > > > On 12 f=E9v, 11:04, giuseppe.maru...@iname.com wrote: > > > > On Feb 11, 3:49=A0pm, Rich Webb <bbew...@mapson.nozirev.ten> wrote: > > > > > On Wed, 11 Feb 2009 10:45:30 +0100, "GiuseppeMarullo" > > > > > <giuseppe.maru...@nospam.iname.com> wrote: > > > > >Hi, > > > > >I am going to buy/build a LogicAnalyzer, I need some help > > > > >to properly select some features. > > > > > >My requirements: > > > > >- absolute minimum 16 channels > > > > >- state analysis 100 MHz minimum > > > > >- variable theresold (TTL/3.3V absolute minimum variable is > > > > >better) > > > > >- memory (don't know what to search for, 32Kbit/ch minimum?) > > > > >- UART, SPI. I2C AND 1-Wire > > > > >- export capabilities > > > > > >- expandable (nice to have, custom plugins) > > > > > >So far, there are these contenders: > > > > > >- Intronix (http://www.pctestinstruments.com/) > > > > > =A0389USD + 120USD customs + 30USD shipping =3D 539USD! =3D > > > > >423.794 EUR! > > > > > =A0Probably the best, highly priced (hobbyst and customs!), > > > > >many channels, speediest and very few memory. No 1-Wire (It > > > > >may come in the future), no additional plugins, not > > > > >expandable > > > > > They may have Euro-zone resellers. Guessing that based on their hav= ing > > > > German and French versions of the help files; a quick Google search > > > > turns up a Swiss site, at least. Try e-mailing the Intronix support= line > > > > for info on who may be a reseller on that side of the pond. > > > > > Note that the Intronix also includes a CAN interpreter. CANbus is p= retty > > > > useful for control and monitoring apps. > > > > > -- > > > > Rich Webb =A0 =A0 Norfolk, VA- Hide quoted text - > > > > > - Show quoted text - > > > > Rich, > > > thanks but I did my homework already, including VAT it is still in a > > > whopping 500 EUR range, I do not question the value of the tool, by > > > still my pockets are not that deep for a LA now. I just need somethin= g > > > that will allow me to debug stuff with more than 8 wires and see 5 > > > samples of a 25MHz signals, or I would have solved with Sealea or > > > Usbee at 150USD. > > > > Giuseppe > > > I've been using the Sump LogicAnalyzerfor some time now, and it is > > really nice (I already owned the Spartan-3 Starter Board).. > > The trigger system is fine, and the client software is OK. Everything > > is released under the GNU GPL, so you have access to source code. > > I've added to the client software an export to VHDL source, so I can > > view it in ModelSim, and useanalyzerresult as a testbench. > > One drawback is that it uses the RS232 serial port, but well, > > replacing it with an USB connection using something like FTDI245 USB > > FIFO could be done easily. > > Another one is that you need to protect the FPGA inputs, in my case I > > used a few resistors and zener diodes to clamp the input levels. > > > My 2 cents > > Greg- Hide quoted text - > > > - Show quoted text - See here : http://www.daycounter.com/Circuits/Level-Translators/Level-Trans= lator-Zener-Clamp.gif I don't have the analyzer near me, but IIRC, I used BZX55-C3V3 diodes, and 150 ohms resistors. The Java client is minimal (I still haven't tested the latest version though), however I use it mostly to make a vhdl export, as ModelSim for instance has a more polished UI.Article: 138293
On Fri, 13 Feb 2009 02:14:18 -0800 (PST), Gregory Estrade wrote: > [I] make a vhdl export, as ModelSim >for instance has a more polished UI. You could also consider exporting VCD. That would save you the trouble of simulating your resulting VHDL, and would permit you to use free viewers such as gtkwave (or Modelsim, which has the capability to view VCD in its wave viewer). VCD is a pretty weird format, but the parts you need are probably simple enough. See http://en.wikipedia.org/wiki/Value_change_dump as a starting point. I tried a Google search for "vcd file format" and got a gazillion hits on some strange video format, which is NOT what you want! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138294
> Any ideas?? Overshoot/undershoot/ringing/noise on the active serial interface lines. How far is the serial config device away from the FPGA? Are the lines terminated at all? If you look at the clock/data lines on a scope are they clean? Does hanging a scope probe off the line make things worse/better? I would try to get a small value cap tacked on the clock line to see if that changes things. I'm a bit paranoid about noise on config device interfaces so normally place mine as close to the FPGA as possible. Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883 32/12 Hardengreen Business Park Fax: +44 131 663 8771 Dalkeith, Midlothian EH22 3NX www.nialstewartdevelopments.co.ukArticle: 138295
On 13 f=E9v, 11:32, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 13 Feb 2009 02:14:18 -0800 (PST), Gregory Estrade wrote: > > [I] make a vhdl export, as ModelSim > >for instance has a more polished UI. > > You could also consider exporting VCD. =A0That would > save you the trouble of simulating your resulting VHDL, > and would permit you to use free viewers such as > gtkwave (or Modelsim, which has the capability > to view VCD in its wave viewer). > > VCD is a pretty weird format, but the parts you need > are probably simple enough. =A0See > > http://en.wikipedia.org/wiki/Value_change_dump > > as a starting point. =A0I tried a Google search for > "vcd file format" and got a gazillion hits on some > strange video format, which is NOT what you want! > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thanks for the info, it shouldn't be too hard to add this feature too, I'll give it a try.Article: 138296
www.xilinx.com/microblaze There should be a reference guide on that page.Article: 138297
>The Java client is minimal (I still haven't tested the latest version
>though), however I use it mostly to make a vhdl export, as ModelSim
>for instance has a more polished UI.
Gregory, thanks for all the info, the client very minimal:
C:\data\laspartan3e\LogicAnalyzer-release\client>java -jar analyzer.jar
Error while invoking application: null
java.lang.reflect.InvocationTargetException
at java.awt.EventQueue.invokeAndWait(Unknown Source)
at javax.swing.SwingUtilities.invokeAndWait(Unknown Source)
at org.sump.analyzer.Loader.main(Loader.java:94)
Caused by: java.lang.Error: Do not use
org.sump.analyzer.tools.SPIProtocolAnalysis$SPIProtocolAnalysisDialog.add()
use org.sump.anal
yzer.tools.SPIProtocolAnalysis$SPIProtocolAnalysisDialog.getContentPane().add()
instead
at javax.swing.JDialog.createRootPaneException(Unknown Source)
at javax.swing.JDialog.addImpl(Unknown Source)
at java.awt.Container.add(Unknown Source)
at
org.sump.analyzer.tools.SPIProtocolAnalysis$SPIProtocolAnalysisDialog.<init>(SPIProtocolAnalysis.java:178)
at
org.sump.analyzer.tools.SPIProtocolAnalysis.init(SPIProtocolAnalysis.java:536)
at org.sump.analyzer.MainWindow.createGUI(MainWindow.java:207)
at org.sump.analyzer.MainWindow.run(MainWindow.java:401)
at java.awt.event.InvocationEvent.dispatch(Unknown Source)
at java.awt.EventQueue.dispatchEvent(Unknown Source)
at
java.awt.EventDispatchThread.pumpOneEventForHierarchy(Unknown Source)
at java.awt.EventDispatchThread.pumpEventsForHierarchy(Unknown
Source)
at java.awt.EventDispatchThread.pumpEvents(Unknown Source)
at java.awt.EventDispatchThread.pumpEvents(Unknown Source)
at java.awt.EventDispatchThread.run(Unknown Source)
Any idea?
Giuseppe
Article: 138298
Synthesize seems to be ok, but I get this on simulate behavior:
Running Fuse ...
fuse -intstyle ise -incremental -o jb02_tb_isim_beh.exe -prj
jb02_tb_beh.prj -top jb02_tb
Running : C:\Xilinx\10.1\ISE\bin\nt\unwrapped\fuse.exe -ise C:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/
uart_jb_02_goto.ise -intstyle ise -incremental -o jb02_tb_isim_beh.exe
-prj jb02_tb_beh.prj -top jb02_tb
Determining compilation order of HDL files
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
kcuart_tx.vhd
Restoring VHDL parse-tree ieee.std_logic_1164 from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/std_logic_1164.vdb
Restoring VHDL parse-tree std.standard from c:/xilinx/10.1/ise/vhdl/
hdp/nt/std/standard.vdb
Restoring VHDL parse-tree ieee.std_logic_arith from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/std_logic_arith.vdb
Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/xilinx/10.1/
ise/vhdl/hdp/nt/ieee/std_logic_unsigned.vdb
Restoring VHDL parse-tree unisim.vcomponents from c:/xilinx/10.1/ise/
vhdl/hdp/nt/unisim/unisim.vdbl
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
kcuart_rx.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
bbfifo_16x8.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
uart_tx.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
uart_rx.vhd
Analyzing VHDL file source/jb02_version_goto/data_gen.vhd
Restoring VHDL parse-tree ieee.numeric_std from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/numeric_std.vdb
Analyzing VHDL file source/jb02_version_goto/JB_Loki_Top.vhd
Analyzing VHDL file source/jb02_version_goto/jb02_tb.vhd
Saving VHDL parse-tree work.kcuart_tx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
kcuart_tx.vdb
Saving VHDL parse-tree work.kcuart_rx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
kcuart_rx.vdb
Saving VHDL parse-tree work.bbfifo_16x8 into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
bbfifo_16x8.vdb
Saving VHDL parse-tree work.uart_tx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
uart_tx.vdb
Saving VHDL parse-tree work.uart_rx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
uart_rx.vdb
Saving VHDL parse-tree work.data_gen_pkg into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
data_gen_pkg.vdb
Saving VHDL parse-tree work.data_gen into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
data_gen.vdb
Saving VHDL parse-tree work.lprj_top into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
lprj_top.vdb
Saving VHDL parse-tree work.jb02_tb into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
jb02_tb.vdb
Starting static elaboration
Restoring VHDL parse-tree unisim.lut4 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree std.textio from c:/xilinx/10.1/ise/vhdl/hdp/
nt/std/textio.vdb
Restoring VHDL parse-tree ieee.vital_timing from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/vital_timing.vdb
Restoring VHDL parse-tree ieee.vital_primitives from c:/xilinx/10.1/
ise/vhdl/hdp/nt/ieee/vital_primitives.vdb
Restoring VHDL parse-tree unisim.vpkg from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxf5 from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxf6 from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdrs from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdre from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.lut2 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.mult_and from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxcy from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.xorcy from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.lut3 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fde from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.srl16e from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fd from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdr from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Completed static elaboration
Fuse Memory Usage: 63060 Kb
Fuse CPU Usage: 1327 ms
Using precompiled package standard from library std
Using precompiled package std_logic_1164 from library ieee
Using precompiled package std_logic_arith from library ieee
Using precompiled package std_logic_unsigned from library ieee
Using precompiled package numeric_std from library ieee
Using precompiled package textio from library std
Using precompiled package vital_timing from library ieee
Using precompiled package vital_primitives from library ieee
Compiling package data_gen_pkg
Compiling package vcomponents
Compiling package vpkg
Compiling architecture lut4_v of entity lut4 [\LUT4("1110010011111111")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110010000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0001010101000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0110011000000110")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000000000001")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("1000000000000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("1011111110100000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000001000000")
\]
Compiling architecture muxf5_v of entity muxf5 [muxf5_default]
Compiling architecture muxf6_v of entity muxf6 [muxf6_default]
Compiling architecture fdrs_v of entity fdrs [\FDRS('0')\]
Compiling architecture fdre_v of entity fdre [\FDRE('0')\]
Compiling architecture lut2_v of entity lut2 [\LUT2("1000")\]
Compiling architecture mult_and_v of entity mult_and
[mult_and_default]
Compiling architecture muxcy_v of entity muxcy [muxcy_default]
Compiling architecture xorcy_v of entity xorcy [xorcy_default]
Compiling architecture lut3_v of entity lut3 [\LUT3("00010000")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("10010100")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("11000100")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("01010100")\]
Compiling architecture fde_v of entity fde [\FDE('0')\]
Compiling architecture srl16e_v of entity srl16e [\SRL16E
("0000000000000000")\]
Compiling architecture fd_v of entity fd [\FD('0')\]
Compiling architecture low_level_definition of entity kcuart_tx
[kcuart_tx_default]
Compiling architecture fdr_v of entity fdr [\FDR('0')\]
Compiling architecture low_level_definition of entity bbfifo_16x8
[bbfifo_16x8_default]
Compiling architecture macro_level_definition of entity uart_tx
[uart_tx_default]
Compiling architecture low_level_definition of entity kcuart_rx
[kcuart_rx_default]
Compiling architecture macro_level_definition of entity uart_rx
[uart_rx_default]
Compiling architecture rtl of entity data_gen [\data_gen(9,
(84,200,77,32,32,32,...]
Compiling architecture behavorial of entity lprj_top
[lprj_top_default]
Compiling architecture behavior of entity jb02_tb
ERROR:Simulator - Failed to link the design. Check to see if any
previous simulation executables are still running.
I added this code:
------------------------------------------------------------------------
-- A LABEL is a marker, a noop, but used for the GOTOL
constant op_LABEL : t_ubyte := 176; --NON standard ascii char.
subtype t_lbl_r is integer range 0 to 15; -- 16 labels are
availabe for now.
subtype t_lbl is t_ubyte_array(t_lbl_r);
function find_label(pgm: t_ubyte_array) return t_lbl is
constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
variable it: t_lbl;
begin
it := (others => 0);
for i in 0 to (p'length-2) loop
if (p(i)= op_label) then
it(p(i)) := i;
end if;
end loop;
return it;
end;
constant the_label: t_lbl := find_label(the_program);
------------------------------------------------------------------------------------
to working and simulating code that had t_ubyte_array
already working:
------------------------------------
subtype t_ubyte is integer range 0 to 255;
--
-- and an array of those things.
type t_ubyte_array is array(natural range <>) of t_ubyte;
-- Function to convert the generic value into ROM-contents format
function contents(pgm: t_ubyte_array) return t_rom is
constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
variable it: t_rom;
begin
it := (others => 0);
for i in p'range loop
it(i) := p(i);
end loop;
return it;
end;
-----------------------------------
Any ideas?
Article: 138299
Fixed, wrong installation setup.
Now I need a sample file, anyone willing to share one? This will help me
to check if I could use this instead of purchase one.
TIA,
Giuseppe
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