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Messages from 140900

Article: 140900
Subject: Re: Old School Altera MAX 7000
From: "Gerry_MAN" <gerryob@digital-circuitry.com>
Date: Thu, 28 May 2009 22:21:40 -0500
Links: << >>  << T >>  << A >>
I've actually done this already with the DATA I/O Labsite programmer and it
erases the Altera chips perfectly.

But I have almost all of the components for the Altera MPU setup and now I
just want to finish the deal since I've been searching for so long, I
refuse to just quit. Plus it would be interesting to learn and use the
unit. I've done so much research on it, I really am aching to try it out.

Like I said, more of a collector at this point. :)


-Gerry 

># So anyone that knows where to get an Altera LP6 Logic Programming
>card
># please let me know. I'm willing to purchase it if the price is
>reasonable.
>
>An alternative could be to look for a Universal Pgmr on EBAY, that
>supports
>EPM7128's ?
>
>Or ask Altera for the Algorithm, hoping that someone still works there
>from
>this era ;)
>
>-jg
>
>

Article: 140901
Subject: Re: ISE USB Slave Parallel programming
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 28 May 2009 21:13:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 1:55=A0am, Cy Drellinger <c...@montana.net> wrote:
> I am putting together a small board with two programmable logic
> devices ( XC2C64A and XC3S100 ) in a daisy chain configuration. I am
> trying to set up a slave parallel programming solution through an FTDI
> FT245RL and am wondering about ISE and its ability to identify the two
> devices through this configuration. Specifically, does the FTDI driver
> make the USB channel transparent to the ISE? I am needing some
> documentation in setting up this chain. I have looked over the
> schematics for Digilent's XC3S700AN starter kit, but schematics do not
> show the USB chain for programming the FPGA. Having done an amount of
> programming on the starter kit and the response in this forum that
> chain seems flaky with ISE. Have done some reading in XAPP502 but the
> USB channel has me a bit nervous. Any help would be appreciated.
>
> Sincerely,
>
> Cy Drollinger
> Electronic Realization L.L.C.
> Bozeman, MT

ISE can only use Xilinx licensed hardware, so no support for FTdi
based cables.
if you have some usb gadget based on FTDI you need and can use only
3rd
party drivers and software, there is no ISE integration possible

Antti


Article: 140902
Subject: Re: phase locking a slow (2Mhz) signal.
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 28 May 2009 21:14:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 28, 11:27=A0pm, gabor <ga...@alacron.com> wrote:
> On May 28, 2:59=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
>
>
> > On May 28, 3:32 pm, doug <x...@xx.com> wrote:
>
> > > jleslie48 wrote:
> > > > On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote:
>
> > > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48
>
> > > >>>><j...@jonathanleslie.com> wrote:
>
> > > >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phas=
e
> > > >>>>>shifting function, but it goes on and says the DCM has a wide
> > > >>>>>frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz sign=
al phase
> > > >>>>>locked?
>
> > > >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I=
 want
> > > >>>>>to mimic that signal on an internal std_logic pin with the idea =
that
> > > >>>>>if the 2MHz signal on the incoming pin is ever lost, the interna=
l
> > > >>>>>std_logic pin continues the original timing as if nothing has
> > > >>>>>happened.
>
> > > >>>>>Any suggestions?
>
> > > >>>>Implement your own NCO. Basically run a high resolution counter w=
ith
> > > >>>>high speed clock and detect at which count the 2MHz signal is tog=
gling
> > > >>>>(both edges if need be) and generate an internal signal at the sa=
me
> > > >>>>count. Now even if the external signal disappears you have the co=
unt
> > > >>>>(phase) already and you can keep generating the internal signal. =
You
> > > >>>>can use this internal signal either as a clock source (ie a divid=
ed
> > > >>>>clock) or as an enable to its downstream logic.
> > > >>>>--
> > > >>>>Muzaffer Kal
>
> > > >>>>DSPIA INC.
> > > >>>>ASIC/FPGA Design Services
>
> > > >>>>http://www.dspia.com
>
> > > >>>as I've been thinking about this today I also thought to forget th=
e
> > > >>>DCM and just do it with the regular system clock. =A0The main syst=
em
> > > >>>clock will be anywhere between 25-100MHZ, and for that matter, the
> > > >>>25MHz can be 4X with the DCM. =A0so now the issue is on the rising=
 edge
> > > >>>of the inbound 2MHz clock have the internal 2mhz clock count off 5=
0
> > > >>>ticks of the 100MHz clock to do my best "phase lock"
>
> > > >>Hi Jonathan,
>
> > > >>I am currently working on the same sort of design. =A0I don't think=
 an
> > > >>NCO is the entire job. =A0What you need is a phase locked loop with=
 a
> > > >>mode of holding the last setting when the input clock is lost. =A0T=
o do
> > > >>this you need an integrator between the phase detector and the NCO
> > > >>which will accumulate and hold a value to maintain the output
> > > >>frequency when the input clock is lost. =A0The trick is this is not=
 a
> > > >>stable circuit and needs other feedback to stabilize it. =A0If you =
know
> > > >>anything about DSP, this is not a hard problem to analyze. =A0The
> > > >>integrator puts a pole on the unit circle at 1,0 which by itself is
> > > >>not stable. =A0You can add a proportional feedback element to add a=
 zero
> > > >>which can be placed very close to the pole which will stabilize it =
for
> > > >>frequencies other than near DC. =A0But we don't care about being DC
> > > >>bounded because the feedback loop will compensate for that.
>
> > > >>Rick
>
> > > > Sorry what does NCO stand for?
>
> > > It is also called a DDS for Direct Digital Synthesizer. =A0Analog dev=
ices
> > > makes a family of them. And they are very nice units. Basically they
> > > are a phase accumulator. =A0The frequency output is equal to the cloc=
k
> > > frequency times the phase count divided by the counter full scale.
> > > The big advantage is that the step size is constant and is the
> > > clock frequency divided by the counter size. =A0Thus a 24bit counter
> > > and a 16MHz clock gives a step size of 1Hz. =A0Compare this with a
> > > frequency divider where you get an output of f, f/2, f/3 etc.
> > > The downside is that there is some jitter (up to one clock period)
> > > and that makes it difficult to use in some low noise applications.
> > > The commercial devices have a sin ROM and a D/A to give a nice
> > > sine wave output. They are useful in FPGAs where you can track
> > > moving input clocks. Rick's comments above are quite correct in
> > > that you can make a PLL in the fpga digitally.
>
> > >Numerically Controlled Oscillator
>
> > >/Mikhail
>
> > Ahh, thanks again all.
>
> By the way, since I didn't see anyone else pointing this out,
> the DCM would not have worked for this as it doesn't have an
> oscillator, only delay lines. =A0So in the DCM case no input
> translates into no output.
>
> Regards,
> Gabor

actually DCM can work as oscillator :)

there are some xilinx reference design that use that feature

Antti

Article: 140903
Subject: I don't like xilinx (again)
From: Marteno Rodia <marteno_rodia@o2.pl>
Date: Thu, 28 May 2009 22:02:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,
Again I encountered (or, more precisely, my colleague) some problem
with Xilinx. As far as I understand what he is trying to do, he wants
to synthesize two different cores into one system. The problem is that
during synthesis ISE throws out some pins of one core, which are,
however, necessary because they feeds inputs of the other core.

How could this happen? Any tips? What should we check?

MR

Article: 140904
Subject: Re: I don't like xilinx (again)
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 29 May 2009 01:42:11 -0400
Links: << >>  << T >>  << A >>
1. The title of your message is not going to help you in resolving your 
problem.
2. Your description of the problem is too generic. Generally speaking the 
tools will throw out anything which is not required for final physical 
output.


/Mikhail



"Marteno Rodia" <marteno_rodia@o2.pl> wrote in message 
news:6be75ef1-0259-4bd4-bdc7-96fe12669295@3g2000yqk.googlegroups.com...
> Hello,
> Again I encountered (or, more precisely, my colleague) some problem
> with Xilinx. As far as I understand what he is trying to do, he wants
> to synthesize two different cores into one system. The problem is that
> during synthesis ISE throws out some pins of one core, which are,
> however, necessary because they feeds inputs of the other core.
>
> How could this happen? Any tips? What should we check?
>
> MR 



Article: 140905
Subject: Re: Online tool that generates parallel CRC and Scrambler
From: Jake7 <evgenist@gmail.com>
Date: Thu, 28 May 2009 23:51:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 20, 1:46=A0pm, Mark <m...@cacurry.net> wrote:
> Evgeni,
>
> Ok neat. =A0But why not just code the algorithm in straight verilog or
> VHDL, instead of C generates verilog? =A0The C generated verilog code
> is unmanageable.
>
> CRC, and LFSR algorithms are the top of the list for implenting in
> hardware (i.e. HDLs) rather than C. =A0C implementations are messy.
>
> You don't need to calculate "one-bit per clock" - rather one-bit per
> ITERATION. =A0Who says each iteration must be a clock tick? =A0Just
> implement the procedural code for the logic update of one bit and
> stick a 'for' loop around it for 'n' bits. =A0Boom, done. =A0Let
> the synthesis tool optimize, and produce the big XOR trees.
>
> The core of the verilog code that supports any polynomial
> (width, taps), and any data size could consist of less than
> 10 lines of code.
>
> --Mark


Mark,

Actually, I've been using this algorithm coded in Verilog and running
from a simulator. Because it's a web-based tool and running on a
server it's coded in Perl. I also have versions that are coded in C
and JavaScript. It all depends on how and where it's been used.

Evgeni

Article: 140906
Subject: Re: Online tool that generates parallel CRC and Scrambler
From: Jake7 <evgenist@gmail.com>
Date: Thu, 28 May 2009 23:54:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 20, 5:43=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> In comp.arch.fpga Mark <m...@cacurry.net> wrote:
> (snip)
>
> <CRC, and LFSR algorithms are the top of the list for implenting in
> < hardware (i.e. HDLs) rather than C. =A0C implementations are messy.
>
> (snip)
>
> < The core of the verilog code that supports any polynomial
> < (width, taps), and any data size could consist of less than
> < 10 lines of code.
>
> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
> which takes up very little space. =A0You could easily generate
> many of them, also wider than 16 bits. =A0
>
> -- glen

Glen,

That's true. I didn't want the tools to generate FPGA-specific code.

Evgeni

Article: 140907
Subject: Re: Online tool that generates parallel CRC and Scrambler
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 29 May 2009 07:14:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch.fpga Jake7 <evgenist@gmail.com> wrote:
(snip, I wrote)

<> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
<> which takes up very little space. ?You could easily generate
<> many of them, also wider than 16 bits. ?
 
< That's true. I didn't want the tools to generate FPGA-specific code.

It seems that ISE is good at finding shift registers.
I don't know exactly what ISE find or doesn't find, but it
seems that the difference is efficient use of space.

-- glen

Article: 140908
Subject: Re: phase locking a slow (2Mhz) signal.
From: "Fredxx" <fredxx@spam.com>
Date: Fri, 29 May 2009 10:21:51 +0100
Links: << >>  << T >>  << A >>

"doug" <xx@xx.com> wrote in message 
news:No2dnYPnRYMPRYPXnZ2dnUVZ_uOdnZ2d@posted.docknet...
>
>>
>> Sorry what does NCO stand for?
>>
> It is also called a DDS for Direct Digital Synthesizer.  Analog devices
> makes a family of them. And they are very nice units. Basically they
> are a phase accumulator.  The frequency output is equal to the clock
> frequency times the phase count divided by the counter full scale.
> The big advantage is that the step size is constant and is the
> clock frequency divided by the counter size.  Thus a 24bit counter
> and a 16MHz clock gives a step size of 1Hz.  Compare this with a
> frequency divider where you get an output of f, f/2, f/3 etc.
> The downside is that there is some jitter (up to one clock period)
> and that makes it difficult to use in some low noise applications.
> The commercial devices have a sin ROM and a D/A to give a nice
> sine wave output. They are useful in FPGAs where you can track
> moving input clocks. Rick's comments above are quite correct in
> that you can make a PLL in the fpga digitally.

You mention jitter, but in a conventional DDS with a DAC, the output is 
filtered, such that the crossing point error becomes a fraction of a clock 
period.  The final accuracy is dependent on clock rate, DAC accuracy and 
filter.

The OP hasn't given an indication of what jitter he could tolerate.  Most 
FPGAs can accept a higher clock than 100MHz, the Spartan 3 will happily run 
at 250Mhz.

Some care should be exercised when looking at the 2MHz edges to ensure that 
the effect of metastable states are minimised.



Article: 140909
Subject: Re: Coolrunner II: what's wrong up here ?
From: gert1999 <ggddbb@gmail.com>
Date: Fri, 29 May 2009 04:24:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 28 mei, 00:35, -jg <Jim.Granvi...@gmail.com> wrote:
> On May 28, 2:09=A0am, gert1999 <ggd...@gmail.com> wrote:
>
> > I solved the problem !
> > All I had to do is adding the following timing constraints
>
> > clock period 40 ns
> > offset before clock 10 ns
> > offset after clock 10 ns
>
> > It just works and had nothing but absolutely nothing to do with the
> > code
> > I wonder why the manual did not mention anything about this ?
>
> Strange - CPLDs are usually the most timing agnostic.
> (and you'd expect the tools to take a first guess at any timing)
>
> You should be able to compare the two Fitter report files, to see just
> how the
> logic mapped, and play 'spot the difference' between the one that
> worked, and the one that failed.
>
> -jg

Reply to Rick; you got a point by saying that there is something else
wrong.  It is not simulating properly at top level and the board
displays all zero without counting.

Adding the timing constraints resulted in the fact that the dead board
comes alive and displays the zeros.

Reply to jg: it is strange but it makes a difference.  I've been
reading lot's of pdf-files that are available on the web and I found
one of them (kind of quick start example) emphesises "make sure you
add the following timing constraints"

I will compare the fitter reports and examine the code of the handbook
example.   I will rewrite the clock circuit without that structured
discription in it
I've tryed examples that exist of 1 file code with a simple counter as
divider (eg blinking led) and it works fine.   I got the feeling
something is wrong there as anual indicates some strikt values of
division are allowed, others not (will be fixed in another version and
that kind of stuff).  I got a warning on it but manual sais to ignore
it

I will leave the code up there (will keep track of version by
numbering).  I remark manual example does not drive the cathodes.  I
will experiment with lots of things and try to work it out.

Meanwhile thanks a lot for helping

Gert

Article: 140910
Subject: Re: phase locking a slow (2Mhz) signal.
From: jleslie48 <jon@jonathanleslie.com>
Date: Fri, 29 May 2009 05:24:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 5:21 am, "Fredxx" <fre...@spam.com> wrote:
> "doug" <x...@xx.com> wrote in message
>
> news:No2dnYPnRYMPRYPXnZ2dnUVZ_uOdnZ2d@posted.docknet...
>
>
>
>
>
> >> Sorry what does NCO stand for?
>
> > It is also called a DDS for Direct Digital Synthesizer.  Analog devices
> > makes a family of them. And they are very nice units. Basically they
> > are a phase accumulator.  The frequency output is equal to the clock
> > frequency times the phase count divided by the counter full scale.
> > The big advantage is that the step size is constant and is the
> > clock frequency divided by the counter size.  Thus a 24bit counter
> > and a 16MHz clock gives a step size of 1Hz.  Compare this with a
> > frequency divider where you get an output of f, f/2, f/3 etc.
> > The downside is that there is some jitter (up to one clock period)
> > and that makes it difficult to use in some low noise applications.
> > The commercial devices have a sin ROM and a D/A to give a nice
> > sine wave output. They are useful in FPGAs where you can track
> > moving input clocks. Rick's comments above are quite correct in
> > that you can make a PLL in the fpga digitally.
>
> You mention jitter, but in a conventional DDS with a DAC, the output is
> filtered, such that the crossing point error becomes a fraction of a clock
> period.  The final accuracy is dependent on clock rate, DAC accuracy and
> filter.
>
> The OP hasn't given an indication of what jitter he could tolerate.  Most
> FPGAs can accept a higher clock than 100MHz, the Spartan 3 will happily run
> at 250Mhz.
>
> Some care should be exercised when looking at the 2MHz edges to ensure that
> the effect of metastable states are minimised.

I haven't mentioned jitter because I simply do not know.  As I'm
working with a relatively slow clock of 2MHz, I can't believe that
jitter is an issue.  I'm synching a RS485 signal if that answers the
question.

So meantime, my FPGA comes with a 25MHz Oscillator chip, are you
saying there is no issue with me running it through a DCM and cranking
it up to 250MHz and using that as the system clock?


Article: 140911
Subject: Question about SERR of Xilinx PCIE core.
From: Rebecca <pang.dudu.pang@hotmail.com>
Date: Fri, 29 May 2009 07:22:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello, I am using the embedded PCIe block in Xilinx V5LX110T. The
wrapper is generated by pcie_blk_plus_v1.10, which includes some block
mems and support read/write to the mem.
I changed the UCF file to match our board. PC can detect the board and
it can be read/written. It seems working except the lspci -vv always
shows the SERR+ in the status report.
It has bothered me many days.
Any idea and recommendation are appreciated.

Thank you very much.
Rebbecca

Article: 140912
Subject: Re: When is it to generate transparent latch or usual combinational
From: Andy <jonesandy@comcast.net>
Date: Fri, 29 May 2009 07:25:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 28, 8:32=A0pm, Jacko <jackokr...@gmail.com> wrote:
>'Inferred latches for signal' is quite a
> strange phrase, maybe 'possible forgotten signal assignment' would be
> better. It only seems to be if ... then ... else ... end if; which
> generates inferred latches. case and if ... then ... end if; does not
> seem to. I guess this is because no else is definite latch/register,
> and case can contain many places of non assignment and so could flood
> the message display. It's not that strange really.

I agree, it is not that strange...

But it really has nothing to do with missing "else" statements. It
only has to do with missed assignments. Complex if/elsif or case
statements just make it much easier to miss an assignment.
Unfortunately, simply adding an "else" for every "if" is not
guaranteed to catch every missed assignment.

If combinatorial processes are needed/desired, the best coding
mechanism to ensure a latch-free implementation is to include a
default assignment for every driven signal, right up front in the
process. This is the simplest coding method to write, review, audit
and maintain, because then it simply does not matter whether you have
an "else" for every "if", or an assignment in every branch of a case
statement.

Andy

Article: 140913
Subject: Re: phase locking a slow (2Mhz) signal.
From: doug <xx@xx.com>
Date: Fri, 29 May 2009 06:52:38 -0800
Links: << >>  << T >>  << A >>


jleslie48 wrote:

> On May 29, 5:21 am, "Fredxx" <fre...@spam.com> wrote:
> 
>>"doug" <x...@xx.com> wrote in message
>>
>>news:No2dnYPnRYMPRYPXnZ2dnUVZ_uOdnZ2d@posted.docknet...
>>
>>
>>
>>
>>
>>
>>>>Sorry what does NCO stand for?
>>
>>>It is also called a DDS for Direct Digital Synthesizer.  Analog devices
>>>makes a family of them. And they are very nice units. Basically they
>>>are a phase accumulator.  The frequency output is equal to the clock
>>>frequency times the phase count divided by the counter full scale.
>>>The big advantage is that the step size is constant and is the
>>>clock frequency divided by the counter size.  Thus a 24bit counter
>>>and a 16MHz clock gives a step size of 1Hz.  Compare this with a
>>>frequency divider where you get an output of f, f/2, f/3 etc.
>>>The downside is that there is some jitter (up to one clock period)
>>>and that makes it difficult to use in some low noise applications.
>>>The commercial devices have a sin ROM and a D/A to give a nice
>>>sine wave output. They are useful in FPGAs where you can track
>>>moving input clocks. Rick's comments above are quite correct in
>>>that you can make a PLL in the fpga digitally.
>>
>>You mention jitter, but in a conventional DDS with a DAC, the output is
>>filtered, such that the crossing point error becomes a fraction of a clock
>>period.  The final accuracy is dependent on clock rate, DAC accuracy and
>>filter.
>>
>>The OP hasn't given an indication of what jitter he could tolerate.  Most
>>FPGAs can accept a higher clock than 100MHz, the Spartan 3 will happily run
>>at 250Mhz.
>>
>>Some care should be exercised when looking at the 2MHz edges to ensure that
>>the effect of metastable states are minimised.
> 
> 
> I haven't mentioned jitter because I simply do not know.  As I'm
> working with a relatively slow clock of 2MHz, I can't believe that
> jitter is an issue.  I'm synching a RS485 signal if that answers the
> question.

I am puzzled. If all you want to do is decode a serial signal, why
not just decode it with a higher speed clock as is done in a
regular UART?  If you are sending, you can generate a clock within
the tolerance of the other receiver without any trouble.

> 
> So meantime, my FPGA comes with a 25MHz Oscillator chip, are you
> saying there is no issue with me running it through a DCM and cranking
> it up to 250MHz and using that as the system clock?
> 

Article: 140914
Subject: Re: phase locking a slow (2Mhz) signal.
From: doug <xx@xx.com>
Date: Fri, 29 May 2009 06:56:23 -0800
Links: << >>  << T >>  << A >>


Fredxx wrote:

> "doug" <xx@xx.com> wrote in message 
> news:No2dnYPnRYMPRYPXnZ2dnUVZ_uOdnZ2d@posted.docknet...
> 
>>>Sorry what does NCO stand for?
>>>
>>
>>It is also called a DDS for Direct Digital Synthesizer.  Analog devices
>>makes a family of them. And they are very nice units. Basically they
>>are a phase accumulator.  The frequency output is equal to the clock
>>frequency times the phase count divided by the counter full scale.
>>The big advantage is that the step size is constant and is the
>>clock frequency divided by the counter size.  Thus a 24bit counter
>>and a 16MHz clock gives a step size of 1Hz.  Compare this with a
>>frequency divider where you get an output of f, f/2, f/3 etc.
>>The downside is that there is some jitter (up to one clock period)
>>and that makes it difficult to use in some low noise applications.
>>The commercial devices have a sin ROM and a D/A to give a nice
>>sine wave output. They are useful in FPGAs where you can track
>>moving input clocks. Rick's comments above are quite correct in
>>that you can make a PLL in the fpga digitally.
> 
> 
> You mention jitter, but in a conventional DDS with a DAC, the output is 
> filtered, such that the crossing point error becomes a fraction of a clock 
> period.  The final accuracy is dependent on clock rate, DAC accuracy and 
> filter.

This is true but it is where the hard work comes in. The job of the
filter ends up being to  interpolate the zero crossing positions
within the one clock cycle jitter.  That is why you want lots of
ROM and D/A bits plus a good analog filter outside.  This does not
work well in an fpga.  For my applications, just running the
clock signal through the FPGA on a buffer makes it to noisy
to use even with an external DDS.
> 
> The OP hasn't given an indication of what jitter he could tolerate.  Most 
> FPGAs can accept a higher clock than 100MHz, the Spartan 3 will happily run 
> at 250Mhz.
> 
> Some care should be exercised when looking at the 2MHz edges to ensure that 
> the effect of metastable states are minimised.
> 
> 

Article: 140915
Subject: Urgent help with a Simple AND simulation
From: Peter <pvrequiz@gmail.com>
Date: Fri, 29 May 2009 08:49:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everyone,
I cannot simulate a simple AND Gate

the original project:
I have downloaded the AND gate VHDL to a CPLD and it works file
without adding extra bits to simulate.
You create the ucf file and download to the CPLD and then real time
I've tested the out put and it works fine

I am getting to the AND gate project becuase I am having problem
simulating bigger VHDL code. trying to understand the basic.

When I simulate in ISim from 11.1 suite, I went step by step and I
figured out the simulation only run through the code  outputC <=
inputA and inputB; only once.

So I added a SEQ and simulater again and this time it does do back to
the VHDL file and run  outputC <= inputA and inputB; every time the
clk rising

the problem I have now is I cannot simulate a simple AND Gate in Isim
look at the tb file I have create when inputA is like the clock,
inputB is high always, but outputC is dead

Could you please help??? Thanks



This is the original project
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MyANDGate is
    Port (inputA : in  STD_LOGIC;
           inputB : in  STD_LOGIC;
           outputC : out  STD_LOGIC);
end MyANDGate;

architecture Behavioral of MyANDGate is

begin

 outputC <= inputA and inputB;

end Behavioral;

______________________________________________________

Adding bit for simulation
VHDL file

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MyANDGate is
    Port ( clk : in  STD_LOGIC;  -- simulation purpose only

				inputA : in  STD_LOGIC;
           inputB : in  STD_LOGIC;
           outputC : out  STD_LOGIC);
end MyANDGate;

architecture Behavioral of MyANDGate is


begin


SEQ: process(clk)
begin
	if (clk'event and clk = '1') then
		 outputC <= inputA and inputB;

	end if;
end process SEQ;

end Behavioral;

_______________________________________________________________

the tb file

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY MyANDGate_tb IS
END MyANDGate_tb;

ARCHITECTURE behavior OF MyANDGate_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT MyANDGate
    PORT(
			clk : in  std_logic;
         inputA : IN  std_logic;
         inputB : IN  std_logic;
         outputC : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
	signal clk : std_logic := '0';
   signal inputA : std_logic := '0';
   signal inputB : std_logic := '1';

 	--Outputs
   signal outputC : std_logic;

	constant clk_period : time :=  0.5425347us;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: MyANDGate PORT MAP (
			clk => clk,
          inputA => inputA,
          inputB => inputB,
          outputC => outputC
        );

   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   clk_process :process
   begin
		clk <= '0';
		inputA  <= '0';
		wait for clk_period/2;
		clk <= '1';
		inputA  <= '1';
		wait for clk_period/2;

end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ms.
      wait for 100ms;

      wait for clk_period*10;

      -- insert stimulus here

      wait;
   end process;

END;


Article: 140916
Subject: Re: phase locking a slow (2Mhz) signal.
From: jleslie48 <jon@jonathanleslie.com>
Date: Fri, 29 May 2009 08:51:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 10:52 am, doug <x...@xx.com> wrote:

> > I haven't mentioned jitter because I simply do not know.  As I'm
> > working with a relatively slow clock of 2MHz, I can't believe that
> > jitter is an issue.  I'm synching a RS485 signal if that answers the
> > question.
>
> I am puzzled. If all you want to do is decode a serial signal, why
> not just decode it with a higher speed clock as is done in a
> regular UART?  If you are sending, you can generate a clock within
> the tolerance of the other receiver without any trouble.
>
>

this is how I DECODE the serial signal.  I'm not trying to decode it
at this time, but rather have my fpga repeat the signal with no phase
difference when the signal is lost.

The point is my fpga is a middleware layer, and it cannot add any
phase difference to the downstream consumer of the signal. I do know
know or have control of the end consumer of the data stream.


Article: 140917
Subject: Re: phase locking a slow (2Mhz) signal.
From: doug <xx@xx.com>
Date: Fri, 29 May 2009 09:47:10 -0800
Links: << >>  << T >>  << A >>


jleslie48 wrote:

> On May 29, 10:52 am, doug <x...@xx.com> wrote:
> 
> 
>>>I haven't mentioned jitter because I simply do not know.  As I'm
>>>working with a relatively slow clock of 2MHz, I can't believe that
>>>jitter is an issue.  I'm synching a RS485 signal if that answers the
>>>question.
>>
>>I am puzzled. If all you want to do is decode a serial signal, why
>>not just decode it with a higher speed clock as is done in a
>>regular UART?  If you are sending, you can generate a clock within
>>the tolerance of the other receiver without any trouble.
>>
>>
> 
> 
> this is how I DECODE the serial signal.  I'm not trying to decode it
> at this time, but rather have my fpga repeat the signal with no phase
> difference when the signal is lost.

I see the requirement now. Decoding the signal and retransmitting it
makes it easy to deal with loss of signal but how do you deal with
reacquisition of signal and fitting that nicely into a data stream?
> 
> The point is my fpga is a middleware layer, and it cannot add any
> phase difference to the downstream consumer of the signal. I do know
> know or have control of the end consumer of the data stream.

This always makes it harder.

> 

Article: 140918
Subject: Re: I don't like xilinx (again)
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 29 May 2009 11:22:19 -0700
Links: << >>  << T >>  << A >>
Marteno Rodia wrote:

> during synthesis ISE throws out some pins of one core, which are,
> however, necessary because they feeds inputs of the other core.
> How could this happen?

If both cores are instanced, you don't need pins
on the output of the first core.
To synthesize just one core, change the top entity/module.

           -- Mike Treseler

Article: 140919
Subject: Re: Urgent help with a Simple AND simulation
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Fri, 29 May 2009 11:43:55 -0700
Links: << >>  << T >>  << A >>
Peter wrote:
> Hi everyone,
> I cannot simulate a simple AND Gate
> 
> the original project:
> I have downloaded the AND gate VHDL to a CPLD and it works file
> without adding extra bits to simulate.
> You create the ucf file and download to the CPLD and then real time
> I've tested the out put and it works fine
> 
> I am getting to the AND gate project becuase I am having problem
> simulating bigger VHDL code. trying to understand the basic.
> 
> When I simulate in ISim from 11.1 suite, I went step by step and I
> figured out the simulation only run through the code  outputC <=
> inputA and inputB; only once.
> 
> So I added a SEQ and simulater again and this time it does do back to
> the VHDL file and run  outputC <= inputA and inputB; every time the
> clk rising
> 
> the problem I have now is I cannot simulate a simple AND Gate in Isim
> look at the tb file I have create when inputA is like the clock,
> inputB is high always, but outputC is dead
> 
> Could you please help??? Thanks
> 

Look at the relationship of the CLK, inputA, inputB in the simulator.

Article: 140920
Subject: Re: phase locking a slow (2Mhz) signal.
From: jleslie48 <jon@jonathanleslie.com>
Date: Fri, 29 May 2009 12:25:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 1:47 pm, doug <x...@xx.com> wrote:
> jleslie48 wrote:
> > On May 29, 10:52 am, doug <x...@xx.com> wrote:
>
> >>>I haven't mentioned jitter because I simply do not know.  As I'm
> >>>working with a relatively slow clock of 2MHz, I can't believe that
> >>>jitter is an issue.  I'm synching a RS485 signal if that answers the
> >>>question.
>
> >>I am puzzled. If all you want to do is decode a serial signal, why
> >>not just decode it with a higher speed clock as is done in a
> >>regular UART?  If you are sending, you can generate a clock within
> >>the tolerance of the other receiver without any trouble.
>
> > this is how I DECODE the serial signal.  I'm not trying to decode it
> > at this time, but rather have my fpga repeat the signal with no phase
> > difference when the signal is lost.
>
> I see the requirement now. Decoding the signal and retransmitting it
> makes it easy to deal with loss of signal but how do you deal with
> reacquisition of signal and fitting that nicely into a data stream?
>
>
>
> > The point is my fpga is a middleware layer, and it cannot add any
> > phase difference to the downstream consumer of the signal. I do know
> > know or have control of the end consumer of the data stream.
>
> This always makes it harder.
>
>

I've created a semaphore flag to mark who is creating the output
signal to the downstream consumers.  If the inbound signal is missing,
I use the internally generated signal.  On acquisition of the inbound
signal, I set the semaphore to adjust the output signal to that, and
that [will] trigger this new ~re-sync~ the internally generated signal
to the newly aquirred inbound signal.  Should the inbound signal then
be lost, the internal signal will have already been set up to the
exact phase of the last known inbound, and so the downstream device
should be unaware of the difference (plus or minus a few clock
pulses.)   The idea is if the loss of signal is due to a wire
disconnect, when the user reconnects the wire, everything is the
same.  If he has re-cycled the power on the producer, well then the
act of re-acquisition of will reset the internally generated signal
for the new rs485 signal.


Article: 140921
Subject: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
From: rickman <gnuarm@gmail.com>
Date: Fri, 29 May 2009 12:29:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 28, 11:07 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I don't like to print download version of many documents. The download
> prints are huge and not easy to keep them in order.
>
> So that I bought Virtex-4 FPGA Handbook for $10 years ago, and I want
> to buy Virtex-5 FPGA Handbook too, but cannot find the related
> information.
>
> I also want to buy Altera's Data Handbook.
>
> I will appreciate if anyone can pose the website for these books if
> they are available.
>
> Thank you.
>
> Weng

Chip makers stopped printing manuals years ago.  You can often get
flyers and short brochures from salesmen, but otherwise, it is all
electronic.  I think it was some ten years ago that I asked a salesman
for a printed copy and he printed it off on his printer.  At that
point I gave up and came over to the dark side...

I still like my magazines in print.  It is hard to drag the keyboard
and monitor into the ... uh, reading room.  But even those are getting
smaller with links to "the complete article" on the web.

Rick

Article: 140922
Subject: Re: Online tool that generates parallel CRC and Scrambler
From: OutputLogic <evgenist@gmail.com>
Date: Fri, 29 May 2009 13:33:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 12:14=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> In comp.arch.fpga Jake7 <evgen...@gmail.com> wrote:
> (snip, I wrote)
>
> <> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
> <> which takes up very little space. ?You could easily generate
> <> many of them, also wider than 16 bits. ?
>
> < That's true. I didn't want the tools to generate FPGA-specific code.
>
> It seems that ISE is good at finding shift registers.
> I don't know exactly what ISE find or doesn't find, but it
> seems that the difference is efficient use of space.
>
> -- glen

Glen,

I observe that Xilinx ISE synthesizes shift registers (SRL16 or SRL32)
if the FFs don't have a reset, like this code:

    always @(posedge clk) begin
       reg_q2 <=3D reg_q1;
       reg_q3 <=3D reg_q2;
    end

So if your CRC/Scrambler/LFSR code doesn't have a reset, it's going to
be synthesized in the most compact way. The downside is that it would
take more effort to reset such a circuit. For example shift 0 through
the SRLs.

Evgeni

Article: 140923
Subject: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
From: gabor <gabor@alacron.com>
Date: Fri, 29 May 2009 14:30:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 29, 3:29=A0pm, rickman <gnu...@gmail.com> wrote:
> On May 28, 11:07 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
> > Hi,
> > I don't like to print download version of many documents. The download
> > prints are huge and not easy to keep them in order.
>
> > So that I bought Virtex-4 FPGA Handbook for $10 years ago, and I want
> > to buy Virtex-5 FPGA Handbook too, but cannot find the related
> > information.
>
> > I also want to buy Altera's Data Handbook.
>
> > I will appreciate if anyone can pose the website for these books if
> > they are available.
>
> > Thank you.
>
> > Weng
>
> Chip makers stopped printing manuals years ago. =A0You can often get
> flyers and short brochures from salesmen, but otherwise, it is all
> electronic. =A0I think it was some ten years ago that I asked a salesman
> for a printed copy and he printed it off on his printer. =A0At that
> point I gave up and came over to the dark side...
>
> I still like my magazines in print. =A0It is hard to drag the keyboard
> and monitor into the ... uh, reading room. =A0But even those are getting
> smaller with links to "the complete article" on the web.
>
> Rick

Sounds like it's time to drag your web-enabled mobile PC to
the "reading room" :-)

Article: 140924
Subject: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 29 May 2009 14:57:45 -0700
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:

> I don't like to print download version of many documents. The download
> prints are huge and not easy to keep them in order.

http://www.google.com/search?q=kindle+dx



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