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Messages from 145450

Article: 145450
Subject: Re: What is the most area efficient CRC method
From: OutputLogic <evgenist@gmail.com>
Date: Tue, 9 Feb 2010 21:17:03 -0800 (PST)
Links: << >>  << T >>  << A >>
There is an article in Jan '10 issue of CircuitCellar magazine ( page
40, http://www.scribd.com/doc/24890014/Circuit-Cellar-January-2010-TV
) that discusses different parallel CRC implementation methods.


Thanks,
Evgeni

Article: 145451
Subject: Re: DONE_cycle:6 setting neccessary in bitgen
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Wed, 10 Feb 2010 08:44:06 +0100
Links: << >>  << T >>  << A >>
ghelbig schrieb:
> FWIW:  I spent 3 days debugging an isse (see: "XST is driving me
> crazy" in this usenet group) that was resolved by adding one more
> clock to the startup stream.
> 
> In my configuration, done would go high and all of the combitorial
> logic would word, but none of the sequential logic would work.
> 
> One more (extra) CCLK, and everythig went working.
I know about THAT issue, but I had problems programming via iMPACT. The
thing is that I have no influence on how many CCLK cycles iMPACT
generates. It should be smart enough to know how many are needed but
obviously is not.

The only thing that helped was changing the DONE_cycle-setting, which is
something I've never had to touch before, hence it took me awhile to get
there...

cu,
Sean

-- 
Replace "MONTH" with the three-letter abbreviation of the current month
and the two-digit code for the current year (simple, eh?).

Article: 145452
Subject: Re: Spartan-3E Starter Kit reconfiguration problems
From: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?= <dincay@gmail.com>
Date: Wed, 10 Feb 2010 00:29:38 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 9, 9:09=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Hello,
>
> to talk to the SPI flash on the s3e starter kit board, I have some code t=
hat
> invokes the BSCAN_SPARTAN3 primitive and additional sets and locates
> DAC_CS =3D AMP_CS =3D SF_CE0 =3D FPGA_INIT_B =3D 1 and AD_CONV =3D0;
>
> NET "DAC_CS" LOC =3D "N8" ;
> NET "AMP_CS" LOC =3D "N7"
> NET "AD_CONV" LOC =3D "P11" ;
> NET "SF_CE0" LOC =3D "D16" ;
> NET "FPGA_INIT_B" LOC =3D "T3";
>
> That way I can talk to the SPI device after loading the bitfile via JTAG.
>
> The first SPI access however often fails.
>
> After an SPI access through that core, a press on the PROG button of the
> board still triggers reconfiguration, and the DONE leds still lights up
> after a short while, but the inital program scrolling the LCD doesn't
> start. It only starts after repowering the whole board.
>
> Any idea on what contention I hit and how I can solve?
>
> Thanks
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Do you adjust the configuration mode jumpers?

Article: 145453
Subject: Re: Spartan-3E Starter Kit reconfiguration problems
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 10 Feb 2010 10:54:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dinçay Akçören <dincay@gmail.com> wrote:
> On Feb 9, 9:09 pm, Uwe Bonnes <b...@elektron.ikp.physik.tu-

> Do you adjust the configuration mode jumpers?

No.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 145454
Subject: Re: using an FPGA to emulate a vintage computer
From: Olafur Gunnlaugsson <oli@audiotools.com>
Date: Wed, 10 Feb 2010 10:55:52 +0000
Links: << >>  << T >>  << A >>
Şann 05/02/2010 18:19, Eric Chomko skrifaği:
> Has anyone created a copy machine of an old system using an FPGA? I
> was wondering if it would be possible to take an entire SWTPC 6800 and
> compile the schematics and have it run on an FPGA board.? Wouldn't
> even have to be the latest Xylinx product, I suspect.

There are loads of such projects out there, even a commercial one called 
C-One "the reconfigurable computer", here:
http://www.c64upgra.de/c-one/


Article: 145455
Subject: Re: using an FPGA to emulate a vintage computer
From: jmfbahciv <jmfbahciv@aol>
Date: Wed, 10 Feb 2010 08:39:36 -0500
Links: << >>  << T >>  << A >>
Philipp Hachtmann wrote:
> Eric Chomko wrote:
>> Has anyone created a copy machine of an old system using an FPGA? I
> Yes, pdp8 :-)
> 
> But no front panel yet. Just a CPU with BRAM memory and teletype. Passed 
> the CPU maindecs.
> 
<grin>  What do you use for papertapes?  We used to make a "tray"
[don't remember what we called them] of papertapes which would get
shipped with the PDP-8s.  They may have been diags, or bootstrap,
or something...I can't remember what was written on the labels
right now.


/BAH

Article: 145456
Subject: Reading UDP with FPGA
From: Dek <daniele.dequal@gmail.com>
Date: Wed, 10 Feb 2010 06:04:53 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,

as the title says I have to read some information stored in UDP packet
with an FPGA. Now I'm evaluating 3 options:

1) Use an external processor and send data to FPGA through dedicated
lines
2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
since I'm working on a Xilinx)
3) Write an hardware implementation of the IP stack, or at least of he
part of the stack I need to read those packets

What are the pros and cons of each solution? Can you suggest me others
way to do that?

Thanks all

Dek

Article: 145457
Subject: Re: Reading UDP with FPGA
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 10 Feb 2010 14:18:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dek <daniele.dequal@gmail.com> wrote:
 
> as the title says I have to read some information stored in UDP packet
> with an FPGA. Now I'm evaluating 3 options:
 
> 1) Use an external processor and send data to FPGA through dedicated
> lines
> 2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
> since I'm working on a Xilinx)
> 3) Write an hardware implementation of the IP stack, or at least of he
> part of the stack I need to read those packets

UDP is much easier than TCP, so a good choice.  Other than accepting
the actual data, the complications are doing ARP.  That can easily
be done in another processor.  Any machine on the same subnet
can do it with the appropriate permanent entry in the ARP table.
If your system already has a processor on the same ethernet
but with a different network connection, this would be the easiest.

picoblaze is probably enough to send/receive ARP and otherwise
coordinate reception of the UDP data.  

It could even be done with a more ordinary state machine.  
(That would count as option 3.) 

> What are the pros and cons of each solution? Can you suggest 
> me others way to do that?

-- glen

Article: 145458
Subject: Re: Reading UDP with FPGA
From: John McCaskill <jhmccaskill@gmail.com>
Date: Wed, 10 Feb 2010 07:10:17 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 10, 8:04=A0am, Dek <daniele.deq...@gmail.com> wrote:
> Hi all,
>
> as the title says I have to read some information stored in UDP packet
> with an FPGA. Now I'm evaluating 3 options:
>
> 1) Use an external processor and send data to FPGA through dedicated
> lines
> 2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
> since I'm working on a Xilinx)
> 3) Write an hardware implementation of the IP stack, or at least of he
> part of the stack I need to read those packets
>
> What are the pros and cons of each solution? Can you suggest me others
> way to do that?
>
> Thanks all
>
> Dek



UDP is very simple.  I have some designs that use a PicoBlaze to deal
with multiple streams of UDP packets that are multicast on a Gigabit
Ethernet VLAN.  Those designs are just processing the headers and
diverting the packets of interest to the FPGA fabric for more
processing.  Everything else is sent up the Linux network stack for
the PowerPC to deal with.  If you only care about the UDP data, you
don't need to do that.

I also have designs that use the FPGA fabric to directly deal with the
data from the EMAC with out using a processor at all.  Those are only
dealing with UDP and ICMP, and were simple and straight forward.

I would go for either option 2 or 3.  I don't know enough about your
other constraints to pick between those two.

What FPGA are you using?

Regards,

John McCaskill
www.FasterTechnology.com

Article: 145459
Subject: Re: Reading UDP with FPGA
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 10 Feb 2010 15:31:43 +0000 (UTC)
Links: << >>  << T >>  << A >>
John McCaskill <jhmccaskill@gmail.com> wrote:
(snip)
 
> I also have designs that use the FPGA fabric to directly deal with the
> data from the EMAC with out using a processor at all.  Those are only
> dealing with UDP and ICMP, and were simple and straight forward.

What do you do about ARP?

You won't get the packets unless ARP tells where to send them.

-- glen

Article: 145460
Subject: Re: To get higher clock frequencies at output using propagation
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Wed, 10 Feb 2010 09:07:37 -0800
Links: << >>  << T >>  << A >>
On Tue, 09 Feb 2010 20:11:02 -0600
"Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:

> Hi,
> 
> I'm implementing this project where I've to generate higher output clk
> frequencies using DCM module. I have used a counter for delay
> generator, for propagation delays(Pls suggest if there is any other
> method). I have also instantiated the DCM module with an input freq
> of 50MHz and an output frequency of 320 MHz. I dont know how to write
> the test bench for this(or how to connect the DCM logic to the
> propagation delays to get higher output clock frequencies). I'm new
> to this technology and would highly appreciate if anyone could help
> me with this. the instantiation template is:
> dcm1 instance_name (
>     .CLKIN_IN(CLKIN_IN), 
>     .RST_IN(RST_IN), 
>     .CLKFX_OUT(CLKFX_OUT), 
>     .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
>     .CLK0_OUT(CLK0_OUT), 
>     .LOCKED_OUT(LOCKED_OUT)
>     );
> and the counter logic is:
> module Counter(Clock, Direction, Count_Out);
>     input Clock;
>     input Direction;
> 	 output [3:0] Count_Out;
>     reg [3:0] count_int = 0;
>    always @(posedge Clock)
>       if (Direction)
>          count_int <= count_int + 1;
>       else
>          count_int <= count_int - 1;
> 			
> 	assign Count_Out = count_int;		
> endmodule
> 

I know I'm going to regret this.  I know you're going to wind up being
some student misunderstanding some inane assignment.  But I'm feeling
charitable today and so, against my better judgement, I'm going to try
to walk you back out of the woods.

You're saying you need to generate higher output clock frequencies and
have delays?  Why?  What is it you're actually trying to design here?
I'm making the possibly over-generous assumption here that you're not
simply throwing logic blocks together in random assortments; what's the
actual goal that you're hoping to wind up with?  Because so far what
you're saying doesn't make any sense.  Take a step back, describe what
the project is, and maybe someone will be able to get you pointed in
the right direction.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 145461
Subject: Re: Tieing Off Unused Pins in Quartus II Blocks
From: Jim Thompson <To-Email-Use-The-Envelope-Icon@My-Web-Site.com>
Date: Wed, 10 Feb 2010 11:35:32 -0700
Links: << >>  << T >>  << A >>
On Wed, 10 Feb 2010 13:26:19 -0500, "Gary Brown"
<garyjbrown@charter.net> wrote:

>>> I am new to Altera's Quartus II.  During design I often want 
>>> to define a block's inputs and outputs but leave all or part 
>>> of the design for latter.  Unfortunately, just leaving inputs 
>>> or
>
>> In the output window click on one of the warnings, right click 
>> and
>> you can select to mask off similar warnings.
>
>That helps.
>
>>> FWIW: Has anyone else had bug problems?  In the week or so 
>>> I've been using it it faulted twice, bombed once, and 
>>> occasionly exhibited some unintentional behavior.
>>
>>
>> Not really, I've been using Quartus since it came out and it's
>> generally been very stable (specially since it became Quartus 
>> II).
>
>It hung on me yesterday - the fourth fatal bug in five days of 
>usage.  I'm a former CAD programmer also so am both sympathetic 
>and unsympathetic.
>
>> BTW comp.arch.fpga is probably a better newsgroup for this 
>> type of
>> question.
>
>Thanks for the suggestion.  Will go there.
>
>>
>> Nial.
>>
>> 
>

What I did in PSpice to cope with such no-connect/float issues was to
make a couple of _TINY_ symbols "HIGH" and "LOWW" ;-)
		
                                        ...Jim Thompson
-- 
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

Article: 145462
Subject: Re: using an FPGA to emulate a vintage computer
From: Rick <richardcortese@gmail.com>
Date: Wed, 10 Feb 2010 11:06:30 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 10, 2:55=A0am, Olafur Gunnlaugsson <o...@audiotools.com> wrote:
> =DEann 05/02/2010 18:19, Eric Chomko skrifa=F0i:
>
> > Has anyone created a copy machine of an old system using an FPGA? I
> > was wondering if it would be possible to take an entire SWTPC 6800 and
> > compile the schematics and have it run on an FPGA board.? Wouldn't
> > even have to be the latest Xylinx product, I suspect.
>
> There are loads of such projects out there, even a commercial one called
> C-One "the reconfigurable computer", here:http://www.c64upgra.de/c-one/

It is a great effort but last time I checked it was a bit pricey ~$300
for a basic system.

Just my opinion but some of the other ways of doing it will be more
successful if volume is the sole criteria. For instance all those
MP3/4 type players seem to use some variation of Rockchip or Sunplus
'System on a Chip.' In the Sunplus case it has ~160 mHz ARM processor
as the core. Currently they only emulate NES or GB, type of old system
but they certainly have the processing power and enough I/O sans
keyboard to do most 8 bit and 16 bit computers. Build quality is a
problem of course but you can pick a 4 gig system with LCD screen for
about $50.

Rick

Article: 145463
Subject: Re: using an FPGA to emulate a vintage computer
From: Charles Richmond <frizzle@tx.rr.com>
Date: Wed, 10 Feb 2010 17:35:35 -0600
Links: << >>  << T >>  << A >>
Walter Bushell wrote:
> In article <hksqmd$arq$1@news.eternal-september.org>,
>  Charles Richmond <frizzle@tx.rr.com> wrote:
> 
>> Jecel wrote:
>>> On Feb 8, 7:05 am, Gregory Estrade wrote:
>>>> You can add those too :
>>>> http://torlus.com/index.php?2007/12/05/208-oric-in-a-fpga-continued
>>>> http://torlus.com/index.php?2007/03/19/200-thomson-mo5-in-a-fpga
>>>> http://torlus.com/index.php?2007/01/31/198-hector-hrx-in-a-fpga
>>>>
>>>> Someday, I will set up a dedicated page for all these projects :)
>>> Great! This subject really needs a whole wiki to itself rather than
>>> just a page at a hard to remember address. This is on my "to do" list,
>>> but it will be a while before I get to it.
>>>
>>> -- Jecel
>> "I have discovered a truly wonderful proof of this, but the margin
>>   is too narrow to hold it."     -- Pierre de Fermat
> 
> If only someone had provided him with some butter.
> 

Par-Kay???

-- 
+----------------------------------------+
|     Charles and Francis Richmond       |
|                                        |
|  plano dot net at aquaporin4 dot com   |
+----------------------------------------+

Article: 145464
Subject: Re: Reading UDP with FPGA
From: vanepp@sfu.ca (Peter Van Epp)
Date: Thu, 11 Feb 2010 00:12:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dek <daniele.dequal@gmail.com> writes:

>Hi all,

>as the title says I have to read some information stored in UDP packet
>with an FPGA. Now I'm evaluating 3 options:

>1) Use an external processor and send data to FPGA through dedicated
>lines
>2) Use a microcontroller embedded into the FPGA (i.e. microblaze,
>since I'm working on a Xilinx)
>3) Write an hardware implementation of the IP stack, or at least of he
>part of the stack I need to read those packets

>What are the pros and cons of each solution? Can you suggest me others
>way to do that?

>Thanks all

>Dek

	How fast is the UDP stream (gig or will 10/100 and low throughput do)?
Does your board already have an ethernet PHY or do you need to add one just
for this? If the volume and speed are both low (i.e. 100 or less) there was
a spi interfaced PIC 10/100 board referenced here a while back. That may be 
your cheapest solution (the one referenced here is about $20 and Wiznet makes
a bunch more that are a little more expensive). I don't think it will do 
anywhere near wire speed, but if your traffic is small enough that may be 
the easiest solution (someone else does the IP heavy lifting such as it is and
worries about things like arp :-)). 

Peter Van Epp


Article: 145465
Subject: Re: To get higher clock frequencies at output using propagation delays.
From: "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com>
Date: Wed, 10 Feb 2010 19:22:45 -0600
Links: << >>  << T >>  << A >>
>On Tue, 09 Feb 2010 20:11:02 -0600
>"Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:
>
>> Hi,
>> 
>> I'm implementing this project where I've to generate higher output clk
>> frequencies using DCM module. I have used a counter for delay
>> generator, for propagation delays(Pls suggest if there is any other
>> method). I have also instantiated the DCM module with an input freq
>> of 50MHz and an output frequency of 320 MHz. I dont know how to write
>> the test bench for this(or how to connect the DCM logic to the
>> propagation delays to get higher output clock frequencies). I'm new
>> to this technology and would highly appreciate if anyone could help
>> me with this. the instantiation template is:
>> dcm1 instance_name (
>>     .CLKIN_IN(CLKIN_IN), 
>>     .RST_IN(RST_IN), 
>>     .CLKFX_OUT(CLKFX_OUT), 
>>     .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
>>     .CLK0_OUT(CLK0_OUT), 
>>     .LOCKED_OUT(LOCKED_OUT)
>>     );
>> and the counter logic is:
>> module Counter(Clock, Direction, Count_Out);
>>     input Clock;
>>     input Direction;
>> 	 output [3:0] Count_Out;
>>     reg [3:0] count_int = 0;
>>    always @(posedge Clock)
>>       if (Direction)
>>          count_int <= count_int + 1;
>>       else
>>          count_int <= count_int - 1;
>> 			
>> 	assign Count_Out = count_int;		
>> endmodule
>> 
>
>I know I'm going to regret this.  I know you're going to wind up being
>some student misunderstanding some inane assignment.  But I'm feeling
>charitable today and so, against my better judgement, I'm going to try
>to walk you back out of the woods.
>
>You're saying you need to generate higher output clock frequencies and
>have delays?  Why?  What is it you're actually trying to design here?
>I'm making the possibly over-generous assumption here that you're not
>simply throwing logic blocks together in random assortments; what's the
>actual goal that you're hoping to wind up with?  Because so far what
>you're saying doesn't make any sense.  Take a step back, describe what
>the project is, and maybe someone will be able to get you pointed in
>the right direction.
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>

Hello,
Thanks for the reply. This is what the project abstract says:
"FPGA devices are, in general, synchronous machines driven by a system
clock (or several clocks if multiple domains are simultaneously
implemented). Thus, the clock period is the basic unit for measuring time
properties of designs and/or to provide control signals at the outputs.
However, FPGA are equipped (at least potentially) with mechanisms providing
much finer time measurements/generation. For example, by using diversified
propagation delays within the implemented designs it is possible to
generate frequencies that are much higher than the system clock frequency.
The objective of the project is to propose and implement techniques for
generating signals (either frequencies of individual pulses) which are
below the clock period threshold. At the system level, the project consists
in determining propagation delays using programming tools (ISE platform).
At the experimental level, the estimated timing characteristics are to be
verified for repeatability, stability and consistency".
My professor has asked me to propose delay generators(I dont know what that
means). Can you please guide me on this.	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 145466
Subject: Re: To get higher clock frequencies at output using propagation
From: rickman <gnuarm@gmail.com>
Date: Wed, 10 Feb 2010 18:50:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 10, 8:22=A0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com>
wrote:
> >On Tue, 09 Feb 2010 20:11:02 -0600
> >"Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:
>
> >> Hi,
>
> >> I'm implementing this project where I've to generate higher output clk
> >> frequencies using DCM module. I have used a counter for delay
> >> generator, for propagation delays(Pls suggest if there is any other
> >> method). I have also instantiated the DCM module with an input freq
> >> of 50MHz and an output frequency of 320 MHz. I dont know how to write
> >> the test bench for this(or how to connect the DCM logic to the
> >> propagation delays to get higher output clock frequencies). I'm new
> >> to this technology and would highly appreciate if anyone could help
> >> me with this. the instantiation template is:
> >> dcm1 instance_name (
> >> =A0 =A0 .CLKIN_IN(CLKIN_IN),
> >> =A0 =A0 .RST_IN(RST_IN),
> >> =A0 =A0 .CLKFX_OUT(CLKFX_OUT),
> >> =A0 =A0 .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
> >> =A0 =A0 .CLK0_OUT(CLK0_OUT),
> >> =A0 =A0 .LOCKED_OUT(LOCKED_OUT)
> >> =A0 =A0 );
> >> and the counter logic is:
> >> module Counter(Clock, Direction, Count_Out);
> >> =A0 =A0 input Clock;
> >> =A0 =A0 input Direction;
> >> =A0 =A0 =A0 =A0 output [3:0] Count_Out;
> >> =A0 =A0 reg [3:0] count_int =3D 0;
> >> =A0 =A0always @(posedge Clock)
> >> =A0 =A0 =A0 if (Direction)
> >> =A0 =A0 =A0 =A0 =A0count_int <=3D count_int + 1;
> >> =A0 =A0 =A0 else
> >> =A0 =A0 =A0 =A0 =A0count_int <=3D count_int - 1;
>
> >> =A0 =A0 =A0 =A0assign Count_Out =3D count_int; =A0 =A0 =A0 =A0 =A0
> >> endmodule
>
> >I know I'm going to regret this. =A0I know you're going to wind up being
> >some student misunderstanding some inane assignment. =A0But I'm feeling
> >charitable today and so, against my better judgement, I'm going to try
> >to walk you back out of the woods.
>
> >You're saying you need to generate higher output clock frequencies and
> >have delays? =A0Why? =A0What is it you're actually trying to design here=
?
> >I'm making the possibly over-generous assumption here that you're not
> >simply throwing logic blocks together in random assortments; what's the
> >actual goal that you're hoping to wind up with? =A0Because so far what
> >you're saying doesn't make any sense. =A0Take a step back, describe what
> >the project is, and maybe someone will be able to get you pointed in
> >the right direction.
>
> >--
> >Rob Gaddi, Highland Technology
> >Email address is currently out of order
>
> Hello,
> Thanks for the reply. This is what the project abstract says:
> "FPGA devices are, in general, synchronous machines driven by a system
> clock (or several clocks if multiple domains are simultaneously
> implemented). Thus, the clock period is the basic unit for measuring time
> properties of designs and/or to provide control signals at the outputs.
> However, FPGA are equipped (at least potentially) with mechanisms providi=
ng
> much finer time measurements/generation. For example, by using diversifie=
d
> propagation delays within the implemented designs it is possible to
> generate frequencies that are much higher than the system clock frequency=
.
> The objective of the project is to propose and implement techniques for
> generating signals (either frequencies of individual pulses) which are
> below the clock period threshold. At the system level, the project consis=
ts
> in determining propagation delays using programming tools (ISE platform).
> At the experimental level, the estimated timing characteristics are to be
> verified for repeatability, stability and consistency".
> My professor has asked me to propose delay generators(I dont know what th=
at
> means). Can you please guide me on this. =A0 =A0 =A0 =A0 =A0


It sounds to me that your professor either does not really understand
FPGAs (in the real world) or this is just an exercise for the mind.

A delay generator is just that, a function block that just delays a
signal by some known amount of time.  But anyone who knows anything
about working with FPGAs or any other type of logic design knows that
logic delays vary over a wide range depending on the power voltage,
the chip temperature and the processing that created the chip.  The
rule of thumb I have read is that delays can vary (considering all of
the above over their full range) by a factor of 2!  This makes it very
hard to use the delays for most purposes.

The idea of using delays in the FPGA has been discussed here a number
of times and no one has ever described anything but theory.

Using a DCM is one way to reduce the minimum timing period in a way
intended by the FPGA vendors and fully supported by them.  A DCM is
capable of acting as a PLL to multiply the frequency of the supplied
clock.  This is mainly useful for running the logic at a higher rate.
I am not clear on what is meant by "generating signals (either
frequencies of individual pulses) which are below the clock period
threshold".  I think by "frequencies" he means clocks, so the DCM
should do the job here.

But whether this is what your professor wants depends on what he
intends to use it for.

Good Luck,

Rick

Article: 145467
Subject: Re: To get higher clock frequencies at output using propagation
From: -jg <jim.granville@gmail.com>
Date: Wed, 10 Feb 2010 20:23:58 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 11, 2:22=A0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com>
wrote:
> However, FPGA are equipped (at least potentially) with mechanisms providi=
ng
> much finer time measurements/generation.

This is correct.

> For example, by using diversified
> propagation delays within the implemented designs it is possible to
> generate frequencies that are much higher than the system clock frequency=
.

This is on thinner ice, as you DO need to be very clear about TIME and
FREQUENCY, and the two are not quite as interchangable as the Prof
might think.

> The objective of the project is to propose and implement techniques for
> generating signals (either frequencies of individual pulses) which are
> below the clock period threshold.

Pulse delays you can do, to sub-ns granularity, but Frequencies will
hit a practical ClockMax ceiling.
So usable Fmax is NOT 1/(delay granularity)

> At the system level, the project consists
> in determining propagation delays using programming tools (ISE platform).

You will need more than programming tools.
At the very least, a Frequency Counter.
If you scale within the FPGA (easy to do) you can use
a Sound Card + SW.

Typically you construct a ring oscillator, using a significant number
of delay/logic elements, then  measure the Frequency, and calculate
the element delay from that.

> At the experimental level, the estimated timing characteristics are to be
> verified for repeatability, stability and consistency".

Be sure to vary Voltage and temperature.

-jg


Article: 145468
Subject: Actel FPGA corePWM IP
From: RaulGonz <raullim7@hotmail.com>
Date: Thu, 11 Feb 2010 00:19:44 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

I wish to know if anyone of you out there is using an Actel FPGA board
and knows how to generate PWM signal using the corePWM IP? If you do,
please let me know as i am having a hard time trying to follow the
application note provided by actel on the corePWM. Thank you!

Article: 145469
Subject: Re: To get higher clock frequencies at output using propagation delays.
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 11 Feb 2010 10:50:25 +0100
Links: << >>  << T >>  << A >>
"Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote in message 
news:wImdnRnun5J4xu7WnZ2dnUVZ_sSdnZ2d@giganews.com...
> Hello,
> Thanks for the reply. This is what the project abstract says:
> "FPGA devices are, in general, synchronous machines driven by a system
> clock (or several clocks if multiple domains are simultaneously
> implemented). Thus, the clock period is the basic unit for measuring time
> properties of designs and/or to provide control signals at the outputs.
> However, FPGA are equipped (at least potentially) with mechanisms 
> providing
> much finer time measurements/generation. For example, by using diversified
> propagation delays within the implemented designs it is possible to
> generate frequencies that are much higher than the system clock frequency.
> The objective of the project is to propose and implement techniques for
> generating signals (either frequencies of individual pulses) which are
> below the clock period threshold. At the system level, the project 
> consists
> in determining propagation delays using programming tools (ISE platform).
> At the experimental level, the estimated timing characteristics are to be
> verified for repeatability, stability and consistency".
> My professor has asked me to propose delay generators(I dont know what 
> that
> means). Can you please guide me on this.

My initial understanding of this is that he wants to see a syncronous input 
output delay by a certain resolution higher than the sysem clk.
So if your DLL multiplies the input clk with the factor M, where M is 
limited by input clk and max dll freq, you should be able to delay a signal 
through, say one or several srl16 primitives with this systemclk*M 
resolution.
The new delayed output signal will of course be syncronous in the sysclk*M 
domain, not in the sysclk.



Article: 145470
Subject: Re: Actel FPGA corePWM IP
From: Antti <antti.lukats@googlemail.com>
Date: Thu, 11 Feb 2010 01:52:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 11, 10:19=A0am, RaulGonz <raull...@hotmail.com> wrote:
> Hi,
>
> I wish to know if anyone of you out there is using an Actel FPGA board
> and knows how to generate PWM signal using the corePWM IP? If you do,
> please let me know as i am having a hard time trying to follow the
> application note provided by actel on the corePWM. Thank you!

VERY EASY
use the mouse
put coreABC and corePWM into the design, wire up with the mouse in
smartdesign
and it just works, it does

Antti

Article: 145471
Subject: Re: using an FPGA to emulate a vintage computer
From: Huge <Huge@nowhere.much.invalid>
Date: 11 Feb 2010 09:53:00 GMT
Links: << >>  << T >>  << A >>
On 2010-02-09, Charles Richmond <frizzle@tx.rr.com> wrote:
> Charlie Gibbs wrote:
>> In article <1bd40ftplw.fsf@snowball.wb.pfeifferfamily.net>,
>> pfeiffer@cs.nmsu.edu (Joe Pfeiffer) writes:
>> 
>>> Al Kossow <aek@bitsavers.org> writes:
>>>
>>>> Reviving early computing dinosaurs from the surviving DNA is
>>>> difficult.
>>> That's a line that deserves to be put above the entrance to a
>>> computer museum.
>> 
>> "It's a Unix system!  I know this!"  -- Jurassic Park
>> 
>
> http://www.youtube.com/watch?v=dFUlAQZB9Ng

Another terrible moment in a deeply terrible movie.

I wanted the dinosaurs to kill them all. And quickly.


-- 
                             219361311
       email me, if you must, at huge {at} huge (dot) org <dot> uk]

Article: 145472
Subject: 10 layer stack for 1152 pin BGA routing (and decoupling)?
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 11 Feb 2010 10:05:07 -0000
Links: << >>  << T >>  << A >>
I'm about to start the layout on a board which I think needs
a 10 layer stack.

After the religious wars betwen rickman and Symon on decoupling I'm
unsure on the best stack but am veering towards...

1  signal - Top
2  GND plane
3  signal
4  signal
5  PWR plane
6  GND plane
7  signal
8  signal
9  PWR & GND plane
10 signal - Bottom


There will almost definitely be power pours on layer 9, the BGA
will be on the top layer.



Comments? 



Article: 145473
Subject: Re: using an FPGA to emulate a vintage computer
From: Olafur Gunnlaugsson <oli@audiotools.com>
Date: Thu, 11 Feb 2010 14:06:18 +0000
Links: << >>  << T >>  << A >>
Şann 10/02/2010 19:06, Rick skrifaği:
> On Feb 10, 2:55 am, Olafur Gunnlaugsson<o...@audiotools.com>  wrote:
>> Şann 05/02/2010 18:19, Eric Chomko skrifaği:
>>
>>> Has anyone created a copy machine of an old system using an FPGA? I
>>> was wondering if it would be possible to take an entire SWTPC 6800 and
>>> compile the schematics and have it run on an FPGA board.? Wouldn't
>>> even have to be the latest Xylinx product, I suspect.
>>
>> There are loads of such projects out there, even a commercial one called
>> C-One "the reconfigurable computer", here:http://www.c64upgra.de/c-one/
>
> It is a great effort but last time I checked it was a bit pricey ~$300
> for a basic system.
>
> Just my opinion but some of the other ways of doing it will be more
> successful if volume is the sole criteria. For instance all those
> MP3/4 type players seem to use some variation of Rockchip or Sunplus
> 'System on a Chip.' In the Sunplus case it has ~160 mHz ARM processor
> as the core. Currently they only emulate NES or GB, type of old system
> but they certainly have the processing power and enough I/O sans
> keyboard to do most 8 bit and 16 bit computers. Build quality is a
> problem of course but you can pick a 4 gig system with LCD screen for
> about $50.
>
> Rick

But the neat thing about the C-One is that it has support for what, 10 
systems in total and at the least 4 of them really good.

There is also some support for connecting to older hardware and more on 
the way I gather, but frankly it is more of a hobbyist unit than what 
you are describing

Article: 145474
Subject: Re: 10 layer stack for 1152 pin BGA routing (and decoupling)?
From: Gabor <gabor@alacron.com>
Date: Thu, 11 Feb 2010 06:16:32 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 11, 5:05=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> I'm about to start the layout on a board which I think needs
> a 10 layer stack.
>
> After the religious wars betwen rickman and Symon on decoupling I'm
> unsure on the best stack but am veering towards...
>
> 1 =A0signal - Top
> 2 =A0GND plane
> 3 =A0signal
> 4 =A0signal
> 5 =A0PWR plane
> 6 =A0GND plane
> 7 =A0signal
> 8 =A0signal
> 9 =A0PWR & GND plane
> 10 signal - Bottom
>
> There will almost definitely be power pours on layer 9, the BGA
> will be on the top layer.
>
> Comments?

If you're planning a solid plane for the "PWR plane" on
layer 5, I'd probably swap that one with layer 9 so you'd
have a solid plane near the bottom.  Otherwise you need
to be careful routing high speed signals across the plane
splits on layers 8 and 10.

Regards,
Gabor



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