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Messages from 146400

Article: 146400
Subject: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
From: luudee <rudolf.usselmann@gmail.com>
Date: Mon, 15 Mar 2010 23:41:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 16, 12:08=A0pm, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote:
> On Mar 15, 8:39=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote:
>
>
>
> > On Mar 13, 9:59=A0pm, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote:
>
> > > I googled for s g.723.1 codec ipcore for xilinx FPGA but didn't find
> > > any :(
> > > Please help!
>
> > > Mehdi
>
> > I Googled for "Next Week's Winning Lotto Numbers" and didn't find
> > those either.
>
> > Here's a couple of links for you:
> > <http://www.vhdl-online.de/tutorial/englisch/inhalt.htm>
> > <http://en.wikipedia.org/wiki/G.723.1>
>
> > RK
>
> Thanks a lot!
> I didn't know such a thing like wikipedia! Further I'll always take a
> look there before asking stupid questions!!!
> Waaaaaaaaaaaah ... VHDL is really cool!! I'll move away from
> SystemVerilog.
>
> More seriously: Before asking I made some searches in major IP core
> providers, opensource community, of course I took a look in wikipedia.
> And I don't need courses of HDL since I have already an experience of
> 8 years!! :)
> One major reason why I'm looking for IPs is that I don't want to
> beggin long administrative procedures of paying for G.723.1 patents.
> The IP provider should have done this job!! :-)
>
> Any way I would like to thank you for the effort you made :-)
>
> --
> Mehdi


I doubt you will find an IP Provide who has paid for the Patents.

Typically the end user is responsible for Patent licensing. As an
IP Provider, I can develop and offer an IP without paying for the
patents.

Best Regards,
rudi

Article: 146401
Subject: Re: Why doesn't this situation generate a latch?
From: Magne Munkejord <magnemunk@yahoo.no>
Date: Tue, 16 Mar 2010 10:04:20 +0100
Links: << >>  << T >>  << A >>
rickman wrote:

> You would think that.  I just had to change some code to eliminate a
> sync reset on a register to get rid of one level of LUTs in a Lattice
> design which has a similar if not same FF structure with the dedicated
> LSR input (Local Set/Reset).  Synplify seems to not know how to use
> that.  Maybe this would get changed by the mapper, but I don't think
> it does that.  I was looking at it in the synthesis tool.  Have you
> tried an example?  Does Synplify do a better job with the Xilinx parts
> than they do with Lattice parts?  I'm not convinced they do a good job
> with the arithmetic units.  It is more than once I've seen an adder
> chain duplicated to get the carry out of the top!

Hi Rick,

I tried 5-input registered OR, like this:

     p_sync_or : process (clk) is
     begin
         if rising_edge(clk) then
             q <= a or b or c or d or e;
         end if;
     end process p_sync_or;

In a Virtex4 (4 input LUTs) XST synthesis connects input 'e' to the set 
port of the register, and so does not require two LUTs to implement the 
gate.

When it comes to Synplify I only have the actel edition ( only actel 
parts supported(?)) and I have hardly ever used it.

I think actel parts only support async resets for their registers, in 
which case it is true as you say, that designing synchronous resets will 
generate extra logic in front of the registers. Maybe this is true for 
Lattice as well. In that case I would prefer using an async reset to 
avoid the extra logic and performance penalty.

If the reset signal is synchronously deasserted, it can be constrained 
so that one is certain it will reach each register at a proper time.

Magne


Article: 146402
Subject: Re: Awkward Arithmetic
From: Andy <jonesandy@comcast.net>
Date: Tue, 16 Mar 2010 06:04:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
Though it won't help with signed/unsigned issues, you may also want to
look at the fixed point package. It automatically promotes result
sizes to maintain accuracy for multiplication, addision and
subtraction. You can use it for "integer" math by simply specifying
your LSB index at 0. The idea is that intermediate result or operand
resizing is not usually needed with fixed point, just a final resize
prior to storage (like the implied resize that happens with integers).

I really wish they had gone the extra step to make ufixed - ufixed =
sfixed, but alas, that did not happen (not that it would be an issue
in your problem). With that, we'd have 99% of the flexibility of
integers (automatic signed and size promotion), with virtually
unlimited data sizes, at reduced simulation performance (compared to
integer, not signed/unsigned).
Andy

Article: 146403
Subject: ISE speed determined by console output?
From: HS <hugows@gmail.com>
Date: Tue, 16 Mar 2010 06:41:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi. I was wondering if console output could be "locking" ISE and if
redirecting to a file, or using flags for ISE tools to be silent could
speed things up (xst, map, par).

I use WinXP, btw.

Cheers,
hugo

Article: 146404
Subject: Re: ISE speed determined by console output?
From: d_s_klein <d_s_klein@yahoo.com>
Date: Tue, 16 Mar 2010 09:00:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 16, 5:41=A0am, HS <hug...@gmail.com> wrote:
> Hi. I was wondering if console output could be "locking" ISE and if
> redirecting to a file, or using flags for ISE tools to be silent could
> speed things up (xst, map, par).
>
> I use WinXP, btw.
>
> Cheers,
> hugo

Not enough to notice.  ISE is very CPU intensive.

RK.

Article: 146405
Subject: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
From: d_s_klein <d_s_klein@yahoo.com>
Date: Tue, 16 Mar 2010 09:06:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 15, 9:08=A0pm, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote:
>
> And I don't need courses of HDL since I have already an experience of
> 8 years!! :)
> Mehdi

Experience?  Perhaps.  Wisdom?  No.

RK


Article: 146406
Subject: Re: ISE speed determined by console output?
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Tue, 16 Mar 2010 17:13:16 +0100
Links: << >>  << T >>  << A >>
d_s_klein wrote:
> On Mar 16, 5:41 am, HS <hug...@gmail.com> wrote:
>> Hi. I was wondering if console output could be "locking" ISE and if
>> redirecting to a file, or using flags for ISE tools to be silent could
>> speed things up (xst, map, par).
>>
>> I use WinXP, btw.
>>
>> Cheers,
>> hugo
> 
> Not enough to notice.  ISE is very CPU intensive.

It depends. :)

I remember when they switched the GUI to QT (don't recall which release
that was... ISE8 maybe?), they had a background process "cat.exe" that
used up one entire CPU core. I suppose they used that to paste the
console output into the GUI window... That one would've had me rolling
on the floor laughing, hadn't it slowed down the entire process
considerably on one-core machines. Fortunately they fixed that in the
next SP, but still...

Not that I use the GUI a lot, but for some quick testing of new releases
it's handy sometimes.

cu,
Sean

-- 
Replace "MONTH" with the three-letter abbreviation of the current month
and the two-digit code for the current year (simple, eh?).

Article: 146407
Subject: Any advice on which is the best book on CMOS digital circuit design?
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 16 Mar 2010 10:10:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I want to buy books on  CMOS digital circuit designs. Any advice on
which is the best book on CMOS digital circuit design?

I know the best textbook on software programming is a book written by
MIT 4 professors "The Introduction to Algorithms".

Knuth's "The Art of Computer Programming" 1-3 volumes are good, and I
have read all of them, but they are at too low levels and cover too
limited research area.

I hope to buy the same books on CMOS digital circuit designs, even
though many experts may have different points of views.

Thank you.

Weng

Article: 146408
Subject: Xilinx Spartan6 Virtex6 Rollout
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 16 Mar 2010 13:12:04 -0700
Links: << >>  << T >>  << A >>
 Can anyone tell me where to find out what
Spartan6 and Virtex6 parts, packages, speed
grades, and costs (small quantities) are or
will be?
 I have a comparison charts from the Xilinx web
site and I try to gleen availability from the
Avnet website but this method seems like guess
work.
 Thanks,
 Brad Smallridge
 AiVision



Article: 146409
Subject: Re: Xilinx Spartan6 Virtex6 Rollout
From: austin <austin@xilinx.com>
Date: Tue, 16 Mar 2010 14:43:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
Brad,

Xilinx provides all parts through authorized distributors.

In North America, that is Avnet (as you have noted).  I suggest you
call them on the phone and request quotes and delivery.

If they say 6 weeks, then it is as good as "in stock" but if it says
26 weeks that means the die are probably in die bank, and are not
assembled into packages (yet).

Austin

Article: 146410
Subject: Spartan 3 LVDS - current mode outputs?
From: "Andrew Holme" <ah@nospam.com>
Date: Tue, 16 Mar 2010 22:59:51 -0000
Links: << >>  << T >>  << A >>
Is AR#21774 the only official statement from Xilinx on this, or have I 
missed something?

I want to mess about with non-standard load impedances.

How do they maintain the common mode voltage?  Do they string a potential 
divider between the outputs and servo the centre voltage to half-rail?

Anyone know for sure?

TIA



Article: 146411
Subject: Re: Why doesn't this situation generate a latch?
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 16 Mar 2010 17:24:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 16, 2:04=A0am, Magne Munkejord <magnem...@yahoo.no> wrote:
> rickman wrote:
> > You would think that. =A0I just had to change some code to eliminate a
> > sync reset on a register to get rid of one level of LUTs in a Lattice
> > design which has a similar if not same FF structure with the dedicated
> > LSR input (Local Set/Reset). =A0Synplify seems to not know how to use
> > that. =A0Maybe this would get changed by the mapper, but I don't think
> > it does that. =A0I was looking at it in the synthesis tool. =A0Have you
> > tried an example? =A0Does Synplify do a better job with the Xilinx part=
s
> > than they do with Lattice parts? =A0I'm not convinced they do a good jo=
b
> > with the arithmetic units. =A0It is more than once I've seen an adder
> > chain duplicated to get the carry out of the top!
>
> Hi Rick,
>
> I tried 5-input registered OR, like this:
>
> =A0 =A0 =A0p_sync_or : process (clk) is
> =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0if rising_edge(clk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0q <=3D a or b or c or d or e;
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0end process p_sync_or;
>
> In a Virtex4 (4 input LUTs) XST synthesis connects input 'e' to the set
> port of the register, and so does not require two LUTs to implement the
> gate.
>
> When it comes to Synplify I only have the actel edition ( only actel
> parts supported(?)) and I have hardly ever used it.
>
> I think actel parts only support async resets for their registers, in
> which case it is true as you say, that designing synchronous resets will
> generate extra logic in front of the registers. Maybe this is true for
> Lattice as well. In that case I would prefer using an async reset to
> avoid the extra logic and performance penalty.
>
> If the reset signal is synchronously deasserted, it can be constrained
> so that one is certain it will reach each register at a proper time.
>
> Magne

Magne,
Your method is wrong !

You cannot connect 'e' to the set port of the register. It may
compromise a new data which uses 'q'.

Imagine the case: if 'e' is so earlier asserted that 'q' is asserted
and changes a data 'New" which uses 'q' during setup or hold time
around the next clock triggering edge.Next 'New' signal data may be
invalid.

p_sync_or : process (clk) is
     begin
         if rising_edge(clk) then
             q <=3D a or b or c or d or e;
         end if;
     end process p_sync_or;

A : process(clk)
     begin
         if rising_edge(clk) then
             New <=3D a and q;
         end if;
     end process A;

Weng

Article: 146412
Subject: Re: Question Rdging xilinx chipscope pro triggering
From: saras <saras_rajgiri@yahoo.co.in>
Date: Tue, 16 Mar 2010 20:54:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 12, 6:34=A0pm, John McCaskill <jhmccask...@gmail.com> wrote:
> On Mar 12, 6:34=A0am, saras <saras_rajg...@yahoo.co.in> wrote:
>
> > hello all , I have triggered the chipscope on some error signal and is
> > getting triggered on error.But i am unable to analyse the cause of the
> > error. Is there any way we can sample the previous 20 or 50 samples
> > before trigger so that i can see which are the signals causing the
> > error ? Thanks in advance.
>
> In the trigger setup window, there is a subwindow named capture. =A0On
> the right hand side of the capture window is a field named position
> that defaults to 0. =A0Enter how many samples you want to see preceding
> the trigger in that field.
>
> Regards,
>
> John McCaskillwww.FasterTechnology.com

Thanks a lot.
But in the trigger setup window, there is no subwindow named capture.
All i have is " Enable trigger sequencer" , " Enable storage
qualification" , "trigger width" , "match type", "max number of
samples levels" , "samples depth" and then  " Net connections". I'm
using a licenesed Xilinx 10.1 version.Is there any problem with
version or some other issue? Please help.

Article: 146413
Subject: Re: Awkward Arithmetic
From: rickman <gnuarm@gmail.com>
Date: Tue, 16 Mar 2010 20:59:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 16, 9:04=A0am, Andy <jonesa...@comcast.net> wrote:
> Though it won't help with signed/unsigned issues, you may also want to
> look at the fixed point package. It automatically promotes result
> sizes to maintain accuracy for multiplication, addision and
> subtraction. You can use it for "integer" math by simply specifying
> your LSB index at 0. The idea is that intermediate result or operand
> resizing is not usually needed with fixed point, just a final resize
> prior to storage (like the implied resize that happens with integers).
>
> I really wish they had gone the extra step to make ufixed - ufixed =3D
> sfixed, but alas, that did not happen (not that it would be an issue
> in your problem). With that, we'd have 99% of the flexibility of
> integers (automatic signed and size promotion), with virtually
> unlimited data sizes, at reduced simulation performance (compared to
> integer, not signed/unsigned).
> Andy

Actually, after converting the calculation to signed/unsigned types,
it was still pretty groady, so I changed it back to integer and split
it up.  I need to optimize this design for size and I find that easier
if I separate the arithmetic functions so I can more easily see how
they are being implemented.

I had originally used integer because it make the calculations easy,
but doubted that this was the best way to express the calculations
because of the mess of converting the inputs from signed/unsigned and
back.  As it turned out mixing signed and unsigned is still pretty
messy.

Rick

Article: 146414
Subject: Re: Why doesn't this situation generate a latch?
From: rickman <gnuarm@gmail.com>
Date: Tue, 16 Mar 2010 21:07:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 16, 8:24=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Mar 16, 2:04=A0am, Magne Munkejord <magnem...@yahoo.no> wrote:
>
>
>
>
>
>
>
> > rickman wrote:
> > > You would think that. =A0I just had to change some code to eliminate =
a
> > > sync reset on a register to get rid of one level of LUTs in a Lattice
> > > design which has a similar if not same FF structure with the dedicate=
d
> > > LSR input (Local Set/Reset). =A0Synplify seems to not know how to use
> > > that. =A0Maybe this would get changed by the mapper, but I don't thin=
k
> > > it does that. =A0I was looking at it in the synthesis tool. =A0Have y=
ou
> > > tried an example? =A0Does Synplify do a better job with the Xilinx pa=
rts
> > > than they do with Lattice parts? =A0I'm not convinced they do a good =
job
> > > with the arithmetic units. =A0It is more than once I've seen an adder
> > > chain duplicated to get the carry out of the top!
>
> > Hi Rick,
>
> > I tried 5-input registered OR, like this:
>
> > =A0 =A0 =A0p_sync_or : process (clk) is
> > =A0 =A0 =A0begin
> > =A0 =A0 =A0 =A0 =A0if rising_edge(clk) then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0q <=3D a or b or c or d or e;
> > =A0 =A0 =A0 =A0 =A0end if;
> > =A0 =A0 =A0end process p_sync_or;
>
> > In a Virtex4 (4 input LUTs) XST synthesis connects input 'e' to the set
> > port of the register, and so does not require two LUTs to implement the
> > gate.
>
> > When it comes to Synplify I only have the actel edition ( only actel
> > parts supported(?)) and I have hardly ever used it.
>
> > I think actel parts only support async resets for their registers, in
> > which case it is true as you say, that designing synchronous resets wil=
l
> > generate extra logic in front of the registers. Maybe this is true for
> > Lattice as well. In that case I would prefer using an async reset to
> > avoid the extra logic and performance penalty.
>
> > If the reset signal is synchronously deasserted, it can be constrained
> > so that one is certain it will reach each register at a proper time.
>
> > Magne
>
> Magne,
> Your method is wrong !
>
> You cannot connect 'e' to the set port of the register. It may
> compromise a new data which uses 'q'.
>
> Imagine the case: if 'e' is so earlier asserted that 'q' is asserted
> and changes a data 'New" which uses 'q' during setup or hold time
> around the next clock triggering edge.Next 'New' signal data may be
> invalid.
>
> p_sync_or : process (clk) is
> =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0if rising_edge(clk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0q <=3D a or b or c or d or e;
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0end process p_sync_or;
>
> A : process(clk)
> =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0if rising_edge(clk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0New <=3D a and q;
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0end process A;
>
> Weng

I'm not clear on what your concern is.  Perhaps you are thinging Magne
is talking about e being connected to an async set?  He is describing
a FF with an async set which will do exactly the same thing as an OR
of signal e with the rest of the inputs.

Rick

Article: 146415
Subject: Re: Xilinx Spartan6 Virtex6 Rollout
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Tue, 16 Mar 2010 21:17:04 -0700
Links: << >>  << T >>  << A >>
On Tue, 16 Mar 2010 13:12:04 -0700, "Brad Smallridge"
<bradsmallridge@dslextreme.com> wrote:

> Can anyone tell me where to find out what
>Spartan6 and Virtex6 parts, packages, speed
>grades, and costs (small quantities) are or
>will be?
> I have a comparison charts from the Xilinx web
>site and I try to gleen availability from the
>Avnet website but this method seems like guess
>work.
> Thanks,
> Brad Smallridge
> AiVision
>

The parts are ready but the tools aren't. We're having ghastly timing
problems and we aren't getting support. This is apparently chronic
with S6. Plus, they pulled the plug on our distributor, NuHorizons, so
we no longer have them putting pressure on Xilinx for support.

I'd stick with S3 until they get all this fixed.

John


Article: 146416
Subject: Re: Any advice on which is the best book on CMOS digital circuit
From: Kim Enkovaara <kim.enkovaara@iki.fi>
Date: Wed, 17 Mar 2010 08:44:44 +0200
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> I want to buy books on  CMOS digital circuit designs. Any advice on
> which is the best book on CMOS digital circuit design?

At least "Nanometer CMOS ICs, From Basics to ASICs" written by Harry
Veendrick is quite nice overall book and is up to date with the
technology. The only problem with the book is the price, which is
quite high.

--Kim

Article: 146417
Subject: Re: Xilinx Spartan6 Virtex6 Rollout
From: Antti <antti.lukats@googlemail.com>
Date: Wed, 17 Mar 2010 00:13:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 17, 6:17=A0am, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Tue, 16 Mar 2010 13:12:04 -0700, "Brad Smallridge"
>
> <bradsmallri...@dslextreme.com> wrote:
> > Can anyone tell me where to find out what
> >Spartan6 and Virtex6 parts, packages, speed
> >grades, and costs (small quantities) are or
> >will be?
> > I have a comparison charts from the Xilinx web
> >site and I try to gleen availability from the
> >Avnet website but this method seems like guess
> >work.
> > Thanks,
> > Brad Smallridge
> > AiVision
>
> The parts are ready but the tools aren't. We're having ghastly timing
> problems and we aren't getting support. This is apparently chronic
> with S6. Plus, they pulled the plug on our distributor, NuHorizons, so
> we no longer have them putting pressure on Xilinx for support.
>
> I'd stick with S3 until they get all this fixed.
>
> John

hi John

it seems Xilinx is good on the road i predicted:

I think some years ago I said that Xilinx products will be unusable
because their software will become unusable when they hit 45nm
technology.

Antti

Article: 146418
Subject: Re: Xilinx Spartan6 Virtex6 Rollout
From: "HT-Lab" <hans64@ht-lab.com>
Date: Wed, 17 Mar 2010 07:37:19 -0000
Links: << >>  << T >>  << A >>

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:rnl0q5d1in9rnqhufimeij4jur878p750o@4ax.com...
> On Tue, 16 Mar 2010 13:12:04 -0700, "Brad Smallridge"
> <bradsmallridge@dslextreme.com> wrote:
>
>> Can anyone tell me where to find out what
>>Spartan6 and Virtex6 parts, packages, speed
>>grades, and costs (small quantities) are or
>>will be?
>> I have a comparison charts from the Xilinx web
>>site and I try to gleen availability from the
>>Avnet website but this method seems like guess
>>work.
>> Thanks,
>> Brad Smallridge
>> AiVision
>>
>
> The parts are ready but the tools aren't. We're having ghastly timing
> problems and we aren't getting support.

There might be some fixes in ISE 11.5 which was release yesterday. From the 
website:

"11.5 includes important updates and supports production devices for the
Virtex-6 and Spartan-6 families. However, several workarounds may be required
for Virtex-6 and some Spartan-6 customers using 11.5. Please review Answer
Record 32147 before you upgrade to 11.5. These workarounds will be addressed in
12.1, scheduled for May 2010. Designers targeting families other than Virtex-6
or Spartan-6 do not need to install 11.5. To ensure that ISE Design Suite
functions properly, it is essential that all 11.5 updates are applied together."

Hans
www.ht-lab.com



This is apparently chronic
> with S6. Plus, they pulled the plug on our distributor, NuHorizons, so
> we no longer have them putting pressure on Xilinx for support.
>
> I'd stick with S3 until they get all this fixed.
>
> John
> 



From prenom.nom@gmail.com Wed Mar 17 00:27:49 2010
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Date: Wed, 17 Mar 2010 09:27:49 +0100
From: Matthieu Michon <prenom.nom@gmail.com>
Newsgroups: comp.arch.fpga
Subject: Re: Question Rdging xilinx chipscope pro triggering
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On Tue, 16 Mar 2010 20:54:46 -0700 (PDT)
saras <saras_rajgiri@yahoo.co.in> wrote:

(...)

> But in the trigger setup window, there is no subwindow named capture.
> All i have is " Enable trigger sequencer" , " Enable storage
> qualification" , "trigger width" , "match type", "max number of
> samples levels" , "samples depth" and then  " Net connections". I'm
> using a licenesed Xilinx 10.1 version.Is there any problem with
> version or some other issue? Please help.


Your are probably looking at the Core Inserter software. John was refering to the "Position" number field present in the ChipScope Pro __Analyzer__ software (the application used for capturing and displaying waveforms).


Regards

-- 
Matthieu Michon <prenom.nom@gmail.com>

Article: 146419
Subject: Re: Nested interrupts in Nios system and hung system
From: =?ISO-8859-1?Q?Adam_G=F3rski?= <totutousungorskia@malpawp.pl>
Date: Wed, 17 Mar 2010 10:17:47 +0100
Links: << >>  << T >>  << A >>
jfh pisze:
> Hi,
> 
> The setup is the following :
> - a stratix II GX hosts a Nios IIe
> - one timer running continuously at a period of 1s, priority level 6,
> the handler for this interrupt has some functions calls to usleep and
> performs polling, this handler is made interruptible via the use of
> the alt_irq_interruptible and alt_irq_noninterruptible pair of
> functions
> - one hw interrupt generates an interrupt every 500 us with a prioity
> level 2 a uart running at 115 kbauds using the small driver
> implementation (no interrupt)
> - the main function of the C program is waiting forever for characters
> to come in via the uart and when a command is received it processes it
> and gets back to expecting a new command forever
> 
> With this setup it seems that the uart does not work well. When I
> pause the program after noticing it does not respond the program is
> almost always located in the usleep function called from the low
> priority interrupt handler. Is there anything in the setup described
> that is bad design ? What am i missing ? All ideas are welcome !
> 
> Best regards,
> 
> JF

Hi,

AFAIK interrupts in NIOS II e have software processing. So all 
interrupts are connected to same handler with soft processing.

Change nios version to faster one or you can try add interrupt custom 
instruction to reduce interrupt latency.

BR

Adam

Article: 146420
Subject: Re: Why doesn't this situation generate a latch?
From: Magne Munkejord <magnemunk@yahoo.no>
Date: Wed, 17 Mar 2010 11:24:08 +0100
Links: << >>  << T >>  << A >>
rickman wrote:
> On Mar 16, 8:24 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>> On Mar 16, 2:04 am, Magne Munkejord <magnem...@yahoo.no> wrote:
>>
>>
>>
>>
>>
>>
>>
>>> rickman wrote:
>>>> You would think that.  I just had to change some code to eliminate a
>>>> sync reset on a register to get rid of one level of LUTs in a Lattice
>>>> design which has a similar if not same FF structure with the dedicated
>>>> LSR input (Local Set/Reset).  Synplify seems to not know how to use
>>>> that.  Maybe this would get changed by the mapper, but I don't think
>>>> it does that.  I was looking at it in the synthesis tool.  Have you
>>>> tried an example?  Does Synplify do a better job with the Xilinx parts
>>>> than they do with Lattice parts?  I'm not convinced they do a good job
>>>> with the arithmetic units.  It is more than once I've seen an adder
>>>> chain duplicated to get the carry out of the top!
>>> Hi Rick,
>>> I tried 5-input registered OR, like this:
>>>      p_sync_or : process (clk) is
>>>      begin
>>>          if rising_edge(clk) then
>>>              q <= a or b or c or d or e;
>>>          end if;
>>>      end process p_sync_or;
>>> In a Virtex4 (4 input LUTs) XST synthesis connects input 'e' to the set
>>> port of the register, and so does not require two LUTs to implement the
>>> gate.
>>> When it comes to Synplify I only have the actel edition ( only actel
>>> parts supported(?)) and I have hardly ever used it.
>>> I think actel parts only support async resets for their registers, in
>>> which case it is true as you say, that designing synchronous resets will
>>> generate extra logic in front of the registers. Maybe this is true for
>>> Lattice as well. In that case I would prefer using an async reset to
>>> avoid the extra logic and performance penalty.
>>> If the reset signal is synchronously deasserted, it can be constrained
>>> so that one is certain it will reach each register at a proper time.
>>> Magne
>> Magne,
>> Your method is wrong !
>>
>> You cannot connect 'e' to the set port of the register. It may
>> compromise a new data which uses 'q'.
It wasn't me, XST did it!
>>
>> Imagine the case: if 'e' is so earlier asserted that 'q' is asserted
>> and changes a data 'New" which uses 'q' during setup or hold time
>> around the next clock triggering edge.Next 'New' signal data may be
>> invalid.
>>
>> p_sync_or : process (clk) is
>>      begin
>>          if rising_edge(clk) then
>>              q <= a or b or c or d or e;
>>          end if;
>>      end process p_sync_or;
>>
>> A : process(clk)
>>      begin
>>          if rising_edge(clk) then
>>              New <= a and q;
>>          end if;
>>      end process A;
>>
>> Weng
Since the 'set' port of the register is synchronous the circuit will 
behave as your code above describes it. q will not change state before 
rising edge of clk even if e is asserted earlier. I would think the 
timing tools knows the required setup time for the synchronous set/reset 
ports, and cover their paths as any other synchronous elements.
> 
> I'm not clear on what your concern is.  Perhaps you are thinging Magne
> is talking about e being connected to an async set?  He is describing
> a FF with an async set which will do exactly the same thing as an OR
> of signal e with the rest of the inputs.
> 
> Rick
The second instance of 'async' I would correct to 'sync', but I guess 
that was a typo.

Magne

Article: 146421
Subject: Re: Xilinx Spartan6 Virtex6 Rollout
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 17 Mar 2010 08:30:46 -0700
Links: << >>  << T >>  << A >>
On Wed, 17 Mar 2010 00:13:52 -0700 (PDT), Antti
<antti.lukats@googlemail.com> wrote:

>On Mar 17, 6:17 am, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> On Tue, 16 Mar 2010 13:12:04 -0700, "Brad Smallridge"
>>
>> <bradsmallri...@dslextreme.com> wrote:
>> > Can anyone tell me where to find out what
>> >Spartan6 and Virtex6 parts, packages, speed
>> >grades, and costs (small quantities) are or
>> >will be?
>> > I have a comparison charts from the Xilinx web
>> >site and I try to gleen availability from the
>> >Avnet website but this method seems like guess
>> >work.
>> > Thanks,
>> > Brad Smallridge
>> > AiVision
>>
>> The parts are ready but the tools aren't. We're having ghastly timing
>> problems and we aren't getting support. This is apparently chronic
>> with S6. Plus, they pulled the plug on our distributor, NuHorizons, so
>> we no longer have them putting pressure on Xilinx for support.
>>
>> I'd stick with S3 until they get all this fixed.
>>
>> John
>
>hi John
>
>it seems Xilinx is good on the road i predicted:
>
>I think some years ago I said that Xilinx products will be unusable
>because their software will become unusable when they hit 45nm
>technology.
>
>Antti

Their software has been spinning out of control for years. I've seen
other big software projects like this. Once that pattern is
established, it's nearly impossible to fix.

What's special about 45 nm? Is it just the sheer increase in chip
complexity that breaks the tools? The development software just sees
CLBs.

The worst problem we're having now is with the hard-core DRAM
controller. The architecture is essentially unmanagable, and the tools
throw timing errors even at low clock rates, or just refuse to
compile. We've had cases open on this for months (we got very early
S6/45 units) and the silence is deafening.

I'm sure they'll patch it up eventually. The precise quantization of
"eventually" will determine if we still have a customer and whether 2
man-years of work will be a total loss.

John



Article: 146422
Subject: Re: Awkward Arithmetic
From: jacko <jackokring@gmail.com>
Date: Wed, 17 Mar 2010 08:33:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
Looks like a phase controlled DCO. Maybe the frequency/phase d/dt fm
effect can be used? It does look messy, modulus if its a power of 2
should be easy to remove by a (x downto y) subrange select. If modulus
is n/(n-1) then consider MASH or bitstream delta sigma. OR use a fixed
point overflow clock gating. Has anyone ever tried n/(n-2) via up/down
clock gating of an n divider??

Cheers Jacko

Article: 146423
Subject: Re: Nested interrupts in Nios system and hung system
From: jacko <jackokring@gmail.com>
Date: Wed, 17 Mar 2010 08:38:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 16 Mar, 06:16, jfh <jeanfrancois.has...@gmail.com> wrote:
> Hi,
>
> The setup is the following :
> - a stratix II GX hosts a Nios IIe
> - one timer running continuously at a period of 1s, priority level 6,
> the handler for this interrupt has some functions calls to usleep and
> performs polling, this handler is made interruptible via the use of
> the alt_irq_interruptible and alt_irq_noninterruptible pair of
> functions
> - one hw interrupt generates an interrupt every 500 us with a prioity
> level 2 a uart running at 115 kbauds using the small driver
> implementation (no interrupt)
> - the main function of the C program is waiting forever for characters
> to come in via the uart and when a command is received it processes it
> and gets back to expecting a new command forever
>
> With this setup it seems that the uart does not work well. When I
> pause the program after noticing it does not respond the program is
> almost always located in the usleep function called from the low
> priority interrupt handler. Is there anything in the setup described
> that is bad design ? What am i missing ? All ideas are welcome !
>
> Best regards,
>
> JF

maybe just have the one interrupt at 500us and every 2 interrupts do
the 1s stuff. Maybe set a flag to return to sleep in the interrupt and
do the actual sleep in the main loop.

Cheers Jacko

Article: 146424
Subject: Re: Spartan 3 LVDS - current mode outputs?
From: austin <austin@xilinx.com>
Date: Wed, 17 Mar 2010 08:46:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
Andrew,

The common mode voltage is referenced to the band gap precise voltage
reference, which is in every device since Virtex.

The currents are set by design, and the output impedance is set by a
resistance.  LVDS has a 100 ohm transmit termination, as well as
having a 100 ohm receive termination.

If you don't use 100 ohms, it won't match!

You can probably go anywhere from 75 ohms to 150 ohms, though, and the
reflections will not be so bad that it affects the data link.

It is a fairly easy exercise to add resistance matching networks, so
that the device "sees" 100 ohms, and your transmission media "sees"
what it likes.  The matching networks add loss, so the distance you
can travel is made less, but you can have a perfect match.

Running some simulations using IBIS models will tell you what you need
to know.

And, no, we are not going to provide a schematic drawing of the LVDS
output stage, as that is proprietary, and we have already provided
everything you need (if you simulate the LVDS with the IBIS or
encrytped hspice models that we provide).

Austin




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