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On 20 Mar, 13:57, james <bu...@bud.u> wrote: > On Thu, 18 Mar 2010 12:32:11 -0400, DJ Delorie <d...@delorie.com> wrote: > > |On 03/18/2010 10:03 AM, Francesco wrote: > |> seems that Xilinx has decided to have only one distributor... > | > |Really? =A0Their authorized distributors page lists two. > > That will remain so until June. Then Nu H will either have sold their > existing stock or will return that stock to Xilinx from what I gather. > > Also it looks as if Digikey will remain a "regional" partner. I guess > Digikeyremains a "partner" due to they will be an outlet for parts and > boards and that is all. > > james RS and Farnell sell them, as well. LeonArticle: 146501
On Mar 19, 5:31=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 19 Mar 2010 06:32:38 -0700 (PDT), rickman wrote: > > [Weng] > > >> there are 6 types of > >> reset signals, a situation much more complexer than we think. > >Ok, go ahead and tease us! =A0Or are you going to share with us what the > >six types are? > > 1. Reset that is asserted at the right time, > =A0 =A0but has the wrong polarity, thus holding the design > =A0 =A0in reset throughout your test. > 2. Reset with the right polarity that is not asserted > =A0 =A0reliably at power-up, because you were too cheap > =A0 =A0to spend $0.70 on a power monitor/watchdog chip. > 3. Reset that is triggered at random times during > =A0 =A0operation because it is laid out on the PCB too > =A0 =A0close to a data bus. =A0Capacitive coupling causes > =A0 =A0reset to be momentarily asserted when more than > =A0 =A080% of the data lines transition simultaneously. > 4. Reset that is asserted correctly, but is released > =A0 =A0too close to a clock edge and causes the design > =A0 =A0to go into an illegal state because some flops > =A0 =A0respond to the clock and others don't. > 5. Reset of a counter, used by a designer who thought > =A0 =A0it would be a cool way to make the counter go back > =A0 =A0to zero when it overflows some programmed limit. > 6. Reset that is triggered by the operation of a > =A0 =A0system-level watchdog. =A0It causes the CPU to stop > =A0 =A0operating roughly a millisecond before emitting > =A0 =A0the debug message that would have allowed you > =A0 =A0to diagnose the problem. > > Just in case you thought I was fooling, I should point > out that I have had to debug and correct each of these > at some point in my career. =A0One or two of them were > someone else's fault :-) > -- > Jonathan Bromley Then aren't there at least 7 types of reset? You need to include one that actually works as expected... or have you never found that one in practice ;^) RickArticle: 146502
I am using Active-HDL standard waveform display and have some of my signals configured for analog display which interprets the integer value to create an oscilloscope like display. I am finding that if I try to zoom the vertical range it does not increase the resolution. In some cases I get a coarse stairstep display and in others it tries to display the trace outside of the vertical area of the signal. Is this a known bug? Has anyone else seen it before? RickArticle: 146503
"rickman" <gnuarm@gmail.com> wrote in message news:3c56ca21-0f53-485e-95aa-58fda2ebc64c@30g2000yqi.googlegroups.com... >I am using Active-HDL standard waveform display and have some of my > signals configured for analog display which interprets the integer > value to create an oscilloscope like display. I am finding that if I > try to zoom the vertical range it does not increase the resolution. > In some cases I get a coarse stairstep display and in others it tries > to display the trace outside of the vertical area of the signal. > > Is this a known bug? Has anyone else seen it before? I just tried it on my copy, and it works as I'd expect. The vertical display seems reasonably fine, though I'm not enormously super-Nyquist, so it might be hard to notice subtle errors. Nothing goes outside the display height, and clipped signals are shown in red. There is a check box in the advanced viewer prefs that allows you to trade off accuracy for speed. I haven't played with that though... One problem I do have is that I have to set the properties for my analog displays individually. If I try to set properties for multiple traces at the same time, they get the range estimate very wrong (even if they all have the same range). PeteArticle: 146504
http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 x----------xArticle: 146505
On Mar 21, 7:00=A0am, Peter <pe...@peter2000.co.uk> wrote: > http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=3D290416326824 > > x----------x What? I have tons of those ;-))))))Article: 146506
"Mawa_fugo" <ccon67@netscape.net> schrieb im Newsbeitrag news:308d0cd3-5784-4cd8-8325-9d8cbb831776@z3g2000yqz.googlegroups.com... On Mar 21, 7:00 am, Peter <pe...@peter2000.co.uk> wrote: > http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 > > x----------x What? I have tons of those ;-)))))) JTAG-Adapters, dongles, I doubt. If somebody has to change an old Xilinx-design, he will need the right software revison plus the dongle. The latest revisions dont help, because they no more support the old FPGA devices. HelmutArticle: 146507
I have created a GTP wrapper for and have used the provided testbench to run a simulation. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146508
I have created a GTP wrapper for a 10-bit SDI protocol. I have run the provided testbench but when I simulate the rx data is not what I expect. The testbench sends the following data. 000, 001, 002 ---- 07f then repeats The data I receive is 000, 010, 020 etc which seems to be shifted up by 4 bits. However a value of 040, or 07f gives the rx data of 000 which seems to be missing a 1 bit. Does anyone have a clue what is going on? Cheers Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146509
> Yes and no, > > First create your core logic as a "headless" design with no bus interface. > Make a testbench that directly drives and tests the ports of this core > design. > > Then create a module with a wishbone interface and connections for all the > ports of your core that do not connect to a higher level. Your design will > consist of a wrapper containing these two modules. Copy your test suite and > rewrite it to use the wishbone bus where needed. > > DO NOT create a wishbone interface and then place your core logic below it > in the hierarchy. If you do and then later want to support a different bus > then you are screwed. If you keep the wishbone in one module then it is > alot easier to take that module and convert it into something like a AHB > bus. > You want to be able to add new buses without touching the core. Hi John, I completely got your point and I'm really happy you pointed that out, because most probably I would have made a big mistake! It makes perfectly sense to me and it's surely the way I will go. Thanks again, Al p.s.: funny how very simple ideas sometimes are not so evident to all of us. -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 146510
On Mar 21, 9:25=A0am, "Helmut Sennewald" <helmutsennew...@t-online.de> wrote: > "Mawa_fugo" <cco...@netscape.net> schrieb im Newsbeitragnews:308d0cd3-578= 4-4cd8-8325-9d8cbb831776@z3g2000yqz.googlegroups.com... > On Mar 21, 7:00 am, Peter <pe...@peter2000.co.uk> wrote: > > >http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=3D290416326824 > > > x----------x > > What? I have tons of those > > ;-)))))) > > JTAG-Adapters, dongles, I doubt. > > If somebody has to change an old Xilinx-design, > he will need the right software revison plus the dongle. > The latest revisions dont help, because they no more > support the old FPGA devices. > > Helmut Doesn't Xilinx provide a "Classic" version of their tools? I also have old versions of the Xilinx tools complete with dongle and programming cables. That's one of the reasons why I hate licenses. You may have everything you need, except if the PC is different you may need a new license file. That's the way it is with my current Lattice software. So far they have been happy to provide a license file for every new machine I've wanted to port the software to. But I am sure that one day that will no longer be the case and I'll be stuck! The first time I see a way to get away from these proprietary, licensed tools, I'm gone in a flash! RickArticle: 146511
Hi, the local Lattice FAEs here in Germany recommended me to get a USB ethernet card for my PC and tie the license to that. It works a treat. In the office I usually have it on a windows 2003 server machine (officially not supported but works anyway and I can log in from a quiet thin client). When I go to a customer, trade fair etc. I run the same license from my laptop or one of these neat small form factor PCs from Fujitsu (http://de.fujitsu.com/products/deskbound/personal_computers/esprimo_q_series.html) rickman schrieb: > On Mar 21, 9:25 am, "Helmut Sennewald" <helmutsennew...@t-online.de> > wrote: >> "Mawa_fugo" <cco...@netscape.net> schrieb im Newsbeitragnews:308d0cd3-5784-4cd8-8325-9d8cbb831776@z3g2000yqz.googlegroups.com... >> On Mar 21, 7:00 am, Peter <pe...@peter2000.co.uk> wrote: >> >>> http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 >>> x----------x >> What? I have tons of those >> >> ;-)))))) >> >> JTAG-Adapters, dongles, I doubt. >> >> If somebody has to change an old Xilinx-design, >> he will need the right software revison plus the dongle. >> The latest revisions dont help, because they no more >> support the old FPGA devices. >> >> Helmut > > Doesn't Xilinx provide a "Classic" version of their tools? > > I also have old versions of the Xilinx tools complete with dongle and > programming cables. That's one of the reasons why I hate licenses. > You may have everything you need, except if the PC is different you > may need a new license file. That's the way it is with my current > Lattice software. So far they have been happy to provide a license > file for every new machine I've wanted to port the software to. But I > am sure that one day that will no longer be the case and I'll be > stuck! > > The first time I see a way to get away from these proprietary, > licensed tools, I'm gone in a flash! > > RickArticle: 146512
On 3/20/2010 10:46 AM, HT-Lab wrote: > > There are lots of places were you can legally download it from, if you do a > google search (amba bus protocol) then the first entry is wikipedia and the > second is: > > http://ens.ewi.tudelft.nl/Education/courses/et4351/amba.pdf > > If you read the second page it states: > > Document confidentiality status > This document is Open Access. This document has no restriction on distribution. > I just had a read to this document: http://www.opencores.org/downloads/soc_bus_comparison.pdf Apparently the wishbone seams much easier to use then the other two reported, but it seems to be it doesn't support address pipelining (as Rob already mentioned), which so far I don't have any element to evaluate whether this is a main problem or not. My main intent is to promote, or support and spread the concept of _reuse_ especially in the research world (where I belong to) where people are kind of keen to "reinvent" the wheel. I believe that a lot of efforts can be made more fruitful if a common interface would be available. Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 146513
Howdy Peter! Peter wrote: > http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 Why? Won't you need to deal with supporting older products? Regards, --donArticle: 146514
rickman <gnuarm@gmail.com> writes: > I find your tag line to be pretty annoying as well. It is one of Of course I can remove it. I just got a little curious. Is it that I've been using it for so long? Is it the length? Or is it the context that annoys you? > It is one of those things that once you've read it, you don't need to > keep reading it. There are other readers here besides you. There's probably new people entering the group every day. The sig was mostly targeted towards new participants. > But it is there at the bottom of each post you make and That's the case with most sigs. > hard to ignore. At least I find it hard to ignore. What are the > chances you can switch to something else? This will have to do until I dig out some of my older ones... Petter -- .sig removed by request.Article: 146515
On Mar 21, 3:43=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > rickman <gnu...@gmail.com> writes: > > I find your tag line to be pretty annoying as well. =A0It is one of > > Of course I can remove it. I just got a little curious. Is it that > I've been using it for so long? Is it the length? Or is it the context > that annoys you? It is just the repetition of the message I think. First, I guess I don't agree that it is something that needs to be addressed in this way. Others have used this sort of sig too and after some several hundreds or thousands of times of seeing it it becomes an annoyance. The same is true for commercials on TV. I can't stand some of them the first time I see them. Others start getting on my nerves after a few dozen times. That is why I use the mute and it is also why I haven't done anything to get more channels after I fell of the digital cliff on the broadcast conversion. I now get three channels from one public TV station and am pretty happy with that actually. Thanks for being understanding about your sig. RickArticle: 146516
On Mar 20, 3:17=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > On Mar 20, 2:52=A0am, modimo <g.mod...@gmail.com> wrote: > > > > > On 20 Mar, 04:28, Mawa_fugo <cco...@netscape.net> wrote: > > > > On Mar 19, 10:05=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > On Mar 19, 3:55=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > On Mar 19, 2:17=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > > > On Mar 19, 3:01=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > > > Hi all, > > > > > > > > There's an instance of BRAM in spartan3 device. =A0I used cor= egen with > > > > > > > *.coe file to init the data for the memory module > > > > > > > > My question, is there anyway to edit the mcs file (we use fla= tform > > > > > > > flash for config) to change the content of init data ..."with= out spend > > > > > > > 20 minutes to re-run the whole ISE processes > > > > > > > > Thanks, > > > > > > > "There's an app for that." > > > > > > >http://www.xilinx.com/products/ipcenter/dr_dt_data2mem.htm > > > > > > Thanks for the link, I do search around and all route to that pag= e.. > > > > > But I'm not sure I can get anything, > > > > > Is there any download-able thing ? > > > > > > Thanks > > > > > Have you looked in your Xilinx directories for your installed ISE? > > > > > From a random sell sheet: > > > > > ISE=99 WebPack FPGA Design Tool Suite > > > > =95 Timing driven FPGA hardware implementation tools > > > > =95 Design entry, synthesis and verification capabilities > > > > =95 Data2MEM =96 application for loading on-chip memory > > > > > It looks like it's included standard. > > > > Yes, I see that execute file data2mem, look like old day command > > > line. =A0Guessing it's just another non-user-friendly Xilnx apps ;-) > > > > Thanks > > > Console apps are user-friendly matter of who their friends are ;) > > > Some examples should be helpfulhttp://home.mnet-online.de/al/BRAM_Bitst= reams.html > > > There is also app for updating picoblaze code through jtag that also > > could be useful after some modifications.http://forums.xilinx.com/xlnx/= board/message?board.id=3DPicoBlaze&messag... > > In my app, the data width is 1 bit, with 128k depth, that means I have > 8 BRAM16 inst > > ---------below is my bmm file > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x00001FFFF] > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B76/RAMB16BWER [0:0] =A0PLACED =3D > X2Y12; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B79/RAMB16BWER [0:0] =A0PLACED =3D > X2Y14; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B82/RAMB16BWER [0:0] =A0PLACED =3D > X2Y13; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B85/RAMB16BWER [0:0] =A0PLACED =3D > X2Y15; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B88/RAMB16BWER [0:0] =A0PLACED =3D > X2Y17; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B91/RAMB16BWER [0:0] =A0PLACED =3D > X2Y18; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B94/RAMB16BWER [0:0] =A0PLACED =3D > X2Y19; > END_BUS_BLOCK; > > BUS_BLOCK > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B97/RAMB16BWER [0:0] =A0PLACED =3D > X2Y16; > END_BUS_BLOCK; > > END_ADDRESS_BLOCK; > > ----below is the command line I try to see if I can extract the data > from existing bit file > > $ data2mem -bm mybmmfile.bmm -bt existingbitfile.bit > log.txt > > -------- But it always gives the below error > > ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE > 'mem_module'. > =A0 =A0 ADDRESS_SPACE was defined as 0x00020000 bytes, but the > ADDRESS_RANGE total is 0x00004000 bytes. > > ---Then I try to change the address space to > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x000003FFF], > > ---It then gives no error but the log.txt file is just a blank, > nothing show up > > ---I wonder if this tool can't handle data width with 1 bit wide???? The tool doesn't have a clue. Just lie to it and tell it your RAM is 8 bits wide.Article: 146517
I am running a simulation in Active HDL and using generics to vary some parameters to the top level test bench. I can't seem to figure out what to do to get Active-HDL to use the changed generics I set in the Design Settings dialog box. I've tried restarting the simulation and recompiling the design and this does not always do the job. Watching the Console I see that the new generic values are finally used when an asim command is issued rather than just a restart and a run. The only way I have found to reliably pull in the new generic values is to start a simulation and then use the "End simulation" button to stop it. Surely there is something I am missing... RickArticle: 146518
On Mar 17, 11:53=A0pm, "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > I received my new Nexys2 board today and fired it up. I already had a Bas= ys > and Nexys =A0board so I wanted to see what this one had to offer. > > It is nice. Its larger so that the leds actually line up with the switche= s > and you have room to actually plug in a canned oscillator. You may not ne= ed > it because they upgraded the original resonator to a real oscillator. My > basys board had unstable video with the resonator and needed a can. The > Nexsys2 is ok. > > They doubled the number of external connections off the board and added a > ps2, > uart and vga interface. I took a basys design that I had and edited the > padring,ucf and a couple of config files and it compiled and ran ok. > > It's nice having all those gates. > > John =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com The only thing I don't like about Digilent is the lack of Linux support for their USB. (There is a project on the web somewhere for JTAG support, but no project for doing data transfers.) I have an email from an engineer named "Josh" at Digilent: "We are planning on providing Linux support by the 4th quarter of 2008; so nothing will be available in the short-term. " They're in Microsoft's backyard, and I think UW (where the owners work, I think) receive a lot of Microsoft funding, but I'm sure it's just that nobody but me is interested in Linux...Article: 146519
D Yuniskis <not.going.to.be@seen.com> wrote >Howdy Peter! > >Peter wrote: >> http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 > >Why? Won't you need to deal with supporting older products? > >Regards, >--don Howdy Don :) Great to hear from you :) I thought about this very hard. Of the FPGA designs I did, for those which might come back, I would never have time to set up all the software (on a PC with a DOS partition, which I don't have anymore), go up the not insignificant learning curve on the software, and then be able to make a commercial project out of it. Two of the designs were perhaps more significant. One was a 32-channel sound generator (basically 32 programmable pulse generators feeding a 32-input OR gate) which was originally done in 1992, on a full size ISA card, no kidding. About 8 years ago the customer wanted a PCI version of this card. I said to them I will give them the whole design free of charge but they will need to find somebody else to do it. I posted around Usenet looking for an FPGA programmer in SE UK and one or two turned up and I passed them on but never heard anything else. The *huge* issue is the commercial risk: one has to quote a fixed price, which would make it very profitable if the old tools worked fine, nothing went wrong, and I could still get the XC3030/3090 TQFP chips (which I probably could). But if something goes wrong, and e.g. I have to buy new tools, I would lose some high 4- or low 5-digit sum on it. The other was basically a complicated custom UART supporting some weird characters (122 bits long) with CRCs and all kinds of stuff. This project was done in 1993 and was hugely profitable, helping me to establish my manufacturing business (the kind of thing every consultant should be doing before his hair goes grey and his sandals fall apart :)). To my astonishment the project came up 12 years later, via a completely different customer (but the same end user) and I simply bought more of the XC3090 devices (PLCC, seemed to be available OK) and to my amazement it worked. I first sent a few devices to the customer (who was pretty smart) and he put them into his old boards, and it all worked, so evidently Xilinx did not change the silicon to make it much faster (and break my timing, which was done according to the *then* Xilinx guidelines which said it was OK to use local interconnect (with some 'max skew = 2ns or whatever' parameter on the wire) for clocks because the interconnects were much faster than the D to Q propagation delays). The customer may buy again but I just need to source some more of the old devices. He won't need a logic redesign. The main project I did with the tools was maybe 1 man year spent on prototyping various evolutions of a very low power ASIC, with about 5000 gate equivalent of logic, a real time clock, etc. This one is not coming back. These tools will be very valuable to somebody who did designs in those days, which might come back for modifications. The devices are for the most part available; I checked the XC3090 etc about 2 years ago and Xiling were still selling them, and there are bound to be plenty on the surplus market which these days is huge.Article: 146520
Patrick Maupin <pmaupin@gmail.com> wrote: (snip) > They're in Microsoft's backyard, and I think UW (where the owners > work, I think) receive a lot of Microsoft funding, but I'm sure it's > just that nobody but me is interested in Linux... Pullman is completely the other side of the state from Redmond. There might be a UW branch there, but it is a long way from Seattle. When I ordered my Digilent board last year, there was a storm that closed some of the freeways and, according to UPS tracking, it was diverted through Portland. -- glenArticle: 146521
On Sun, 21 Mar 2010 14:37:22 -0700 (PDT), rickman wrote: >Watching the Console I see that the new generic values are finally >used when an asim command is issued rather than just a restart I can't really understand why you would expect any other behaviour. Generics (and, similarly, Verilog parameters) are finalized at elaboration time, so you must of necessity re-elaborate if you wish to change a generic. As I understand it, the "asim" command is responsible for that elaboration step just as "vsim" is in ModelSim. Restarting a sim generally means simply reloading an already-elaborated image (a "snapshot" in Cadence IUS jargon). You can't expect to tweak the generics on such a snapshot. ModelSim keeps track of compilations to a sufficient extent that it knows to re-elaborate if you try to restart after recompiling something; maybe Active-HDL has some similar feature. But whatever happens, you need a complete new elaboration of the model if you want to change a generic. -- Jonathan BromleyArticle: 146522
On Mar 21, 5:14=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Patrick Maupin <pmau...@gmail.com> wrote: > > (snip) > > > They're in Microsoft's backyard, and I think UW (where the owners > > work, I think) receive a lot of Microsoft funding, but I'm sure it's > > just that nobody but me is interested in Linux... > > Pullman is completely the other side of the state from Redmond. > There might be a UW branch there, but it is a long way from Seattle. > > When I ordered my Digilent board last year, there was a storm that > closed some of the freeways and, according to UPS tracking, it > was diverted through Portland. =A0 > > -- glen A look at their "about" page says "Washington State University" which is based in Pullman, so that was my bad memory all the way around. So, maybe it's just be perceived market size and/or lack of qualified Linux driver people. But if they'd just document their interface, we could do it with libusb. I'm too old to have the patience to reverse engineer this kind of stuff any more. In the same email thread two years ago, I asked about documention, but they ignored that, and figured (correctly) that I would forget about it if I were promised a Linux driver a few months later. But it's been two years since I asked, and a year and a half since they said it was going to be available. We've probably bought 30 or 40 of their Nexys/Nexys2 boards at work, but they would be a lot more useful, and I'd buy a lot more, if I could just use them from Linux. Regards, PatArticle: 146523
Patrick Maupin wrote: > They're in Microsoft's backyard, and I think UW (where the owners > work, I think) receive a lot of Microsoft funding, but I'm sure it's > just that nobody but me is interested in Linux... no, don't worry. yg -- http://ygdes.com / http://yasep.orgArticle: 146524
On Mar 21, 6:19=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 21 Mar 2010 14:37:22 -0700 (PDT), rickman wrote: > >Watching the Console I see that the new generic values are finally > >used when an asim command is issued rather than just a restart > > I can't really understand why you would expect any other > behaviour. =A0Generics (and, similarly, Verilog parameters) > are finalized at elaboration time, so you must of necessity > re-elaborate if you wish to change a generic. =A0As I > understand it, the "asim" command is responsible for > that elaboration step just as "vsim" is in ModelSim. > > Restarting a sim generally means simply reloading an > already-elaborated image (a "snapshot" in Cadence IUS > jargon). =A0You can't expect to tweak the generics on > such a snapshot. > > ModelSim keeps track of compilations to a sufficient extent > that it knows to re-elaborate if you try to restart after > recompiling something; maybe Active-HDL has some similar > feature. =A0But whatever happens, you need a complete new > elaboration of the model if you want to change a generic. > -- > Jonathan Bromley I'm not asking about the behavior of the asim command. I am asking how to invoke this through the GUI. The tool must by necessity re- elaborate after recompiling, right? But that doesn't seem to result in the asim command being run. However, a restart does seem to re- elaborate according to the log file... restart # ELBREAD: Elaboration process. # ELBREAD: Elaboration time 0.0 [s]. # KERNEL: Main thread initiated. # KERNEL: Kernel process initialization phase. # KERNEL: Time resolution set to 1ps. # ELAB2: Elaboration final pass... # ELAB2: Create instances ... # ELAB2: Create instances complete. # ELAB2: Elaboration final pass complete - time: 0.1 [s]. It does say "final pass", so maybe this is not the "full" elaboration. But it does the same thing after compiling the entire project. It seems I have to use the small square button (VCR stop) to stop the simulation to get it to accept a new set of top level generics even if the source is recompiled... strange... Rick
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