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I have a design implemented on a Xilinx Virtex 5. The design contains several power nets sourced by TIEOFFs and feeding some of the slices used by the design. A closer look at several of the LUT equations with a power net input, shows that the power net input does not actually affect the output of the LUT. For example, assuming two nets are feeding a slice. One of the nets is a power net feeding input A6, while the other net is feeding input A1. The LUT equation could be something like the following: <A6LUT>=(A6+~A6)*(A2) What is confusing to me is the fact that (A6+~A6) is always true, thus should not affect the output of the LUT. My questions is, why is a power net needed in that case? Thanks,Article: 150876
On 2/16/2011 7:52 PM, Chris Maryan wrote: > I think you can miss a pulse with your circuit if you go metastable on the output of the slow FF. > > With the T FF (or with pulse stretching) on the fast side followed by some FFs and an edge detect on the slow side, you can put in as many FFs as you like on the slow side to deal with metastability. > > Chris Hi Chris, At 100MHz, you've got up to 10ns for the metastability to resolve. You might want to worry about your circuit being hit by a meteorite or taken by 'The Rapture' before concerning yourself about that type of metastability event. Cheers, Syms. http://www.xilinx.com/support/documentation/application_notes/xapp094.pdfArticle: 150877
On 18 Feb., 02:58, Mike Treseler <mtrese...@gmail.com> wrote: > >> After some study and a lot of discussions with colleagues and friends = I > >> would like to pin down the reasons why I have always believed that a > >> finite state machine (FSM) _is not_ a counter and at the same time try > >> to explain why a counter is a very special FSM (hope the thread will n= ot > >> be too hot!). > > This is indeed a job for the python argument clinic:http://www.youtube.co= m/watch?v=3DteMlv3ripSM > > =A0 =A0 =A0 =A0-- Mike Treseler No, it isn't!Article: 150878
Yes it is!Article: 150879
Hi guys, I'm searching for a general mathematical definition of an FPGA. I propose this y=F(x,u) where y is a vector of output , u is a vector of input and x is a vector of internal state and F is a certain function of x,u. Have you some idea to generalize more this definition? Thank you, SilvioArticle: 150880
On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > Hi guys, > I'm searching for a general mathematical definition of an FPGA. > I propose this y=3DF(x,u) where y is a vector of output , u is a vector > of input and x is a vector of internal state and F is a certain > function of x,u. Have you some idea to generalize more this > definition? > Thank you, > Silvio A mathematical definition for an FPGA??? Is there a mathematical definition for a CPU or a chalkboard? If the design that was implemented in a FPGA included no states (registers, latches, RAMs, etc) it would be possible define the function of the combinatorial function that was implemented in the FPGA as y=3DF(u) using your definitions. But with states what would be the point? The Function could only describe a portion of the design with that portion including only the last state point to outputs and the time based nature of logic states would not be described. Ed McGettigan -- Xilinx Inc.Article: 150881
On Feb 19, 6:14=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > > > Hi guys, > > I'm searching for a general mathematical definition of an FPGA. > > I propose this y=3DF(x,u) where y is a vector of output , u is a vector > > of input and x is a vector of internal state and F is a certain > > function of x,u. Have you some idea to generalize more this > > definition? > > Thank you, > > Silvio > > A mathematical definition for an FPGA??? =A0 =A0Is there a mathematical > definition for a CPU or a chalkboard? > > If the design that was implemented in a FPGA included no states > (registers, latches, RAMs, etc) it would be possible define the > function of the combinatorial function that was implemented in the > FPGA as y=3DF(u) using your definitions. > > But with states what would be the point? =A0The Function could only > describe a portion of the design with that portion including only the > last state point to outputs and the time based nature of logic states > would not be described. > > Ed McGettigan > -- > Xilinx Inc. I think, it's not correct, the internal state variables x are the smallest possible subset of system variables that can represent the entire state of the system at any given time. SilvioArticle: 150882
You need x (vector of internal state) to also be the output of a function of u and x. Once you have that, you've got a mathematical model of a hybrid Mealy/ Moore state machine. I don't think you can generalize it much more than that.Article: 150883
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: (someone wrote) >> I'm searching for a general mathematical definition of an FPGA. (snip) > A mathematical definition for an FPGA??? Is there a mathematical > definition for a CPU or a chalkboard? The APL programming language was originally designed to write a mathematical expression for the IBM 360 system. I suppose one could rewrite the microcode for a CPU in a mathematical form, and call it a mathematical definition of that CPU. > If the design that was implemented in a FPGA included no states > (registers, latches, RAMs, etc) it would be possible define the > function of the combinatorial function that was implemented in the > FPGA as y=F(u) using your definitions. I can believe in writing a mathematical definition for a programmed FPGA, but not for an unprogrammed one. Might just as well write one for a silicon crystal. -- glenArticle: 150884
On Feb 19, 7:42=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > (someone wrote)>> I'm searching for a general mathematical definition of = an FPGA. > > (snip) > > > A mathematical definition for an FPGA??? =A0 =A0Is there a mathematical > > definition for a CPU or a chalkboard? > > The APL programming language was originally designed to write > a mathematical expression for the IBM 360 system. =A0I suppose > one could rewrite the microcode for a CPU in a mathematical > form, and call it a mathematical definition of that CPU. > > > If the design that was implemented in a FPGA included no states > > (registers, latches, RAMs, etc) it would be possible define the > > function of the combinatorial function that was implemented in the > > FPGA as y=3DF(u) using your definitions. > > I can believe in writing a mathematical definition for a > programmed FPGA, but not for an unprogrammed one. =A0Might just > as well write one for a silicon crystal. > > -- glen The fact that the FPGA isn't programmed correspond to the undefined form of F() function. SilvioArticle: 150885
On Feb 19, 10:04=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > On Feb 19, 6:14=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote= : > > > > Hi guys, > > > I'm searching for a general mathematical definition of an FPGA. > > > I propose this y=3DF(x,u) where y is a vector of output , u is a vect= or > > > of input and x is a vector of internal state and F is a certain > > > function of x,u. Have you some idea to generalize more this > > > definition? > > > Thank you, > > > Silvio > > > A mathematical definition for an FPGA??? =A0 =A0Is there a mathematical > > definition for a CPU or a chalkboard? > > > If the design that was implemented in a FPGA included no states > > (registers, latches, RAMs, etc) it would be possible define the > > function of the combinatorial function that was implemented in the > > FPGA as y=3DF(u) using your definitions. > > > But with states what would be the point? =A0The Function could only > > describe a portion of the design with that portion including only the > > last state point to outputs and the time based nature of logic states > > would not be described. > > > Ed McGettigan > > -- > > Xilinx Inc. > > I think, it's not correct, the internal state variables x are the > smallest possible subset of system variables that can represent the > entire state of the system at any given time. > Silvio- Hide quoted text - > > - Show quoted text - Please explain which part of what I wrote you think is incorrect. Ed McGettigan -- Xilinx Inc.Article: 150886
On Sat, 19 Feb 2011 08:12:29 -0800, silvio.baccari wrote: > Hi guys, > I'm searching for a general mathematical definition of an FPGA. I > propose this y=F(x,u) where y is a vector of output , u is a vector of > input and x is a vector of internal state and F is a certain function of > x,u. Have you some idea to generalize more this definition? > Thank you, > Silvio By the time you captured all of the "FPGA-ness" you would have a mathematical description that would be so complex it would be useless. In general the art of mathematical modeling lies not in capturing everything there is to capture about a thing that you want to model. Rather, it lies in capturing _just enough_ information about the thing so that you can get a _representative_ answer for your _immediate problem_. Capture too much information, and at best your model will be confusing, and at worst it'll be so unwieldy that you can't do anything useful with it. So -- tell us what you want to do, and maybe we can help you model whatever subset of FPGA behavior it is that you really need modeled. -- http://www.wescottdesign.comArticle: 150887
Hi, I just downloaded and installed Xilinx ISEWebpack 12.4 on a machine running Kubuntu 10.04 as a 64bit system. As a test for the new system I started with a usual "Hello World" program in Verilog: module main(sw, btn, led, clk, rst); input rst; input[7:0] sw; input[3:0] btn; output[7:0] led; input clk; reg[28:0] cnt; always @(posedge clk or posedge rst) begin if (rst) begin cnt <= 0; end else begin cnt <= cnt + 1; end end assign led = cnt[28:21] & sw; endmodule (I know btn's are unused, they are in for later use) I could synthesize, map, place and route this, and finally generate a main.bit file. Just two problems remained: 1) Although after some wrestling with cable drivers I got the Digilent Cable (type 3) to my Spartan 3 Starter Kit from Digilent recognized and could see the graphical representation of the JTAG chain on the IMPACT screen, nevertheless it was impossible to program successfully: Always there remained "9 errors" in the verified bitstream, even when the board after the failed programming started working as expected. 2) What I found very annoying is, that, using the RTL schematic viewer to display the above design, there always remains an error in the schematic: The counter module inferred from the always block is shown mostly unconnected, only clk is connected, the output Q and the input port_data are unconnected. Also there is no connection from rst to the counter module. This could not be overcome by zooming in. Three years ago I completed a larger hobby project using WindowXP and WebPack 8.1 and never experienced problems like that in 2). Just two verify that my board is not defect after the error messages in 1) I reverted to the old Windows version of the WebPack and indeed could transfer the .bit file without failure. Does anyone have an idea what is the cause for problem 2) and how to overcome it? Is it a specific Linux related issue? The same question I could ask for 1): It seems to be so near to working, but I do not know what to try to make it from 99% success to 100% success. If needed I could post output lines from the IMPACT tool. Greetings Jürgen -- Jürgen Böhm www.aviduratas.de "At a time when so many scholars in the world are calculating, is it not desirable that some, who can, dream ?" R. ThomArticle: 150888
On Feb 16, 12:31=A0am, Antti <antti.luk...@googlemail.com> wrote: > hi > > YES, VCCP floating, JTAG flashing OK, and FPGA working as well :) > > pictures here:http://www.flickr.com/photos/trioflex/ > > Antti Hi All, Just wanted to clarify that Vccp pin is not used in machXO2 (ES & production devices) and so can be left floating. The documentation will be modified to reflect the fact. Alex, Lattice FAE, writing unofficially from homeArticle: 150889
On Fri, 18 Feb 2011 09:58:19 -0600, fpgalover wrote: > I have a design implemented on a Xilinx Virtex 5. The design contains > several power nets sourced by TIEOFFs and feeding some of the slices > used by the design. A closer look at several of the LUT equations with a > power net input, shows that the power net input does not actually affect > the output of the LUT. > > For example, assuming two nets are feeding a slice. One of the nets is a > power net feeding input A6, while the other net is feeding input A1. The > LUT equation could be something like the following: > <A6LUT>=(A6+~A6)*(A2) > What is confusing to me is the fact that (A6+~A6) is always true, thus > should not affect the output of the LUT. If you model the LUT as an ideal device that behaves according to its truth table, then indeed the "unused" inputs have no effect on the output. But LUTs are more like rams: they don't implement logic functions with gates. Instead, they look up answers based on an address you supply, and they use all of their inputs to form that address regardless of the contents of the truth table. Regards, AllanArticle: 150890
On 19 Feb., 17:12, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > Hi guys, > I'm searching for a general mathematical definition of an FPGA. > I propose this y=F(x,u) where y is a vector of output , u is a vector > of input and x is a vector of internal state and F is a certain > function of x,u. Have you some idea to generalize more this > definition? > Thank you, > Silvio Andre DeHon developed a taxonomy that views an FPGA as a processor that executes one very complex instruction word. The theoretical portions of that work might be a good starting point for you: http://www.seas.upenn.edu/~andre/abstracts/dehon_phd.html Kolja SulimmaArticle: 150891
On 19 Feb., 18:14, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > But with states what would be the point? =A0The Function could only > describe a portion of the design with that portion including only the > last state point to outputs and the time based nature of logic states > would not be described. Actually, no, it is pretty common thing to reason about state machines in an abstract way exactly in the way the OP did. For example in model checking. But also in synthesis. A programmed FPGA is just a digital circuit, so one can simple look up the definitions that are used for these. Depending on what you want to do, essentially there are to views on the problem. Either the state transfer funktion: (next_state, output) =3D F(current_state, input) output_series =3D F(input_series) In general the FPGA of course is included in these views, as the configuration is state, and the config pins are inputs. But in many cases it might make sende to capture the notion that the configuration is different from the state captured in the DFFs and BRAMs. So one might write: (next_state, output) =3D F(current_state, input, configuration) or output_series =3D F(input_series, configuration) Of course this does ignore dynamic reconfiguration, so you might end up with: (next_state, output, next_configuration) =3D F(current_state, input, current_configuration) output_series =3D F(input_series, initial_configuration) Kolja SulimmaArticle: 150892
On Feb 19, 11:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote: > Hi guys, > I'm searching for a general mathematical definition of an FPGA. > I propose this y=3DF(x,u) where y is a vector of output , u is a vector > of input and x is a vector of internal state and F is a certain > function of x,u. Have you some idea to generalize more this > definition? > Thank you, > Silvio Your definition is not complete. 1. There needs to be computation of the next state as a function of current state and inputs: x(t+1) =3D g(x(t), u); where x(t) is the internal state at time 't' and the equation tells you how to map to the next clock cycle 't+1' 2. Some things are probabilistic: When a signal is generated within one clock domain but sampled in another clock domain it is not generally possible to state on exactly which clock cycle in the sampling clock domain the received signal will arrive. It might arrive one clock cycle later if the signal violates the setup time. For whatever your purposes are, maybe you don't care about this but since it is not clear why you posed the question, I thought I'd point it out 3. Some things are dependent on things that cannot be predicted exactly. An example here would be the amount of time it takes a phase- locked loop to lock on to the input clock. The output of the PLL is used to clock the state logic, but you can't say exactly when that clock will be available. Again, I'm suspecting that this is more detailed than what you're looking for. 4. Since an FPGA can be reprogrammed, the f() and g() functions change over time (typically only once, but not necessarily just once). Kevin JenningsArticle: 150893
On Feb 19, 4:07=A0pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 19 Feb., 18:14, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wrote= : > > But with states what would be the point? =A0The Function could only > > describe a portion of the design with that portion including only the > > last state point to outputs and the time based nature of logic states > > would not be described. > > Actually, no, it is pretty common thing to reason about state machines > in an abstract way exactly in the way the OP did. > For example in model checking. But also in synthesis. > > A programmed FPGA is just a digital circuit, so one can simple look up > the definitions that are used for these. > Depending on what you want to do, essentially there are to views on > the problem. Either the state transfer funktion: > (next_state, output) =3D F(current_state, input) > output_series =3D F(input_series) > > In general the FPGA of course is included in these views, as the > configuration is state, and the config pins are inputs. > But in many cases it might make sende to capture the notion that the > configuration is different from the state captured in the DFFs and > BRAMs. > So one might write: > (next_state, output) =3D F(current_state, input, configuration) > or > output_series =3D F(input_series, configuration) > > Of course this does ignore dynamic reconfiguration, so you might end > up with: > (next_state, output, next_configuration) =3D F(current_state, input, > current_configuration) > output_series =3D F(input_series, initial_configuration) > > Kolja Sulimma The OP had two inputs to the Function, external inputs and the current internal state, with the result of the Function being the external outputs. The OP made no mention of clocks/time factors or that the next internal state was part of the output function. In this circumstance a vast majority of the internal states don't matter if they don't factor directly on the output state. I find the concept of trying to distill a complex state and time dependent into a simple mathematical equation versus the HDL that describes the system of questionable benefit. Ed McGettigan -- Xilinx Inc.Article: 150894
On Sat, 19 Feb 2011 21:09:54 -0800 (PST), Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: >The OP had two inputs to the Function, external inputs and the current >internal state, with the result of the Function being the external >outputs. The OP made no mention of clocks/time factors or that the >next internal state was part of the output function. In this >circumstance a vast majority of the internal states don't matter if >they don't factor directly on the output state. > >I find the concept of trying to distill a complex state and time >dependent into a simple mathematical equation versus the HDL that >describes the system of questionable benefit. > >Ed McGettigan The two equations: x[k+1] = F(x[k], u[k]) and y[k] = H(x[k], u[k]) (where x is the state, u is input, y is output, F is the state transition matrix and H is output matrix) are called state space equations of a control system and they have a large body of knowledge behind them. Analysis of such systems have bewen studied for a long time and a lot of useful theory exists for such analysis. If an FPGA configuration could be described by such a set of equations, one could decide observability, controllability, stability and other features of such a system. The potential benefits are actually enormous. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150895
On Feb 19, 8:03=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Feb 19, 10:04=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> > wrote: > > > > > > > > > > > On Feb 19, 6:14=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Feb 19, 8:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> wro= te: > > > > > Hi guys, > > > > I'm searching for a general mathematical definition of an FPGA. > > > > I propose this y=3DF(x,u) where y is a vector of output , u is a ve= ctor > > > > of input and x is a vector of internal state and F is a certain > > > > function of x,u. Have you some idea to generalize more this > > > > definition? > > > > Thank you, > > > > Silvio > > > > A mathematical definition for an FPGA??? =A0 =A0Is there a mathematic= al > > > definition for a CPU or a chalkboard? > > > > If the design that was implemented in a FPGA included no states > > > (registers, latches, RAMs, etc) it would be possible define the > > > function of the combinatorial function that was implemented in the > > > FPGA as y=3DF(u) using your definitions. > > > > But with states what would be the point? =A0The Function could only > > > describe a portion of the design with that portion including only the > > > last state point to outputs and the time based nature of logic states > > > would not be described. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > I think, it's not correct, the internal state variables x are the > > smallest possible subset of system variables that can represent the > > entire state of the system at any given time. > > Silvio- Hide quoted text - > > > - Show quoted text - > > Please explain which part of what I wrote you think is incorrect. > > Ed McGettigan > -- > Xilinx Inc. Sorry, the second part of you message ... this part: > > But with states what would be the point? The Function could only > > describe a portion of the design with that portion including only the > > last state point to outputs and the time based nature of logic states > > would not be described.Article: 150896
On Feb 19, 9:02=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > On Sat, 19 Feb 2011 08:12:29 -0800, silvio.baccari wrote: > > Hi guys, > > I'm searching for a general mathematical definition of an FPGA. I > > propose this y=3DF(x,u) where y is a vector of output , u is a vector o= f > > input and x is a vector of internal state and F is a certain function o= f > > x,u. Have you some idea to generalize more this definition? > > Thank you, > > Silvio > > By the time you captured all of the "FPGA-ness" you would have a > mathematical description that would be so complex it would be useless. > > In general the art of mathematical modeling lies not in capturing > everything there is to capture about a thing that you want to model. =A0 > Rather, it lies in capturing _just enough_ information about the thing so > that you can get a _representative_ answer for your _immediate problem_. = =A0 > Capture too much information, and at best your model will be confusing, > and at worst it'll be so unwieldy that you can't do anything useful with > it. > > So -- tell us what you want to do, and maybe we can help you model > whatever subset of FPGA behavior it is that you really need modeled. > > --http://www.wescottdesign.com I'm interested only to the logical behavior of an FPGA; not the complex (transitory) phenomenons between two steady states and the way to implement the logic core and the memory ones. Thanks, SilvioArticle: 150897
On Feb 20, 2:10=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Feb 19, 11:12=A0am, "silvio.baccari" <silvio.bacc...@gmail.com> > wrote: > > > Hi guys, > > I'm searching for a general mathematical definition of an FPGA. > > I propose this y=3DF(x,u) where y is a vector of output , u is a vector > > of input and x is a vector of internal state and F is a certain > > function of x,u. Have you some idea to generalize more this > > definition? > > Thank you, > > Silvio > > Your definition is not complete. > 1. There needs to be computation of the next state as a function of > current state and inputs: =A0x(t+1) =3D g(x(t), u); where x(t) is the > internal state at time 't' and the equation tells you how to map to > the next clock cycle 't+1' > 2. Some things are probabilistic: =A0When a signal is generated within > one clock domain but sampled in another clock domain it is not > generally possible to state on exactly which clock cycle in the > sampling clock domain the received signal will arrive. =A0It might > arrive one clock cycle later if the signal violates the setup time. > For whatever your purposes are, maybe you don't care about this but > since it is not clear why you posed the question, I thought I'd point > it out > 3. Some things are dependent on things that cannot be predicted > exactly. =A0An example here would be the amount of time it takes a phase- > locked loop to lock on to the input clock. =A0The output of the PLL is > used to clock the state logic, but you can't say exactly when that > clock will be available. =A0Again, I'm suspecting that this is more > detailed than what you're looking for. > 4. Since an FPGA can be reprogrammed, the f() and g() functions change > over time (typically only once, but not necessarily just once). > > Kevin Jennings Hi Kevin, the definition of next states is essential for a correct definition (first point). The second and third point is relative to the simulation of the model and I think it is a valid consideration, but it is off topic. The fourth point is a good consideration ... so the functions F and G are time variant. SilvioArticle: 150898
On Wed, 16 Feb 2011 17:11:04 -0000, "Phil Jessop" wrote: >Jeez! Is this was thinking in HDL does for you? >See my other post!s Errrm, no, it's what thinking about some of the possible hidden assumptions and pitfalls may do for you. Something that does not appear to have much troubled your thinking in schematic :-) -- Jonathan BromleyArticle: 150899
> I propose this y=F(x,u) where y is a vector of output , u is a vector of > input and x is a vector of internal state and F is a certain function of > x,u. Have you some idea to generalize more this Sure. You don't have any state changes, except for outputs. At least make it a FSM You also only allow determistic functions, omitting a large class of timing errors The real question might be - what do you hope to do with this definition. What you have isn't specific to FPGAs. Maybe something that composes functions from states, routing, and LUTs? -- mac the naïf
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