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Messages from 151375

Article: 151375
Subject: Xilinx DDR3 controller: rewrite mode registers
From: Martin Herrmann <martin@famherrmann.de>
Date: Tue, 29 Mar 2011 15:25:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi,

I am using the Xilinx DDR3 controller (MIG). I need to trigger rewriting
the mode registers of the DDR3 component during operation. The
controller does not support this, so I'm working on a modification.

The mode register write has to be performed after all read and write
commands submitted so far have been processed (more specifically, after
a complete row has been read or written). Any ideas on how to implement
this?

One possible approach is to wait until all bank machines are idle,
trigger a refresh (so the operation won't be interrupted by the refresh
timer), connect the address and control lines to my own logic instead of
the memory controller and performing the mode register write manually
(making sure to restore the connection in time for the next refresh
operation).

However, this approach seems a bit like a kludge to me. Also, I'm not
sure how to avoid the ZQ calibration or a periodic read getting in the
way.

Any better ideas? Ideally, I would be able to enqueue a command to write
the mode registers, just like I can enqueue read and write commands. I
use "strict" ordering, so reordering should not be an issue.


Martin
-- 
Wise men don't need advice. Fools don't take it.
  - Benjamin Franklin


Article: 151376
Subject: EDK - program behavior
From: Tobias Baumann <ttobsen@hotmail.com>
Date: Tue, 29 Mar 2011 18:13:12 +0200
Links: << >>  << T >>  << A >>
Hi

Last time I asked something about max array size. Now I have another 
problem and I think it has also to do with the memory.

When I have a bigger program, sometimes it run how I want. But if I 
commented something out, the programm stops very early (the commented 
part are some thousand std_outs in a loop or something else, no data 
manipulation what influence my control flow). Sometimes it restarts at a 
specific point. It doesn't do what I want, but it does it allways the 
same way. So the problem seems to be reproducible, but arbitrarily.

So what can the problem be? Unfortunately, I can't post a example, 
because the code is to large (but if you interessted I can send them via 
email).

I need some ideas where I have to search for the problems. Thanks for 
every direct help or information where I can find some.

Regards,
Tobias

Article: 151377
Subject: Re: Xilinx DDR3 controller: rewrite mode registers
From: Gabor <gabor@szakacs.invalid>
Date: Tue, 29 Mar 2011 14:35:46 -0400
Links: << >>  << T >>  << A >>
Martin Herrmann wrote:
> Hi,
> 
> I am using the Xilinx DDR3 controller (MIG). I need to trigger rewriting
> the mode registers of the DDR3 component during operation. The
> controller does not support this, so I'm working on a modification.
> 
> The mode register write has to be performed after all read and write
> commands submitted so far have been processed (more specifically, after
> a complete row has been read or written). Any ideas on how to implement
> this?
> 
> One possible approach is to wait until all bank machines are idle,
> trigger a refresh (so the operation won't be interrupted by the refresh
> timer), connect the address and control lines to my own logic instead of
> the memory controller and performing the mode register write manually
> (making sure to restore the connection in time for the next refresh
> operation).
> 

Don't even think about inserting your control logic at the chip
interface.  The timing won't work.

> However, this approach seems a bit like a kludge to me. Also, I'm not
> sure how to avoid the ZQ calibration or a periodic read getting in the
> way.
> 
> Any better ideas? Ideally, I would be able to enqueue a command to write
> the mode registers, just like I can enqueue read and write commands. I
> use "strict" ordering, so reordering should not be an issue.
> 
> 
> Martin

You talk about "The" DR3 controller, but really there's a different one
for each device family.  For the ones that don't use the hard MCB core
you might find the right source module that schedules the refresh
and other operations.  The mode register write requires all banks
to be precharged, as does the refresh command, so inserting the
mode write just before starting a refresh would be a good place
for it (or following a refresh after waiting Trfc).

-- Gabor

Article: 151378
Subject: only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley
From: Vikram <vkr101@gmail.com>
Date: Tue, 29 Mar 2011 12:42:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
FPGA Camp (http://www.fpgacentral.com/fpgacamp)  is a conference,
which brings engineers together to discuss FPGA, mainly NextGen FPGA
technology, application, methodology, best practices and challenges.
Also provide a location to meet other local FPGA designers to share
their stories.

Since its inception in Year 2009, FPGA Camp decided to stay vendor
neutral. The attendance is completely FREE and so is putting up a
booth. Due to the this approach we soon have been coined as an Open
Source conference by Industry leaders like Eric Bogatin, Colin Warwick
& Max Maxfield.

REGISTER NOW http://bit.ly/fcjHCJ

The event will focus on demonstrating key technologies available to
bring processor inside the FPGAs. It will provide a glimpse of what to
expect in the future, and how to use these great features for your
next project.

AGENDA (visit http://www.fpgacentral.com/fpgacamp for details)
4:00 PM Exhibit booths
4:25 PM Introductions
4:30 PM Tech Talk 1: On Die Instrumentation
5:05 PM Tech Talk 2: PCIe 3.0 case study
5:40 PM Tech Talk 3: Design Choices for Embedded Real-Time Control
Systems
6:15 PM Dinner & Exhibit
6:45 PM Vendor Presentation
7:00 PM Panel: "State Of FPGAs - Current & Future" - Moderated by Dave
Orecchio, CEO, Gaterocket
8:15 PM Closing

Speakers & Moderator
Dave Orecchio - GateRocket Gordon Hands - Lattice Chris Eddington -
Synopsys Dave Bursky - Chip Design Magazine and more...

Sponsors
Lattice Semiconductor
Altium
Rhino Labs
Agilent Technologies
IEEE CNSV
PLDA

REGISTER NOW http://bit.ly/fcjHCJ (registration is FREE & Simple)

Organized by: FPGA Cenral ( http://www.fpgacentral.com )

Article: 151379
Subject: Re: Xilinx DDR3 controller: rewrite mode registers
From: Martin Herrmann <martin@famherrmann.de>
Date: Wed, 30 Mar 2011 06:39:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
Gabor (2011-03-29):
>> One possible approach is to wait until all bank machines are idle,
>> trigger a refresh (so the operation won't be interrupted by the refresh
>> timer), connect the address and control lines to my own logic instead of
>> the memory controller and performing the mode register write manually
> 
> Don't even think about inserting your control logic at the chip
> interface.  The timing won't work.

I realize that the timing is quite challenging for the data lines, but
isn't it easier for the address and control (RAS#, CAS#, WE#) lines?


>> Any better ideas? Ideally, I would be able to enqueue a command to write
>> the mode registers, just like I can enqueue read and write commands. I
>> use "strict" ordering, so reordering should not be an issue.
> 
> You talk about "The" DR3 controller, but really there's a different one
> for each device family.  

Of course - my mistake. I'm using a Virtex6 device.


> and other operations.  The mode register write requires all banks
> to be precharged, as does the refresh command, so inserting the
> mode write just before starting a refresh would be a good place
> for it (or following a refresh after waiting Trfc).

That sounds like a good idea, I will have a look at the refresh logic.


Martin
-- 
Wise men don't need advice. Fools don't take it.
  - Benjamin Franklin


Article: 151380
Subject: Re: MCode Block Problem
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 30 Mar 2011 13:20:00 +0100
Links: << >>  << T >>  << A >>
"mah@k-space.org" <mah@n_o_s_p_a_m.k-space.org> writes:

> HELLO
> I want to use the below function to the xilinx system generator MCode
> Block, but I faced some errors . how to solve this problem.The code
> executed well in matlab but when I used MCode Block it gave me errors.
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> %the function is:
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> function s=dyn_focusing(RF,Lin)
> prec = {xlSigned, 16, 0, xlRound, xlWrap};
> persistent m, m=xl_state(zeros(1,len),prec);
> s=m;
> len=512;
> for k=1:len
>   if Lin(k)<=len
>       s(k)=RF(1,Lin(k));
>       if Lin(k)>len
>         s(k)=0;
>       end
>   end 
> end
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  where RF and Lin are (1X512) array
>

It might help us to help you if you tell us what errors you get!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 151381
Subject: Re: MAX II CPLD and I2S Clock divider jitter
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Wed, 30 Mar 2011 19:23:45 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Mon, 28 Mar 2011 21:29:47 -0700, Mark wrote:

> On Mar 29, 8:25 am, Jim Granville <j.m.granvi...@gmail.com> wrote:
>> On Mar 28, 11:01 pm, Mark <markjsu...@gmail.com> wrote:
>>
>> > 3) Use 1-to-2 buffer (74xxx series) after the oscillator output and
>> > split the clock to CPLD and the DAC.
>>
>>  If you are jitter paranoid, then it is always best to avoid going
>> thru complex logic.
>>
>> -jg
> 
> Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock
> buffers? Is there any advantage of using clock buffers over normal
> buffers for digital audio?

Neither 74LS nor 74HC. Possibly 74AC, or purpose built clock buffers.
Fast clean edges (not HC) and full signal level switching (not LS) are 
important, but watch for edges so fast they propagate right through into 
the audio output.

Also, run the buffer from its own power - at least a LC Pi filter to keep 
its supply quiet. (And I recommend at least the same, or separate 
regulators, to keep FPGA switching noise out of the main logic supply.)

I used 74AC74 for re-clocking on an audio DAC. The effect on glitch 
energy from the (R-2R ladder DAC) was noticeable, and groups of listeners 
claimed to hear differences with different clock buffers (As I did). (I 
started with 74F74, when I switched to 74AC they stopped sending DACs 
back to the factory.) The US magazine "Stereophile" gave the result a 
"Class A" rating, for what that's worth.

- Brian


Article: 151382
Subject: Re: EDK - program behavior
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 31 Mar 2011 03:34:13 -0500
Links: << >>  << T >>  << A >>
>Hi
>
>Last time I asked something about max array size. Now I have another 
>problem and I think it has also to do with the memory.
>
>When I have a bigger program, sometimes it run how I want. But if I 
>commented something out, the programm stops very early (the commented 
>part are some thousand std_outs in a loop or something else, no data 
>manipulation what influence my control flow). Sometimes it restarts at a 
>specific point. It doesn't do what I want, but it does it allways the 
>same way. So the problem seems to be reproducible, but arbitrarily.
>
>So what can the problem be? Unfortunately, I can't post a example, 
>because the code is to large (but if you interessted I can send them via 
>email).
>
>I need some ideas where I have to search for the problems. Thanks for 
>every direct help or information where I can find some.
>
>Regards,
>Tobias
>

You might get a response if you post on the Xilinx forum at:
http://forums.xilinx.com/t5/EDK-and-Platform-Studio/bd-p/EDK
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151383
Subject: Re: EDK - program behavior
From: Tobias Baumann <tobias.baumann@elpra.de>
Date: Thu, 31 Mar 2011 14:20:16 +0200
Links: << >>  << T >>  << A >>
On 31.03.2011 10:34, RCIngham wrote:
>
> You might get a response if you post on the Xilinx forum at:
> http://forums.xilinx.com/t5/EDK-and-Platform-Studio/bd-p/EDK
> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

I did it. I hope there's someone who can help. Here's the link:

http://forums.xilinx.com/t5/Embedded-Processing/Microblaze-prorgam-behavior/td-p/140198

Article: 151384
Subject: MIPI CSI-2 camera interface to parallel
From: nico@puntnl.niks (Nico Coesel)
Date: Thu, 31 Mar 2011 17:12:03 GMT
Links: << >>  << T >>  << A >>

I've run into a bit of a problem. A camera module I would like to use
has a MIPI CSI-2 interface. The SoC I want to connect to only has a
parallel camera interface. How difficult would it be to use an FPGA in
between? Or are there already MIPI to parallel converters?

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 151385
Subject: Ideal FPGA Development Kit
From: allen <ayhoung@gmail.com>
Date: Thu, 31 Mar 2011 22:43:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hey guys,

I work in the FPGA development kit sector, and I was just looking to
see if you guys had any ideas regarding what would be your MUST HAVE
features on an FPGA dev kit?

Thanks in advance!
Allen

Article: 151386
Subject: Re: Ideal FPGA Development Kit
From: backhus <goouse99@googlemail.com>
Date: Thu, 31 Mar 2011 23:18:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 1 Apr., 07:43, allen <ayho...@gmail.com> wrote:
> Hey guys,
>
> I work in the FPGA development kit sector, and I was just looking to
> see if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
>
> Thanks in advance!
> Allen

Hi Allen,
the only thing on which everyone will positively agree is an FPGA at
least. (Oh, I forgot to mention the RS-232! :-)  )
Everything else depends on the application, even the exact type of
FPGA.

You either end up with something that is so mediocre, that only
beginners will use it if the price is low enough, but remains useless
for professional designers,
Or the board will be so overloaded and expensive, that noone can or
will spend the money for it.

Look for example at the boards offered on the Xilinx webpage.
There you find a number of boards for each FPGA family. You almpost
always find a Starter board, some DSP specialized board, some Video
board, maybe a FPGA computing board and so on.

Maybe you could explain a little more about the background and
intention of your query.

Have a nice synthesis
  Eilert

Article: 151387
Subject: Re: Spartan 3e FPGA and data from matlab workspace.
From: backhus <goouse99@googlemail.com>
Date: Thu, 31 Mar 2011 23:22:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 29 Mrz., 17:18, "cavalry" <Cavalrys@n_o_s_p_a_m.gmail.com> wrote:
> Hey,
>
> I need to send data(1158 samples x 21 features) to Spartan 3e FPGA board
> from the matlab workspace with rs232 and then do K-means classification o=
n
> that and then return the data (1158samples x 1 group(1-4)) from the FPGA
> back into the matlab workspace. How do I do that? Kindly let me know if
> there is some tutorial which is spartan 3e specific on this which can tel=
l
> me how to do it step by step.
>
> Thanks and Regards,
> Cavalry
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Hi,
search the forums at the Xilinx page for this.
It's a common topic.
One more hint if you are a beginner:
Picoblaze and kcuart may be helpful for your approach, though it's a
slow connection.

Another approach would be using HW-Cosimulation with sysgen, which may
work faster, but is expensive.

Have a nice synthesis
  Eilert

Article: 151388
Subject: Re: Ideal FPGA Development Kit
From: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?= <dincay@gmail.com>
Date: Fri, 1 Apr 2011 01:03:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 1, 7:43=A0am, allen <ayho...@gmail.com> wrote:
> Hey guys,
>
> I work in the FPGA development kit sector, and I was just looking to
> see if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
>
> Thanks in advance!
> Allen

It depends on the purpose of the board. For beginners and hobbyst
"must have" features will be different. For professional users "must
have" features will be different. But there may be some common
features like rs232 or external memory.

Article: 151389
Subject: Re: Ideal FPGA Development Kit
From: jozamm <jozamm@gmail.com>
Date: Fri, 1 Apr 2011 01:55:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

A student board should contain :

- Switches
- Buttons
- Seven Segments Displays (Multiplexed)
- LCD or a port for a standard 16x2 LCD
- Port for an optional graphical LCD (very nice)
- RS232
- USB
- Memory=20
- Minimal RGB driver
- Optional port for more Clock sources
- A/D converter
- D/A converter
- An add-on for motor driving (seperate board)
- PS/2 interface

A good idea for educational board is to that the FPGA could be changed e.g.=
 Altera or Xilinx. A decent board should have enough features so that a stu=
dent can develop his graduate project on it so that students can spend more=
 time on developing the hardware.

Professional board for computing purposes
- Lots of Memory
- Good Video driver
- 1 or 2 A/D converter
- 2 or 3 USB version 3
- PCI interface
- Slot for more memory
- 4 line LCD (debugging etc.)
- Keyboard interface

These are some ideas, Good luck for your development board

Regards,

Joseph

Article: 151390
Subject: Re: Ideal FPGA Development Kit
From: "Michael Kellett" <nospam@nospam.com>
Date: Fri, 1 Apr 2011 11:44:11 +0100
Links: << >>  << T >>  << A >>

"allen" <ayhoung@gmail.com> wrote in message 
news:81b56b55-23ce-42a4-804a-f6cbc82955fc@q40g2000prh.googlegroups.com...
> Hey guys,
>
> I work in the FPGA development kit sector, and I was just looking to
> see if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
>
> Thanks in advance!
> Allen

I've never seen any point in general purpose development boards - I design a 
board for the job. Reference designs are useful.

If I were going to attempt something with a big feasibility issue it might 
be worth buying a fancy dev board but it hasn't happened yet.

Michael Kellett 



Article: 151391
Subject: Re: Ideal FPGA Development Kit
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 01 Apr 2011 08:48:13 -0700
Links: << >>  << T >>  << A >>
On 3/31/2011 10:43 PM, allen wrote:
> Hey guys,
>
> I work in the FPGA development kit sector, and I was just looking to
> see if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
>
> Thanks in advance!
> Allen

Somewhere that I can actually solder down components.  Plated through 
holes on 0.100" centers, with some grounds and VCCIOs interspersed.  If 
I'm going to the dev kit it's either because a) I'm trying to get up to 
speed on a brand spanking new processor or b) I'm going off-datasheet 
and need to get measured results for things they won't spec.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 151392
Subject: Fun with Xilinx Constraints
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 01 Apr 2011 09:14:32 -0700
Links: << >>  << T >>  << A >>
I'm working on a Spartan 3 design and trying to figure out how, if at 
all, I can constrain what I'm looking for without resorting to hand 
placement and directed routing.

I've got an analog pulse that feeds 4 comparators with different 
thresholds.  This gives me 4 pulses of which each narrower one is 
contained entirely in time by each wider one, like the side view of the 
Towers of Hanoi experiment.  The widest will be 3-4 ns, the narrowest 
will be narrow enough to not consistently be able to trip the internal 
flops.  They'll be coming in at up to 80 MHz.

Given that this is pretty fast for an S3, I've lit on the idea of using 
each pulse to clock a T-flop, then resynchronize the output of the T at 
200 MHz into an XOR change detector; the classic pulse-toggle-pulse 
domain crosser but directly clocked rather than clock enabled.  Code 
(untested) at the end of this message.

So I've got a 2 ns event (rising edges only) and a 5 ns clock period.  I 
need to make sure that all of my resynchronized pulses come out during 
clock cycle n or n+1.  Which, so near as I can figure, means that I want 
to have no more than 3 ns of routing delay skew on these signals, from 
the pins through the Ts to the D input on the first synchronizer stage.

Anyone have the foggiest how to bully the tools into pulling this off?

Thanks,
Rob

--------
entity fast_rising_edge_det is

  generic (
   SYNC_STAGES  : positive := 2;
   REGISTER_OUTPUT : boolean  := true
   );         -- Number of delay flip-flops

  port (
   edge   : in  std_logic;   -- Edge to be detected
   clk    : in  std_logic;   -- Clock to synchronize the output to.
   pulse_out : out std_logic);  -- Output pulse for the rising edge.

end entity fast_rising_edge_det;

architecture Behavioral of fast_rising_edge_det is

  signal toggle    : std_logic        := '0';
  signal delay_stages : std_logic_vector(SYNC_STAGES-1 downto 0)
                           := (others => ''0'');
  signal old_val   : std_logic        := '0';
  signal change    : std_logic;

begin  -- architecture Behavioral

  TFLOP : toggle <= not toggle when rising_edge(edge);

  DLINE : process (clk) is
  begin  -- process
   if rising_edge(clk) then  -- rising clock edge
    if (SYNC_STAGES = 1) then
     delay_stages(0) <= toggle;
    else
     delay_stages <= delay_stages(SYNC_STAGES-2 downto 0) & toggle;
    end if;
   end if;

   old_val <= delay_stages(delay_stages'high);
  end process;

  change <= old_val xor delay_stages(delay_stages'high);

  REG_OUT : if (REGISTER_OUTPUT) generate
   pulse_out <= change when rising_edge(clk);
  end generate REG_OUT;

  NOREG_OUT : if (not REGISTER_OUTPUT) generate
   pulse_out <= change;
  end generate NOREG_OUT;

end architecture Behavioral;

--------

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 151393
Subject: Re: Ideal FPGA Development Kit
From: "scrts" <mailsoc@[remove@here]gmail.com>
Date: Fri, 1 Apr 2011 23:33:20 +0300
Links: << >>  << T >>  << A >>
In my opinion:
1. FT245(or better FT2232 in FIFO mode - faster) for USB data transfer - 
this can be implemented easily either on PC side or FPGA side.
2. DDR or DDR2 memory. Better 2 separate chips if possible. Also easy to 
implement, because all vendors offer controllers for their FPGAs.
3. Ethernet.
4. IO expansions (well routed, not like Xilinx made on their S3E kit).

These are 4 basic things.
If I could find a PCI-E board + at least 2 LVDS RX and 2 TX outputs using 
SMA or other useful connectors in addition to everything I mentioned 
before - that would be perfect.

There are plenty of boards for beginners, but nothing in the middle range to 
get more specific. The Cyclone IV GX starter kit would be just perfect, 
however it has no expansion IOs... Other PCI-E boards cost too much.



"allen" <ayhoung@gmail.com> wrote in message 
news:81b56b55-23ce-42a4-804a-f6cbc82955fc@q40g2000prh.googlegroups.com...
> Hey guys,
>
> I work in the FPGA development kit sector, and I was just looking to
> see if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
>
> Thanks in advance!
> Allen 



Article: 151394
Subject: Doubts about OC PCI Bridge
From: Sink0 <sink00@gmail.com>
Date: Fri, 1 Apr 2011 14:56:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am trying to make use of OC PCI Bridge, and it is working fine on
the PCI Target side. But when i am trying to master the bus using my
wishbone slave i was having a wrong behavior from the Wb slave of the
bridge. When i try to read from the PC, the bridge should send a RTY
until the data is ready.... but when i request the first time.. the
slave assert the retry but never disassert, even after i disassert STB
and CYC... i was looking at the verilog code at the pci_wb_slave.v but
i cant find the reason for this behavior.... Any one ever had this
problem? Any one have the contact with Miha Dolenc? I tryed sending an
email to opencores email but i think it does not exist anymore..

Thank you!

Article: 151395
Subject: Re: Ideal FPGA Development Kit
From: Allan Herriman <allanherriman@hotmail.com>
Date: 02 Apr 2011 02:13:09 GMT
Links: << >>  << T >>  << A >>
On Thu, 31 Mar 2011 22:43:44 -0700, allen wrote:

> Hey guys,
> 
> I work in the FPGA development kit sector, and I was just looking to see
> if you guys had any ideas regarding what would be your MUST HAVE
> features on an FPGA dev kit?
> 
> Thanks in advance!
> Allen


Not that I use dev kits, but if I did I would look for the following:

- For an FPGA with transceivers, I would want two of them brought out to 
a pair of SFP+ sockets.  The PCB routing should be of sufficient quality 
to allow this to work at 10Gb/s.
The SFP+ control signals would also need to be connected to the FPGA (via 
level translators if the FPGA can't handle 3.3V hotplug signals).

- Sites on the PCB for at least a few clock oscillators suitable for 
clocking the transceivers.  These would be LVDS or PECL oscillators, not 
the CMOS ones that don't work so well above a few hundred MHz.  One or 
two sites would be populated with oscillators that would allow the 
transceivers to do 1GbE and 10GbE.  (The spare sites are to allow the 
user to solder in their own oscs to support other protocols.)  

- A USB to JTAG programming dongle built-in, probably using something 
like an FT2232H or FT232H.
- Open source host driver software for the built-in JTAG programming 
hardware, with binaries available for at least WinXP, Win7 and major 
flavours of Linux.

Regards,
Allan

Article: 151396
Subject: Re: Ideal FPGA Development Kit
From: John Adair <g1@enterpoint.co.uk>
Date: Sat, 2 Apr 2011 02:55:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Much delayed but will hopefully be actually be on show at ESC Silicon
Valley in May our Raggedstone3 will have most of this for you.

John Adair
Enterpoint Ltd.

On Apr 1, 9:33=A0pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote:
> In my opinion:
> 1. FT245(or better FT2232 in FIFO mode - faster) for USB data transfer -
> this can be implemented easily either on PC side or FPGA side.
> 2. DDR or DDR2 memory. Better 2 separate chips if possible. Also easy to
> implement, because all vendors offer controllers for their FPGAs.
> 3. Ethernet.
> 4. IO expansions (well routed, not like Xilinx made on their S3E kit).
>
> These are 4 basic things.
> If I could find a PCI-E board + at least 2 LVDS RX and 2 TX outputs using
> SMA or other useful connectors in addition to everything I mentioned
> before - that would be perfect.
>
> There are plenty of boards for beginners, but nothing in the middle range=
 to
> get more specific. The Cyclone IV GX starter kit would be just perfect,
> however it has no expansion IOs... Other PCI-E boards cost too much.
>
> "allen" <ayho...@gmail.com> wrote in message
>
> news:81b56b55-23ce-42a4-804a-f6cbc82955fc@q40g2000prh.googlegroups.com...
>
> > Hey guys,
>
> > I work in the FPGA development kit sector, and I was just looking to
> > see if you guys had any ideas regarding what would be your MUST HAVE
> > features on an FPGA dev kit?
>
> > Thanks in advance!
> > Allen


Article: 151397
Subject: Virtex 5 PCIe Debug
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Sat, 02 Apr 2011 05:38:59 -0500
Links: << >>  << T >>  << A >>
I am trying to debug a Virtex 5 PCI Express core. When I insert it into a
PC it is not detecting it. I have chipscope connected to the LTSSM state
machine signals and it seems to be stuck in state 2. Is there any
documentation from Xilinx that gives info about the states and the signals
that are exchanged during the link training?

Thanks

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151398
Subject: Re: Ideal FPGA Development Kit
From: "PovTruffe" <PovTache@gaga.invalid>
Date: Sat, 2 Apr 2011 13:41:58 +0200
Links: << >>  << T >>  << A >>
"Allan Herriman" <allanherriman@hotmail.com> a crit :
> - A USB to JTAG programming dongle built-in, probably using something
> like an FT2232H or FT232H.
> - Open source host driver software for the built-in JTAG programming
> hardware, with binaries available for at least WinXP, Win7 and major
> flavours of Linux.


What are the advantages of using this chip compared to using the
manufacturer USB cable ?



Article: 151399
Subject: Re: Ideal FPGA Development Kit
From: Allan Herriman <allanherriman@hotmail.com>
Date: 02 Apr 2011 12:34:58 GMT
Links: << >>  << T >>  << A >>
On Sat, 02 Apr 2011 13:41:58 +0200, PovTruffe wrote:

> "Allan Herriman" <allanherriman@hotmail.com> a écrit :
>> - A USB to JTAG programming dongle built-in, probably using something
>> like an FT2232H or FT232H.
>> - Open source host driver software for the built-in JTAG programming
>> hardware, with binaries available for at least WinXP, Win7 and major
>> flavours of Linux.
> 
> 
> What are the advantages of using this chip compared to using the
> manufacturer USB cable ?


Nobody else in the office can borrow it if it's soldered to your board.


Allan



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