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Messages from 157850

Article: 157850
Subject: Directly connect two XAUI ports inside FPGA
From: Guenther Wenninger <g!!rw@bitschubbser.org>
Date: Mon, 20 Apr 2015 17:40:41 +0200
Links: << >>  << T >>  << A >>
Hi all,

to implement something like a passthru mode, we want to directly
connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.

Therefor we did instantiate two XAUI-cores and connected txd/txc from
one core with the rxd/rxc from the other core and vice versa.
Because both cores use a different refclk we simply added two
synchronizer FFs in between.

In our test-design this works. But when added to the full design
this code fails (the data after the synchronizer FFs seems scrambled).
Is it at all possible to directly connect two XAUI cores?
Is it possible to connect two blocks with the same clock frequency
but - probably - different clock phase just using 2xFFs?

Kind regards,
/gw

-- 
For reply: Remove the additional chars from the local part.

Article: 157851
Subject: Re: Choosing the right FPGA board
From: Brad Whitlock <bradley.whitlock@gmail.com>
Date: Mon, 20 Apr 2015 14:24:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, April 20, 2015 at 6:01:43 AM UTC-6, FrewCen wrote:
> Hello!
>=20
> I have several years of experience in programming, and I'd like to move=
=20
> on to FPGAs to enjoy more fun.
>=20
> As I have a limited budget for my playing with electronics, I'd like to=
=20
> choose the most versatile board for the best price with a decent support=
=20
> from manufacturer. I'm a student, so I guess the academic prices apply=20
> for me.
>=20
> I tried to do my own research on google. What I wanted to have on my=20
> board was:
>  - VGA/HDMI port
>  - SD card slot
>  - some memory
>  - PS/2 keyboard
>  - USB and Enthernet, although I have almost no idea about how these two=
=20
> work
>=20
>=20
> I found these boards:
>=20
> > Basys(tm)2 - Xilinx Spartan-3E, 8-bit VGA, PS/2 - 69$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > Basys(tm)3 - Xilinx Artix-7, 12-bit VGA, USB host for kb/mice, flash -
> 79$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > miniSpartan6+ - Spartan 6 LX 9, HDMI, serial flash, microSD - 75$
> http://www.scarabhardware.com/product/minisp6/
> > ZYBO Zynq(tm)-7000 - Xilinx Z-7010, Cortex-A9, flash, memory, SD, USB,
> gigabit=20
> Ethernet, HDMI, 16-bit VGA - 125$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > Altera DE0 Board - Altera Cyclone III 3C16, 4-BIT VGA, SD, serial port,
> PS/2,=20
> flash - 81$
> http://www.terasic.com.tw/cgi-bin/page/archive.pl?...
> > Altera DE0-CV Board - Altera Cyclone V 5CEBA4F23C7N, 4-bit VGA, microSD=
,
> PS/2 -=20
> 99$
> > Altera DE1 Board - Altera Cyclone II 2C20, 4-bit R-2R per channel VGA,
> PS/2, SD,=20
> flash - 127$
>=20
> here's where I can't decide. Again, cost is important for me, but I also=
=20
> know that Digilent and Terasic are Some Names.
>=20
> What would you choose? Do you have any of your own recommendations?
> Please help, I'm honestly an absolute nooob here.
>=20
>=20
> ---------------------------------------
> Posted through http://www.FPGARelated.com

FrewCen,

You didn't specify your budget and I noticed that for the Digilent prices, =
you showed the 'Acedemic' price...

I recently chose to get a ZYBO from Digilent and am happy with my decision.=
 In my opinion, SoC based development kits are the way to go because they p=
rovide the most learning opportunity. It is also my opinion that industry i=
s in need of SoC engineers, so the learning will be relevant.

With the ZYBO, you can learn FPGA design as well as embedded uC design. You=
 can pretty well skip all the ARM related development if you want, and focu=
s on just FPGA stuff, but having the ARM cores there makes for a very versa=
tile learning opportunity.

If you are interested in Embedded Linux, I recommend you get at least 512MB=
 DDR. The Basys 3 would make a poor embedded Linux system IMO, but it can a=
nd has been done. I prefer to not limit myself at the outset and get more h=
ardware than I think I'll need. It's not that expensive...

Along with the dev board, a decent book will be very helpful. I recomment A=
dvanced FPGA Design by Steve Kilts.

Good luck on your Journey,
BradW

Article: 157852
Subject: Re: Choosing the right FPGA board
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 20 Apr 2015 23:33:10 +0100 (BST)
Links: << >>  << T >>  << A >>
FrewCen <105208@fpgarelated> wrote:
> I found these boards:
> 
> > Basysâ?¢2 - Xilinx Spartan-3E, 8-bit VGA, PS/2 - 69$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > Basysâ?¢3 - Xilinx Artix-7, 12-bit VGA, USB host for kb/mice, flash -
> 79$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > miniSpartan6+ - Spartan 6 LX 9, HDMI, serial flash, microSD - 75$
> http://www.scarabhardware.com/product/minisp6/
> > ZYBO Zynqâ?¢-7000 - Xilinx Z-7010, Cortex-A9, flash, memory, SD, USB,
> gigabit 
> Ethernet, HDMI, 16-bit VGA - 125$
> http://www.digilentinc.com/Products/Detail.cfm?Nav...
> > Altera DE0 Board - Altera Cyclone III 3C16, 4-BIT VGA, SD, serial port,
> PS/2, 
> flash - 81$
> http://www.terasic.com.tw/cgi-bin/page/archive.pl?...
> > Altera DE0-CV Board - Altera Cyclone V 5CEBA4F23C7N, 4-bit VGA, microSD,
> PS/2 - 
> 99$
> > Altera DE1 Board - Altera Cyclone II 2C20, 4-bit R-2R per channel VGA,
> PS/2, SD, 
> flash - 127$
> 
> here's where I can't decide. Again, cost is important for me, but I also 
> know that Digilent and Terasic are Some Names.

You should understand that Xilinx v Altera is a bit like PC v Mac (not
necessarily that way round) - you aren't just choosing a part vendor, you're
choosing a whole ecosystem and toolchain which will have a big impact on the
experience for have.

I'd avoid the older parts (Cyclone II and III) since those may not be
supported in future versions of the Altera toolchain.  The same might apply
to the Spartan 3E, though I'm not as familiar with that.

One hidden caveat is that the later Altera devices (eg Cyclone V) take much
more RAM in your PC for synthesis than older ones (eg 1.5 v 6 GiB).  So
depends what kind of a PC you're going to use.

Be aware that the Zynq (and the DE1-SoC) have an ARM onboard, and some of
the peripherals are on the ARM side rather than the FPGA side.  You can,
however, ignore the ARM side if you like and just use the FPGA peripherals.

Digilent and Terasic are both suppliers of education boards, which explains
why the costs of those boards are lower than other vendors.  Their
popularity also means there are more educational resources for using their
boards.

Theo

Article: 157853
Subject: Re: Choosing the right FPGA board
From: thomas.entner99@gmail.com
Date: Mon, 20 Apr 2015 16:51:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
I would second Theo's comments and add that you can download the design sof=
tware of both X and A and play around with it to see what you like more. Th=
e difference in the design software is much bigger then in the devices.

I also would use new generation devices, either with Arm (Zynq, Cyclone V S=
oc) or without (Artix 7, Cyclone V). The Arm devices are much more complex =
to start with, on the other hand they might be more interesting for you wit=
h your classic software background. You can use Linux on the Arm and off-lo=
ad some tasks to the FPGA part. If you want to use Ethernet and/or USB, I w=
ould recommend this approach.

Thomas

Article: 157854
Subject: Re: Choosing the right FPGA board
From: jonesandy@comcast.net
Date: Mon, 20 Apr 2015 18:23:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
A couple you didn't mention from Terasic that warrant consideration:
DE1-SoC Board ($175)
Cyclone V GX Starter Kit ($179)

The latter does not have an arm cpu, but does have an arduino header, for further expansion using aruduino shields.

Andy

Article: 157855
Subject: Re: Choosing the right FPGA board
From: HT-Lab <hans64@htminuslab.com>
Date: Tue, 21 Apr 2015 11:37:47 +0100
Links: << >>  << T >>  << A >>
On 21/04/2015 02:23, jonesandy@comcast.net wrote:
..
> The latter does not have an arm cpu, but does have an arduino header, for further expansion using aruduino shields.
>
> Andy
>

Andy made a good point, don't be too concerned if your favourite board 
is missing an interface. Using Arduino or my favourite SPI (easy to 
implement) you can add a whole range of interfaces to your board 
(SD/Ethernet/VGA/etc). Have a look at various breakout boards offered by 
Sparkfun and others.
So I would recommend a simple board with a big FPGA and some external 
SRAM, then build up your knowledge by adding various interfaces and 
softcores.

Apart from the excellent boards from Digilent and Terasic I would also 
suggest you check out eBay and Enterpoint,

Good luck,
Hans
www.ht-lab.com

Article: 157856
Subject: Re: Choosing the right FPGA board
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 21 Apr 2015 13:54:57 +0100 (BST)
Links: << >>  << T >>  << A >>
HT-Lab <hans64@htminuslab.com> wrote:
> Andy made a good point, don't be too concerned if your favourite board 
> is missing an interface. Using Arduino or my favourite SPI (easy to 
> implement) you can add a whole range of interfaces to your board 
> (SD/Ethernet/VGA/etc). Have a look at various breakout boards offered by 
> Sparkfun and others.

It depends what you want to do.  Lots of Arduino interfaces are really
limited because they're designed to be chained to a feeble ATmega.  So you
can divide into those interfaces that are naturally slow, like I2C, keypad,
accelerometer, etc, and those where high bandwidth is important
(SD/Ethernet/VGA/etc).  The naturally slow interfaces won't lose anything
using an Arduino interface, while the high bandwidth interfaces /can/ be
driven via an Arduino shield, but will lose a lot of performance while doing
so.

OTOH, doing something like USB virtually demands a CPU - you won't be able
to usefully drive it from an FPGA alone (without soft-CPU inside). 
So having a CPU do that makes sense (either a microcontroller or on-FPGA
ARM - using it on a soft-CPU like NIOS-II or Microblaze is probably too much
hassle).

> So I would recommend a simple board with a big FPGA and some external 
> SRAM, then build up your knowledge by adding various interfaces and 
> softcores.
> 
> Apart from the excellent boards from Digilent and Terasic I would also 
> suggest you check out eBay and Enterpoint,

What do you suggest looking for on eBay?

As has already been said, choosing a board is more than just the feature
list -- the example projects and tutorials make a big difference.

Theo

Article: 157857
Subject: Re: Choosing the right FPGA board
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Tue, 21 Apr 2015 16:49:59 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Mon, 20 Apr 2015 23:33:10 +0100, Theo Markettos wrote:

> FrewCen <105208@fpgarelated> wrote:
>> I found these boards:
>> 
>> > Basysâ?¢2 - Xilinx Spartan-3E, 8-bit VGA, PS/2 - 69$
>> http://www.digilentinc.com/Products/Detail.cfm?Nav...
>> > Basysâ?¢3 - Xilinx Artix-7, 12-bit VGA, USB host for kb/mice, flash -
>> 79$
>> http://www.digilentinc.com/Products/Detail.cfm?Nav...
>> > miniSpartan6+ - Spartan 6 LX 9, HDMI, serial flash, microSD - 75$
>> http://www.scarabhardware.com/product/minisp6/
>> > ZYBO Zynqâ?¢-7000 - Xilinx Z-7010, Cortex-A9, flash, memory, SD, USB,
>> gigabit Ethernet, HDMI, 16-bit VGA - 125$
>> http://www.digilentinc.com/Products/Detail.cfm?Nav...
>> > Altera DE0 Board - Altera Cyclone III 3C16, 4-BIT VGA, SD, serial
>> > port,
>> PS/2,
>> flash - 81$
>> http://www.terasic.com.tw/cgi-bin/page/archive.pl?...
>> > Altera DE0-CV Board - Altera Cyclone V 5CEBA4F23C7N, 4-bit VGA,
>> > microSD,
>> PS/2 -
>> 99$
>> > Altera DE1 Board - Altera Cyclone II 2C20, 4-bit R-2R per channel
>> > VGA,
>> PS/2, SD,
>> flash - 127$
>> 
> 
> I'd avoid the older parts (Cyclone II and III) since those may not be
> supported in future versions of the Altera toolchain.  The same might
> apply to the Spartan 3E, though I'm not as familiar with that.
> 

Theo, I think you've underestimated how aggressively both X and A have 
been pruning their old silicon from the latest tools.  Xilinx Vivado has 
no support for anything other than 7 series parts, ISE has been moved to 
"sustaining".  Altera Quartus II, likewise, has dropped support for even 
the Cyclone III from the 14.x branch.

So, of the OP's list, the Artix-7, Z-7010, and Cyclone V still have the 
full support of their vendors.  The rest already have the gold pen for 
all they've done, the cardboard box on their desks, and security standing 
over their shoulders.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 157858
Subject: Re: FPGA / DSP - Urgent need in Orange County, CA
From: bobpainter <bob@turnkeylogicinc.com>
Date: Tue, 21 Apr 2015 18:35:48 -0500
Links: << >>  << T >>  << A >>
Hi Robert,

I am interested in your posting looking for DSP/FPGA Engineer.  I am finishing up work on a high reliability ASIC design for Satellite use in Denver and am available in a few weeks.

What city is this located in?

Thanks,
Bob Painter



Article: 157859
Subject: Re: Choosing the right FPGA board
From: Mike Field <mikefield1969@gmail.com>
Date: Tue, 21 Apr 2015 18:53:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,


> Basys(tm)2 - Xilinx Spartan-3E, 8-bit VGA, PS/2 - 69$=20

Don't do it - ver old, very small, on-board XTAL is junk.

> Basys(tm)3 - Xilinx Artix-7, 12-bit VGA, USB host for kb/mice, flash -=20
79$=20
Nice board, I have one - great for FPGA tinkering, not so good for embedded=
 MCU as it has no off-FPGA memory.

> miniSpartan6+ - Spartan 6 LX 9, HDMI, serial flash, microSD - 75$=20

Nice board, I have one too - HDMI In and Out, which is rather unique at the=
 price point. LX9 is quite small, and the SDRAM RAM bandwidth is quite low =
for playing with video streams. I don't think that you can use the on-board=
 memory with EDK projects, so it isn't a good platform for embedded develop=
ment. You will need a soldering iron to add any other peripherals other tha=
n the basic on board set.

> ZYBO Zynq(tm)-7000 - Xilinx Z-7010, Cortex-A9, flash, memory, SD, USB,=20
gigabit=20
Ethernet, HDMI, 16-bit VGA - 125$=20

I've got it's big brother, the Zedboard and it is great. I quite like the l=
ook of the Zybo and would consider it if I didn't have a Zedboard.=20

> Altera DE0 Board - Altera Cyclone III 3C16, 4-BIT VGA, SD, serial port,=
=20
PS/2,=20
flash - 81$=20

Have not used, but I assume that it is only still available to be compatibl=
e with existing coursework

http://www.terasic.com.tw/cgi-bin/page/archive.pl?...=20
> Altera DE0-CV Board - Altera Cyclone V 5CEBA4F23C7N, 4-bit VGA, microSD,=
=20
PS/2 -=20
99$=20
Newer, bigger FPGA, with much more memory than the old DE0. I would recomme=
nd it as the Altera board for learning FPGA design on.

> Altera DE1 Board - Altera Cyclone II 2C20, 4-bit R-2R per channel VGA,=20
PS/2, SD,=20
flash - 127$=20

Very old FPGA, but has lots of goodies to play with (e.g. SDRAM+FLASH+SRAM,=
 audio codec...). I also assume that it is only still available to be compa=
tible with existing reference material.

If you are interested in embedded Linux, then also look at the DE1-SoC Boar=
d. I've go one on my desk at work at the moment and it is quite nice. It is=
 an approximate match for the Zybo.

If I was spending my own money, I'ld go for a Zybo (if interested in Embedd=
ed Linux) or a Basys3 (if primarily interested in FPGA logic design). But t=
hen I guess I am a bit of a Xilinx fanboy as that is what I learnt on.

Mike

Article: 157860
Subject: Xilinx Aurora link splitter
From: Hendrik van der Heijden <hvdh@gmx.de>
Date: Thu, 23 Apr 2015 09:15:39 +0200
Links: << >>  << T >>  << A >>
Hi,

I'm a software guy and now that I have a hardware problem,
I hope to find some good advice here.

There are two devices A and B connected using Aurora link
(single lane, full duplex) over SFP + optical LC cables.
Data transfer is mostly A->B.

Now I want to tap into this link transparently, so that device
C gets a copy of (at least) everything that A sends.
C is fast enough to receive, so it doesn't need to do
flow control with A.

I read that Aurora cores are configured for individual use.
If there's no solution on a lower level, I have access to
the actual Aurora core source used in devices A and B.

Is there a device available which can split an Aurora link
resp. duplicate it to a mirror port? Is there some dev board
which can be made into what I need without too much work?
I only need one such device.


Kind regards,


Hendrik vdH

Article: 157861
Subject: Re: Xilinx Aurora link splitter
From: GaborSzakacs <gabor@alacron.com>
Date: Thu, 23 Apr 2015 08:42:47 -0400
Links: << >>  << T >>  << A >>
Hendrik van der Heijden wrote:
> Hi,
> 
> I'm a software guy and now that I have a hardware problem,
> I hope to find some good advice here.
> 
> There are two devices A and B connected using Aurora link
> (single lane, full duplex) over SFP + optical LC cables.
> Data transfer is mostly A->B.
> 
> Now I want to tap into this link transparently, so that device
> C gets a copy of (at least) everything that A sends.
> C is fast enough to receive, so it doesn't need to do
> flow control with A.
> 
> I read that Aurora cores are configured for individual use.
> If there's no solution on a lower level, I have access to
> the actual Aurora core source used in devices A and B.
> 
> Is there a device available which can split an Aurora link
> resp. duplicate it to a mirror port? Is there some dev board
> which can be made into what I need without too much work?
> I only need one such device.
> 
> 
> Kind regards,
> 
> 
> Hendrik vdH

I'm not sure I understand everything, but it sounds like you
could use any board that has 3 SFP ports and an FPGA capable
of supporting 3 Aurora ports.  That would be the case if
device C has an Aurora receiver.  If device C doesn't, or
if this is just a conceptual thing for debug, you could
get away with 2 SFP ports and whatever interface you need to
get the data out some other way, possibly even PCIe if the
interposing board plugs into a "debug" PC to listen in to
the link.

You say that C doesn't need flow control, but if B uses flow
control, you need to make sure that the latency added by
the interface doesn't create problems with that flow control,
or else you would need logic in the interface to handle the
flow control, possibly with some extra buffering.

You also didn't mention the bit rate.  If it's not too high
there might also be the possibility of redriving the signal
without having SERDES in between.  That would add very little
latency to the link.

An intermediate latency solution would be to use a SERDES-based
re-driver using a recovered clock.  Or you could use an FPGA
without Aurora cores to retransmit with fairly low latency if
you have access to the reference clock from boards A and B.

-- 
Gabor

Article: 157862
Subject: Re: Xilinx Aurora link splitter
From: Hendrik van der Heijden <hvdh@gmx.de>
Date: Thu, 23 Apr 2015 22:57:32 +0200
Links: << >>  << T >>  << A >>
Am 23.04.2015 um 14:42 schrieb GaborSzakacs:
>> I'm a software guy and now that I have a hardware problem,
>> I hope to find some good advice here.
>>
>> There are two devices A and B connected using Aurora link
>> (single lane, full duplex) over SFP + optical LC cables.
>> Data transfer is mostly A->B.
>>
>> Now I want to tap into this link transparently, so that device
>> C gets a copy of (at least) everything that A sends.
> 
> I'm not sure I understand everything, but it sounds like you
> could use any board that has 3 SFP ports and an FPGA capable
> of supporting 3 Aurora ports.

Right, can you recommend some specific suitable board?

> That would be the case if device C has an Aurora receiver.
> If device C doesn't, or if this is just a conceptual thing
> for debug, you could
> get away with 2 SFP ports and whatever interface you need to
> get the data out some other way, possibly even PCIe if the
> interposing board plugs into a "debug" PC to listen in to
> the link.

Currently, my device C is a PCIe card with a single SFP.
Its FPGA contains an Aurora core plus some logic to make received
data available to the PC.

Like you, I see two options:

1)
Assuming I can get the FPGA source code for my PCIe card and get
a version with two SFPs, how much effort would it be to have the
Aurora link pass-through between both SFPs bidirectionally?

Can I just connect Aurora port A's RX lanes to port B's TX lanes
and vice versa (in FPGA logic) or is there more to it?

SFP A RX -------> in  AuroraCoreA RX -->--+ --> Decoder to PC RAM
SFP A TX <------- out             TX <--  |
                                       |  |
SPF B RX -------> in  AuroraCoreB RX -->  |
SFP B TX <------- out             TX <----+


> If it's not too high there might also be the possibility of
> redriving the signal without having SERDES in between.
> That would add very little latency to the link.
> An intermediate latency solution would be to use a SERDES-based
> re-driver using a recovered clock.

I have too little knowledge here to tell whether these ideas would work.
Can I directly connect the two SFP's RX and TX? On the "raw" pins or
behind the SERDES ("MGT"?)?
Would the AuroraCore output received data or stay in link down
state because no one reacts to its output?

SFP A RX -----+--> in  AuroraCore RX --> Decoder to PC RAM
SFP A TX <-+  |    out            TX <-- (unused)
           |  |
           |  |
SPF B RX --+  |
SFP B TX <----+



2)
Get a 3xSFP FPGA board, put Aurora cores in there and hook them up:
  Port A RX -> Port B TX + Port C TX
  Port B TX <- Port B RX

I was hoping I could buy something like this directly, instead of
having to develop it myself (or paying someone to do so). If if can't
buy it directly, the first option seems to be the better one.

> You say that C doesn't need flow control, but if B uses flow
> control, you need to make sure that the latency added [..]

Latency shouldn't be an issue. A and B should work fine
with up to 1ms added latency.

> You also didn't mention the bit rate. 

The Aurora link is 2GBit/s, payload data rate is maybe half that.

> Or you could use an FPGA
> without Aurora cores to retransmit with fairly low latency if
> you have access to the reference clock from boards A and B.

I cannot interface boards A and B directly, only the Aurora link
in-between.

Thanks for your ideas so far,


Hendrik vdH

Article: 157863
Subject: Re: Directly connect two XAUI ports inside FPGA
From: "Tomas D." <mailsoc@gmial.com>
Date: Thu, 23 Apr 2015 23:01:20 +0100
Links: << >>  << T >>  << A >>

"Guenther Wenninger" <g!!rw@bitschubbser.org> wrote in message 
news:slrnmja7fp.cf4.g!!rw@masterbase.bitschubbser.org...
> Hi all,
>
> to implement something like a passthru mode, we want to directly
> connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.
>
> Therefor we did instantiate two XAUI-cores and connected txd/txc from
> one core with the rxd/rxc from the other core and vice versa.
> Because both cores use a different refclk we simply added two
> synchronizer FFs in between.
>
> In our test-design this works. But when added to the full design
> this code fails (the data after the synchronizer FFs seems scrambled).
> Is it at all possible to directly connect two XAUI cores?
> Is it possible to connect two blocks with the same clock frequency
> but - probably - different clock phase just using 2xFFs?

WHat about a DCFIFO and do transaction within packet boundary? E.g. transfer 
to different clock domain (read fifo) when a full packet is in?

Regards
Tomas D. 



Article: 157864
Subject: Re: Does each core of 8-core Intel processor has an independent floating
From: Hendrik van der Heijden <hvdh@gmx.de>
Date: Fri, 24 Apr 2015 08:26:05 +0200
Links: << >>  << T >>  << A >>
Am 05.04.2015 um 15:43 schrieb Weng Tianxiang:
> Does each core of 8-core Intel processor has an independent floating X87 unit? 

Yes. All cores are identical, each has independent resources to do x87.

> 5.2 X87 FPU INSTRUCTIONS
> The x87 FPU instructions are executed by the processor's x87 FPU. 
> These instructions operate on floating-point, integer,[..]
> 
> These instructions are divided into the following subgroups:
> data transfer, load constants, and FPU control instructions.
> 
> From above text I have a feeling that all 8 execution cores share the same X87 FPU unit.

No that's wrong. Instruction documentation describes the core itself (a single core).
Depending on the CPU model, you get multiple instances of the described core.

> Is there anyone who has real experiences with X87 FPU unit?

x87 is legacy nowadays. It is (mostly?) superseded by SSE and AVX instructions,
which have better performance and also allow for SIMD parallelism.


Hendrik vdH


Article: 157865
Subject: Re: Directly connect two XAUI ports inside FPGA
From: SysTom <mr.thomas.c.jones@gmail.com>
Date: Mon, 27 Apr 2015 21:10:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
In the full design did the two XAUI ports use precisely the physical ports and internal routing?

Article: 157866
Subject: Re: Registered signal synchronizer [was: Directly connect two XAUI
From: Guenther Wenninger <g!!rw@bitschubbser.org>
Date: Tue, 28 Apr 2015 09:39:24 +0200
Links: << >>  << T >>  << A >>
Hi all,

thank you for the input. I also had the idea to use
a FIFO, but this needs some non-trivial glue-logic
as we want to dynamically change the connection mode
from "direct-connect" to "internal-data-to-xaui".

What I still would like to know: If it is "okay" to
synchronize two registered std_logic_vector's (same clock
frequency, different phase) using a 2-FF synchronizer.

What seems to have helped in the end was the AR from
Xilinx: http://www.xilinx.com/support/answers/39492.html

Thanks again and kind regards,
/gw

Guenther Wenninger <g!!rw@bitschubbser.org> schrieb:
> Hi all,
>
> to implement something like a passthru mode, we want to directly
> connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.
>
> Therefor we did instantiate two XAUI-cores and connected txd/txc from
> one core with the rxd/rxc from the other core and vice versa.
> Because both cores use a different refclk we simply added two
> synchronizer FFs in between.
>
> In our test-design this works. But when added to the full design
> this code fails (the data after the synchronizer FFs seems scrambled).
> Is it at all possible to directly connect two XAUI cores?
> Is it possible to connect two blocks with the same clock frequency
> but - probably - different clock phase just using 2xFFs?
>
> Kind regards,
> /gw
>


-- 
For reply: Remove the additional chars from the local part.

Article: 157867
Subject: Interested in VHDL and FPGA Development?
From: jjchristman13@gmail.com
Date: Tue, 28 Apr 2015 17:10:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
Check out my course! Lifetime and Unlimited Access!
https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=FIVERR15

Article: 157868
Subject: Re: Choosing the right FPGA board
From: "FrewCen" <105208@FPGARelated>
Date: Wed, 29 Apr 2015 12:50:25 -0500
Links: << >>  << T >>  << A >>
THANK YOU ALL for this discussion, you helped a lot.
I have chosen Altera Cyclone IV on a different (Arduino-like) board, since
that comes easier for me, but if I ever come to a larger chunk of money
again, I'll go for  the processor directly on-board.

Thank you all again. 
---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157869
Subject: Spartan-3 stater kit
From: jmariano <jmariano65@gmail.com>
Date: Fri, 1 May 2015 11:24:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear all,

I'm really not a specialist in FPGA :-)

For several years now I have a microbalze SoC running on a Digilent Spartan=
-3 Starter Kit Board with a XC3S200 FPGA. The board acts as the digital con=
troller of a NMR spectrometer. Since I need more uC memory to update my cod=
e (only have 16 K in this implementation) I purchase from Diligent another =
S3SKB with a XC3S1000FT256-4 FPGA that was been sitting at my desk for four=
 years now.=20

I finally decided to migrate the design from my old board to the new one. T=
o make sure I knew what to do, I started with one of those MB tutorials fou=
nd on the web, compile it and download the bit file to the old board using =
impact. The application run as expected. I then went back to XPS and change=
d the device size on system->project option, recompiled the design, and aft=
er downloading, nothing happens. Actually, all leds on the board lit up and=
 stay that way.

So, I guess my questions are:
1 - The new board came with a design loaded on the platform PROM. Do I need=
 to change anything to force MB to load from BRAM?
2 - Besides changing the device size on XPS, do I need to change anything e=
lse on my project.

Any other ideas?

I'm using XPS 7.1 (it works for me !)

Regards
jmariano

Article: 157870
Subject: Re: Spartan-3 starter kit
From: GaborSzakacs <gabor@alacron.com>
Date: Fri, 01 May 2015 15:03:35 -0400
Links: << >>  << T >>  << A >>
jmariano wrote:
> Dear all,
> 
> I'm really not a specialist in FPGA :-)
> 
> For several years now I have a microbalze SoC running on a Digilent Spartan-3 Starter Kit Board with a XC3S200 FPGA. The board acts as the digital controller of a NMR spectrometer. Since I need more uC memory to update my code (only have 16 K in this implementation) I purchase from Diligent another S3SKB with a XC3S1000FT256-4 FPGA that was been sitting at my desk for four years now. 
> 
> I finally decided to migrate the design from my old board to the new one. To make sure I knew what to do, I started with one of those MB tutorials found on the web, compile it and download the bit file to the old board using impact. The application run as expected. I then went back to XPS and changed the device size on system->project option, recompiled the design, and after downloading, nothing happens. Actually, all leds on the board lit up and stay that way.
> 
> So, I guess my questions are:
> 1 - The new board came with a design loaded on the platform PROM. Do I need to change anything to force MB to load from BRAM?
> 2 - Besides changing the device size on XPS, do I need to change anything else on my project.
> 
> Any other ideas?
> 
> I'm using XPS 7.1 (it works for me !)
> 
> Regards
> jmariano

Is the XC3S1000 really the exact same board with just a larger FPGA chip
mounted?  If not you'd need to make sure that the UCF file matches the
new board connections.

-- 
Gabor

Article: 157871
Subject: Re: Spartan-3 starter kit
From: jmariano <jmariano65@gmail.com>
Date: Fri, 1 May 2015 14:57:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Gabor, thanks for the help. Digilent's documentation is spase but the board revision is the same and the manual is the same for both FPGA, so I assume ucf to be the same.

Article: 157872
Subject: Re: Spartan-3 stater kit
From: BobH <wanderingmetalhead.nospam.please@yahoo.com>
Date: Fri, 01 May 2015 16:40:39 -0700
Links: << >>  << T >>  << A >>
Depending on how the clock generation is handled on the board, you may 
have to configure an external PLL to get the desired clock frequency to 
the FPGA. The PLL got configured with the vendors GUI. The old Opal 
Kelly Spartan 3 boards that I am familiar with required this. There may 
also be some jumpers to set for stuff like auto-configure.

Good Luck,
Bob

On 5/1/2015 11:24 AM, jmariano wrote:
> Dear all,
> So, I guess my questions are:
> 1 - The new board came with a design loaded on the platform PROM. Do I need
> to change anything to force MB to load from BRAM?
> 2 - Besides changing the device size on XPS, do I need to change anything
> else on my project.
>
> Any other ideas?
>
> I'm using XPS 7.1 (it works for me !)
>
> Regards
> jmariano
>


Article: 157873
Subject: Re: Spartan-3 stater kit
From: Brian Davis <brimdavis@aol.com>
Date: Sat, 2 May 2015 06:25:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Friday, May 1, 2015 at 2:24:40 PM UTC-4, jmariano wrote:
>
> after downloading, nothing happens. 
> Actually, all leds on the board lit up and stay that way.
> 
I've seen this before, as a first step try removing the M0 jumper.

See this post/thread for more info and other debugging suggestions:
https://groups.google.com/d/msg/comp.arch.fpga/l1zQYEyTmV8/qW-SIiYrFmMJ


-Brian

Article: 157874
Subject: Re: Spartan-3 stater kit
From: jmariano <jmariano65@gmail.com>
Date: Sat, 2 May 2015 07:23:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Saturday, May 2, 2015 at 2:25:55 PM UTC+1, Brian Davis wrote:
> On Friday, May 1, 2015 at 2:24:40 PM UTC-4, jmariano wrote:
> >
> > after downloading, nothing happens. 
> > Actually, all leds on the board lit up and stay that way.
> > 
> I've seen this before, as a first step try removing the M0 jumper.
> 
> See this post/thread for more info and other debugging suggestions:
> https://groups.google.com/d/msg/comp.arch.fpga/l1zQYEyTmV8/qW-SIiYrFmMJ
> 
> 
> -Brian

Hi,

Thanks for the help.

BobH, the S3SKB has a on board 50 MHz clock connected to the FPGA. You can replace it by other clock generator but that's it. Of course you can use DCM inside the FPGA to juggle with your clock, but not from the outside.

Brian, I'll try that when I'm back to work next Monday.

jmariano



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