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Messages from 16150

Article: 16150
Subject: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 06 May 1999 12:08:48 -0400
Links: << >>  << T >>  << A >>
While I don't like the idea of socketing an SRAM based FPGA, there are
adapters out there that will let you do it.  I've had customers use
adapters from emulation technology and ironwood.  A current customer is
also using a bga to pga adapter, but I'm not sure who makes it.

Stuart Clubb wrote:

> On Thu, 06 May 1999 07:55:18 +0200, Emil Blaschek
> <emil.blaschek@siemens.at> wrote:
>
> >If you want to use the full power of VHDL,
> > better use Design-Compiler to generate a primitive Netlist in VHDL,
> > and export this to MAX2 for fitting.
>
> ROTFL !!!!
>
> Stuart
> For Email remove "NOSPAM" from the address



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16151
Subject: Re: Bugs in place and route s/w....XLINX???
From: mcgett@feynman.xsj.xilinx.com (Ed Mcgettigan)
Date: 6 May 1999 09:12:43 -0700
Links: << >>  << T >>  << A >>
In article <7gqs18$92r$1@autumn.news.rcn.net>, jok <jok@erols.com> wrote:
>Is there a source which might have a caveat list regarding bugs with latest
>place and route software for XLINX?  I have heard of one user seeing problems 
>with two nodes driving the same net after place and route.  Maybe the list 
>would have work-arounds.  

You should try out http://support.xilinx.com the answer database is quite
comphrensive and includes suggested workarounds when applicable.  The 
scenario that you describe should not happen and is check at many points
in the software by DRC rules.  The only exception to this would be tri-state
buffers, when you want to have multiple-sources for the same net.

>I can't imagine doing hand routing of CLBs anymore, or is that in fashion
>again?
>

There are very few people today that do this.

Ed
Article: 16152
Subject: Fpga gates, PLD gates ASIC gates: Help us please.
From: hhk@wxs.nl (hhk)
Date: Thu, 06 May 1999 17:00:23 GMT
Links: << >>  << T >>  << A >>
Hello,

We are two gratuade students in Holland. Currently we are examining
the possibillity's of the Actel 54SX 16 (Antifuse) FPGA.
During this examination we compare this component with an Altera MAX
7000 CPLD (EEPROM).

At this point we want to compare the capacity of both components....
Evry one we talked to adviced us to compare the capacity by means of
gates.

But here is the problem. The Actel family's capacity is specified in
(usable) PLD gates and the Altera probably specified in ASIC gates.

The big problem is: What are PLD gates, ASIC gates an what are FPGA
gates. And above all: What is the DIFFERENCE between these types of
gates.

Please help us, reply's can also be directed to dg351@signaal.nl.

Yours cincerely,

H.H. Kruizinga
Article: 16153
Subject: Re: Bugs in place and route s/w....XLINX???
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Thu, 06 May 1999 10:08:45 -0700
Links: << >>  << T >>  << A >>
Check the Xilinx Answers database. The search engine is pretty much
useless unless you know exactly what you're looking for, so I just
check for new entries every now and then. It contains about 3370
items at present, newest at the end. It would be nice if the records
had a date field and it wasn't necessary to load the whole thing
to check for updates. Apparently you can request automatic email
notification of updates, if this appeals to you.

http://www.xilinx.com/techdocs/techdocs.htm

-- 
Tom Burgess


jok wrote: <snipped>
> 
> Is there a source which might have a caveat list regarding bugs with latest
> place and
> route software for XLINX?
Article: 16154
Subject: DSP in FPGA
From: "Cemal Coemert (TIP)" <coemert@fokus.gmd.de>
Date: Thu, 06 May 1999 19:11:01 +0200
Links: << >>  << T >>  << A >>
Hi everyone,

I would like to implement some DSP functions in a FPGA ( with VHDL ).
Where can I get some examples?

Have a nice day
Cemal


Article: 16155
Subject: Re: Configuring Xilinx FPGAs
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 6 May 1999 17:29:17 GMT
Links: << >>  << T >>  << A >>
How to make daisychain bit streams, by Philip Freidin.
Derived from a posting of mine, 07/10/1997

Anyway, here is the solution.

1) check that the total bitstream length you are going for is less
   than the maximum length (which is about 16 million bits). Your
   basic bitstream for a 4010 is 178096, so no big probs here.
   I dont remember what you said the second device was, but lets
   assume it is also a 4010

2)  Now go create RAW bit stream files for both the XC4010 devices.
    The makebits command for the Xact Step SW is "makebits -b filename.lca"
    The makebits command for M1 is "bitgen -b filename.ncd"

3)  Now take each of the files created, and edit them in a text editor.
    Remove the text from the beginning of each file, and also the header
    line: (make sure you have an editor that can handle long lines)

The M1 stuff looks like this: (delete 8 lines, including the first
data line.)

Xilinx ASCII Bitstream
Created by Bitstream M1.2.6
Design name:    Test01.ncd
Architecture:   xc4036EX
Part:           4036exdip16
Date:           Fri Feb 28 23:16:48 1997
Bits:           832523
1111111100100000001111001000100110011111
010101111111111011111110101111111010111111101111010101  etc ...
011111111111110111111111011111111101111111110111111111  etc ...
011110111101101101110111111111111111111111111111110110  etc ...
011111111101111111111011111111101111111110111111111011  etc ...


4) Now join all the files together, in the same order as the daisy chain.
   The first section of combined file is the data for the first chip
   in the chain. The last section is for the last chip.
   Be real careful that all you have in the file is the data bits (minus
   the headers that you deleted).

5) count how many bits there are. The answer should be real close
   to 2 * 178096. (file length cant be used as it includes CR and LF
   characters. We only want the total of '0' and '1' characters)

6) Now comes the best bit (a pun) of all. You need to build a new header.
   Start with one of the headers that you saved.
   The bits are:
        P   Preamble
        S   Start Code
        L   Length Count
        T   Tail Pad

   1111111100100000001111001000100110011111
   PPPPPPPPSSSSLLLLLLLLLLLLLLLLLLLLLLLLTTTT

Take the length count that you calculated in step 5, and add 40 to it
(which is the length of the header) then add 1 for each chip in daisy
chain (2 in your case). The sum might be 356234 or maybe a slightly
higher (but not more than 50 higher). Convert to a 24 bit binary number:
000001010110111110001010   (356234 = 056F8A hex)

Insert this number in-place of the 'L' field of your saved header, and then
with your bright new combined header, put it at the beginning of your
combined bitstream file. it will look something like this now:

1111111100100000010101101111100010101111
010101111111111011111110101111111010111111101111010101  etc ...
011111111111110111111111011111111101111111110111111111  etc ...
011110111101101101110111111111111111111111111111110110  etc ...
011111111101111111111011111111101111111110111111111011  etc ...

7) go to the end of the file and add at least 2 (because there are 2 chips)
   extra '1' bits. I would probably add 20.

8) The file is now ready to go into whatever you are going to store
   the bitstream in, i.e. PROM, RAM, Floppy, paper tape, whatever.
   During configuration, the data is sent to the first chip starting
   at the left of the first line, and just sending the data in the
   same order that it is in the file. If you need to convert the data
   into byte wide data, and then serialize it during download, REMEMBER
   to maintain the order.

9) When downloading the bitstream, I usually clock the CCLK an extra
    10 to 20 times beyond the length of the bitstream, so I might add
    additional pad '1' bits at the end of the stream, but NOT change
    the length count at the beginning.

Have fun,

Philip Freidin

In article <3729B79C@mail.lumino.de> Rolf Aengenendt <RAENGEN@LUMINO.de> writes:
>
>Thanks for the information, but we definitely would like to know how the 
>combined bitstream is made up.
>
>One cause is that we want to have the uP software that performs the loading 
>of the FPGAs extract the length information from the bitstream(s) with. The 
>other, more important, cause is, that the two FPGA programs are created with 
>different software tools ("XDE" and "Foundation M1.5") and we have no idea 
>how to combine the output of those to a single bitstream.
>Rolf Aengenendt, Lumino GmbH, Krefeld, Germany
>fon: +49-2151-8196-76 fax: +49-2151-8196-6676
>mailto:raengen@lumino.de
>internet: http://www.lumino.de

Article: 16156
Subject: Re: Help me: What is FPGA?
From: hhk@wxs.nl (hhk)
Date: Thu, 06 May 1999 17:53:13 GMT
Links: << >>  << T >>  << A >>
On Fri, 30 Apr 1999 19:18:40 -0700, "Iwan Santoso Oei"
<iwanoei@mindspring.com> wrote:

>Hi, i am new guys in this room. Because i will make a thesis in FPGA topic,
>if you don't mind, tell me about FPGA is.
>1. What is FPGA? Is the function of FPGA can do the same like
>Microcontrolller?
>2. I confuse if FPGA programmable from the beginning(using VHDL or Verilog),
>how can we change the design when we already made it?
>3. If the FPGA can do the same function like Microcontroller(such as
>Motorola 68HC11), is that any possibilities that FPGA will replace
>Microcontroller in the future?
>
>Thanks for your attention and help
>
>
>

Hi, I am a student in electronics so i don't know too much about it.
But FPGA stands for Field Programmable Gate Array. And is not
something like a microcontroler. So it won't replace it.

A microcontoler is continuisly driven by software. An FPGA is some
kind of board filled with and/or/xor etc. ports. Using these ports a
complete PCB can be programmed into the device. Depending on the used
technology the FPGA can be reprogramed or not.
To change the design you have to change your VHDL design and implement
the desing again.

As i don't know evry thing I just can advise you to visit the internet
site of Xilinx (great site) Actel and altera. These are all
manufacturers of FPGA's and PLD's.

HHK
Article: 16157
Subject: PCI slave in FPGA?
From: zaitcev@bogus.com (Pete Zaitcev)
Date: Thu, 06 May 1999 18:39:00 GMT
Links: << >>  << T >>  << A >>
Hi everybody:

I am sorry if this is an FAQ or if I am not doing my homework.
Basically I am a software guy who tries to size up a small hardware
project (does it send shivers up your spine?).

Can someone tell me if it is possible to purchase a shrink
wrapped design which has PCI on one side and 8 bit bus
on other side? (I think it is called a "macro").
I have no idea about attainable size in contemporary
FPGAs... PCI looks awfuly complex to me.

If such a thing exists, where can I find one? And how much that may cost?
A million $$? A hundreed thousand?

An option which I would be eager to find is a GPL-ed FPGA design
for a PCI slave. I heard there is a guy named J. H. Allen who made 
a design (a CPU) under a sort of GPL (LGPL). That sounds wonderful for a
software person, so that I can change stuff myself, and contribute
it back. This is not a requirement though.

Thanks,
--Pete
Article: 16158
Subject: Re: How do I design this ?
From: John Janusson <jjanusso@nospam.i-o.com>
Date: Thu, 06 May 1999 13:40:28 -0500
Links: << >>  << T >>  << A >>
I'm not familiar with these specs, but I can tell you that you'll probably want
to oversample more that 8 times for any real world application...  128 or 256 is
probably a better number...  and I'll post this link again since I found it to
be an excellent source of design ideas for stuff like this (it's schematics, not
vhdl)...

http://www.microlet.com/yam/yamfeat.htm

John


Zeki Basbuyuk wrote:

> Hi,
> I work for a wireless radio company. I am looKing for some "sounding board".
> On one of the designs, we have a synchronous interface s/th like V.35 or
> RS-449 etc. I am designing a multiplexer using VHDL. I would like to
> implement an all digital PLL. A VCO simulated as an NCO, Phase comparator,
> integrator, etc. etc. My question is as follows.
> Is this a sound approach, or am I missing something such as jitter that the
> NCO would intorduce? The NCO source would be running approximately 8 times
> or higher than the clock I would like to generate. Are there any
> standards(formal or nonformal) as far as acceptable clock jitter for
> synchronous systems? I know there are for G.703 but I couldn't find any for
> V.35 RS-449, v.11
> Thank you.



Article: 16159
Subject: 68HC11+EPLD development system
From: Slavek Przepiorski <s.przepiorski@auckland.ac.nz>
Date: Fri, 07 May 1999 07:48:40 +1300
Links: << >>  << T >>  << A >>
68HC11+EPLD development system


Dear colleagues,
I can announce that, you may find new development system for 68HC11 
and EPLD in one, at the address below:
http://www.ele.auckland.ac.nz/info/techos/design/tools/labest.htm 
Any queries mailto: s.przepiorski@auckland.ac.nz
Article: 16160
Subject: Re: How do I design this ?(synchronous interface)
From: "Zeki Basbuyuk" <zbasbuyuk@moseleysb.com>
Date: Thu, 6 May 1999 14:10:06 -0500
Links: << >>  << T >>  << A >>

John Janusson wrote in message <3731E21C.E815ED14@nospam.i-o.com>...
>I'm not familiar with these specs, but I can tell you that you'll probably
want
>to oversample more that 8 times for any real world application...  128 or
256 is
>probably a better number...

It is a good suggestion but I have some limitations as far as how fast I can
go in digital domain. The data rates are as high as 8Mbits. The highest I
can use in my system will be at 60 MHz.




Article: 16161
Subject: Re: Fpga gates, PLD gates ASIC gates: Help us please.
From: elh@vu-vlsi.ee.vill.edu (Edward L. Hepler)
Date: 6 May 1999 16:52:20 -0400
Links: << >>  << T >>  << A >>
In article <3731c513.698195@news.wxs.nl>, hhk <hhk@wxs.nl> wrote:
>The big problem is: What are PLD gates, ASIC gates an what are FPGA
>gates. And above all: What is the DIFFERENCE between these types of
>gates.

ASIC gate counts are traditionally given in terms of "equivalent 2-input
nands"...  When looking at the cells (gates) that make up a standard
cell library, usually the area of a 1X drive 2-input nand is used 
as the "area" of 1 gate.  All other cells' areas are normalized to this
value to determine their respective gate equivalency...  So a D flipflop
may be 10 gates, while an inverter may appear to be 0.6 gates.  Sometimes
an asic vendor will round to the nearest integer, so an inverter and a
2-input nand both have the cost of 1 gate.

Most SRAM based FPGAs use a small SRAM with some extra logic and perhaps
4 D flipflops to make up a cell (LUT, etc).  The inputs to the cell are 
used as the address lines to the SRAM.  During programming, the SRAM
is loaded with the appropriate values so that it produces the desired
logic function for the inputs; in other words, it becomes a table lookup
device.  The outputs from the SRAM typically feed the inputs to the 
D flipflops and also are available as outputs of the cell...  By 
connecting the outputs from cells together, most logic functions can
be produced.   (This has been an oversimplified description of an
FPGA, but is good enough to make the necessary points.)    Most FPGA
vendors base the gate counts that they can accomodate by estimating 
the number of gates that it might take to replace the look-up table
and flipflops...   Most of the time, these assumptions are printed
(in a small font) somewhere on the spec sheets...  Note also that 
since there are (for example) 4 flipflops in the cell, then by an
ASIC's standards, there are already 40 gates in the cell... 

But consider a large decoder.  It may be primarily combinatorial and not
need the 4 flipflops attached to each cell.  Further, it may need many
cells to produce the desired combinatorial result(s).   So the "typical"
gates/cell number that the vendors advertise may be quite optimisitc.
For example, I have recently produced some VHDL IP which implements
a 68000 object-code compatible processor.  The instruction decoder takes the 
16 bit instruction and produces many signals that are used elsewhere in the 
design and in the state-machine, etc.  The decoder synthesizes to about 
1400 gates when targeting a traditional standard cell ASIC library.  The 
same VHDL sythesizes to 573 LUTs when targeting an SRAM based FPGA!!
this means that each LUT is only giving me the equivalent of about 3 gates!

The overall design synthesizes to about 24,000 (equivalent 2-input nands)
when targeting a standard-cell library, but requires an FPGA that claims
to be capable of 80,000 to 100,000 gates when targeting the FPGA...

So, to summarize, the definition of a gate for ASICs is pretty well defined,
but the gate count for FPGAs and the way a gate is defined for them is
pretty much a spec-man-ship game that the marketing folks play!

Hope this helps.

Ed Hepler

Dr. Edward L. Hepler
  President,                     Adjunct Professor, 
  VLSI Concepts, Inc.            Villanova University Graduate Courses:
    VLSI and System                  ECE-8440 System Design and Modeling 
      Architecture, Design,          ECE-8445 Advanced Computer Architecture
      and CAD                        ECE-8460 VLSI Design
email: hepler@vlsi-concepts.com  or  elh@ece.vill.edu
voice: (610) 408-9121
fax:   (610) 408-9121
www:   http://www.vlsi-concepts.com     Read: I John 5:10-13


Article: 16162
Subject: "DACafe.com: The ultimate resource for the EDA customers"
From: p_sin@my-dejanews.com
Date: Fri, 07 May 1999 06:06:34 GMT
Links: << >>  << T >>  << A >>


Check out www.dacafe.com for the latest in the EDA world,the world's most
comprehensive EDA design tool directory,online EDA engineering books(complete
manuscripts)and a lot more.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 16163
Subject: Re: DSP in FPGA
From: Brian Pedersen <brian@kom.auc.dk>
Date: Fri, 07 May 1999 07:38:44 GMT
Links: << >>  << T >>  << A >>
"Cemal Coemert (TIP)" wrote:
> 
> Hi everyone,
> 
> I would like to implement some DSP functions in a FPGA ( with VHDL ).
> Where can I get some examples?

The question you might want to ask is "How do i implement DSP
functionality in FPGA ?". Probably the easiest way is by encoding a
state machine doing what you want. You can code it in a semi-behavioral
style, a FIR filter could look like the one I have made available at
http://www.danbbs.dk/~kibria/brian/dsp/fir_filt_ctrl.vhd (synthesizable
by Exemplar Leonardo):

I'm sorry for the lack of comments, and that some of the comments are in
danish. Try to see if you can get anything out of it. For designs just a
little more sophisticated than a FIR filter, it is necessary to
partition your design in smaller parts (FSM, Datapath components etc.).
For methods to do this in a structured manner, you could look at Daniel
Gajski: Principles of Digital Design.

--                                               
Brian Pedersen, DSP Student                    _/     _/_/_/  _/_/_/  _/
Applied Signal Processing and Implementation  _/_/   _/       _/   _/ _/
Department of Communication Technology       _/  _/   _/_/_/  _/_/_/  _/
Aalborg University, Denmark                 _/_/_/_/       _/ _/      _/
URL: http://www.danbbs.dk/~kibria/brian/   _/      _/ _/_/_/  _/      _/
Article: 16164
Subject: Re: PCI slave in FPGA?
From: Le mer Michel <michel.lemer@ago.fr>
Date: Fri, 07 May 1999 10:13:51 +0200
Links: << >>  << T >>  << A >>
Pete Zaitcev wrote:

> Hi everybody:
>
> I am sorry if this is an FAQ or if I am not doing my homework.
> Basically I am a software guy who tries to size up a small hardware
> project (does it send shivers up your spine?).
>
> Can someone tell me if it is possible to purchase a shrink
> wrapped design which has PCI on one side and 8 bit bus
> on other side? (I think it is called a "macro").
> I have no idea about attainable size in contemporary
> FPGAs... PCI looks awfuly complex to me.
>
> If such a thing exists, where can I find one? And how much that may cost?
> A million $$? A hundreed thousand?
>
> An option which I would be eager to find is a GPL-ed FPGA design
> for a PCI slave. I heard there is a guy named J. H. Allen who made
> a design (a CPU) under a sort of GPL (LGPL). That sounds wonderful for a
> software person, so that I can change stuff myself, and contribute
> it back. This is not a requirement though.
>
> Thanks,
> --Pete

Hello

See the web site of your target vendor. They have list of cores you can
purchase.

Hope this helps,

Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes (France)
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 16165
Subject: Re: BGA Prototyping ?
From: Edgar Conzen <conzen@atecomedgar.com>
Date: Fri, 07 May 1999 11:02:53 +0200
Links: << >>  << T >>  << A >>


Pascal Dornier wrote:
 
> Amen. BGA, it takes balls...

ROTFL!!!!!!!!!!

-- 
    --------->>>>  ! ANTI-SPAM !   

  "edgar"  has to be removed from my email address
These are my private opinions, not those of my employer
Article: 16166
Subject: Re: How do I design this ?
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 07 May 1999 11:02:33 GMT
Links: << >>  << T >>  << A >>
Hi Zeki,

On Thu, 6 May 1999 10:53:45 -0500, "Zeki Basbuyuk"
<zbasbuyuk@moseleysb.com> wrote:
>Hi,
>I work for a wireless radio company. I am looKing for some "sounding board".
>On one of the designs, we have a synchronous interface s/th like V.35 or
>RS-449 etc. I am designing a multiplexer using VHDL. I would like to
>implement an all digital PLL. A VCO simulated as an NCO, Phase comparator,
>integrator, etc. etc. My question is as follows.
>Is this a sound approach, or am I missing something such as jitter that the
>NCO would intorduce? The NCO source would be running approximately 8 times
>or higher than the clock I would like to generate. Are there any
>standards(formal or nonformal) as far as acceptable clock jitter for
>synchronous systems? I know there are for G.703 but I couldn't find any for
>V.35 RS-449, v.11
>Thank you.

Short answer:
I don't know of any intrinsic jitter specs for those serial interfaces
either.
I would guess that 0.05UIp-p intrinsic jitter is as low as you would
ever need to go for most datacomms (except for those that use echo
cancellation, but that doesn't apply here).
You will probably find that the inputs of most systems will tolerate
about 0.4UIp-p (wideband) before they fall over.  (At 0.4UIp-p, the
eye pattern is almost closed.)
For systems that have dedicated clock lines (and don't need to recover
the clock from the data) the jitter tolerance can be HUGE.  It will be
limited only by buffer sizes inside the uart (or whatever).

Long answer:
For the G.703 interface, you can get the intrinsic jitter figures from
a number of sources:

From the high frequency tolerance figures from G.823:

Rate		High Frequency Jitter Tolerance
64kb/s		0.05UIp-p = 781ns p-p
2.048Mb/s	0.2UIp-p  = 96.6ns p-p
8.448Mb/s	0.2UIp-p  = 23.6ns p-p
(The intrinsic jitter must be less that the maximum tolerable jitter,
of course.)

From G.736 Max Intrinsic Jitter:
2.048Mb/s	0.05UIp-p = 24.4ns p-p

I don't have G.742 handy, but I imagine that the figure would be
0.05UIp-p intrinsic at 8.448Mb/s, which comes out as 5.9ns p-p.

Commercial M13 (or whatever) multiplexer chips that work at these
rates often have on board analog PLLs.  This is a bit hard to do with
RTL VHDL ;-)

The ones that don't have PLLs seem to have DLLs with phase rotators.
Again, they are hard to describe in RTL VHDL, and are impossible in
FPGAs.
(Before anyone pipes up: No, you can't use the built in DLLs in Virtex
parts for this.)

The basic idea is that you use the DLL to synthesise 360 degrees worth
of N evenly spaced phases of a reference clock.  The frequency of this
clock is nominally the same as the output frequency.
You then use an N to 1 multiplexer to pick off the appropriate phase
to send to the output.
Typically an NCO would be used to drive the multiplexer select lines.
If there is a frequency offset, the selected multiplexer tap will jump
from one phase to the next, causing the phase to always advance (or
retard) from the reference phase, producing the frequency offset.
The intrinsic jitter produced is roughly the size of the phase steps.
This would be 1/N UIp-p.
The major advantage is that all the logic operates at the reference
clock rate.  You don't need a high speed sampling clock to keep the
jitter low.

Muxes in wireless radios that I've designed (years ago - I wouldn't do
this now) have used PLLs using VCXOs as their jitter reducers.
This approach might work for you as you only have an intrinsic jitter
problem at the higher bit rates.  Use a single VCXO, and divide its
output with a fractional N divider for the lower rates.  This gets
expensive if you have multiple channels (one VCXO per channel).

I've also seen commercial multiplexer chips (using NCOs) that
effectively doubled the sampling clock frequency by being able to
update the output on both the rising and falling edge of the clock,
thus halving the intrinsic jitter.
In this case (instead of just using the NCO MSB as the output) look at
the most significant few NCO bits and work out which clock edge is the
best one to use for each output edge.
The NCO only has to run at the clock rate.
I guess this is sort of like the DLL with phase rotator, but with only
two phases.

Since you are after an all digital approach using synthesisable VHDL,
I guess the last one is the only help I can give.

Regards,
Allan.
P.S.  I've used Moseley equipment before.  A stereo generator, from
when I used to work in broadcast radio.
Article: 16167
Subject: Re: How do I design this ?
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 07 May 1999 11:16:17 GMT
Links: << >>  << T >>  << A >>
On Fri, 07 May 1999 11:02:33 GMT,
allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote:
>[snip]
>Muxes in wireless radios that I've designed (years ago - I wouldn't do
>[snip]

Wireless radios indeed!  I meant digital radios.

Oops,
Allan.
Article: 16168
Subject: Re: BGA Prototyping ?
From: roman pollak <roman.pollak@Sun.COM>
Date: Fri, 07 May 1999 13:26:08 +0200
Links: << >>  << T >>  << A >>
Pascal Dornier wrote:
> 
> Stephen Maudsley wrote in message <7gsd3h$sei$1@plutonium.btinternet.com>...
> >
> >roman pollak <roman.pollak@Sun.COM> wrote in message
> >news:373197BB.7986C450@Sun.COM...
> >> Hi,
> >>
> >> I'm looking for some kind of socket or other tool for bga device.
> >> Actually, I'm wondering how other people deal with BGA devices as
> >well.
> >
> >Haven't used sockets since PGA. Solder them direct and get the board
> >right first time.
> 
> Amen. BGA, it takes balls...

When you can do it with soldering iron, that's ok for you. But I got a
problem with it. I guess you don't have the whole waveflow soldering
machine at home, don't you ?

regards roman
Article: 16169
Subject: Re: BGA Prototyping ?
From: rk <stellare@erols.com.NOSPAM>
Date: Fri, 07 May 1999 08:40:01 -0400
Links: << >>  << T >>  << A >>
hi,

no, i don't have a waveflow soldering iron machine at home.  nor am i very good
with a regular soldering iron.

but there's one company who makes bga sockets with an array of pins on the
bottom.  this is bolted down to the board (carefully) and all those little
contacts are made.  i do have one such socket but don't recall the vendor's name
off-hand - home today - but can look it up if anyone's interested. i haven't
actually tried it out yet as it's for a board that i have planned in the next
month or so.

rk

_________________________________________________________

roman pollak wrote:

> Pascal Dornier wrote:
> >
> > Stephen Maudsley wrote in message <7gsd3h$sei$1@plutonium.btinternet.com>...
> > >
> > >roman pollak <roman.pollak@Sun.COM> wrote in message
> > >news:373197BB.7986C450@Sun.COM...
> > >> Hi,
> > >>
> > >> I'm looking for some kind of socket or other tool for bga device.
> > >> Actually, I'm wondering how other people deal with BGA devices as
> > >well.
> > >
> > >Haven't used sockets since PGA. Solder them direct and get the board
> > >right first time.
> >
> > Amen. BGA, it takes balls...
>
> When you can do it with soldering iron, that's ok for you. But I got a
> problem with it. I guess you don't have the whole waveflow soldering
> machine at home, don't you ?
>
> regards roman



Article: 16170
Subject: Re: DSP in FPGA
From: Ray Andraka <randraka@ids.net>
Date: Fri, 07 May 1999 09:05:57 -0400
Links: << >>  << T >>  << A >>
 An FPGA DSP application is normally a point solution that does just one
thing, but does it very well.  When a different function is needed, the FPGA
is reloaded with a specific circuit for that task.  This is in stark
contrast to a DSP microprocessor, which does many things but is not
optimized for any one particular task.  The FPGA circuits for DSP are
generally highly pipelined data path structures.  Some simple examples are
FIR filters, multipliers and adders.  Examples of these can be found on the
various FPGA vendor's web pages.

State machines in most FPGA DSP applications I've dealt with are dirt simple
or even non-existant.  If there is a state machine, it is usually something
simple just to provide control signals to the data path (clears, add
subtract controls and the like).  In pipelined processors this can usually
be handled by a simple counter and a string of delay elements.

The highly data path nature of DSP in FPGAs demands attention to the
implementation and placement if you expect to achieve the performance and
density goals you are using an FPGA for in the first place.  For that
reason, you will likely find that you need to specify placement in your
design (this may not be true for altera 10K because of the device
architecture- see deja news for posts I've made on the device selection
subject before).  In any event, you do need to pay attention to the device
architecture when doing your design whether it is by schematic, VHDL,
verilog or stone and chisel.  VHDL tends to hide the architectural detail,
so it is very easy to wind up with something that does not map nicely to the
architecture.  Also, some VHDL synthesizers do not support placement.  Those
that do
(synplicity and exemplar) require use of a structural style and user
attributes.  It is messy, but fortunately much of it can be hidden in lower
levels of the hierarchy if you develop a library of components.  The main
point of this rant is that you can use VHDL, but unless you already are
intimately familiar with the FPGA architecture and the VHDL tools, don't
expect the same performance you can get with schematics (because VHDL
purposely insulates the user from the architecture).  By doing your designs
in a structured hierarchical manner, you will find that there is a fairly
small set of building blocks that you use over and over.  One of the
advantages of VHDL (FPGA express doesn't cut it here) is the ability to
create a library of parameterizable placed macros for this set of functions
instead of having a separate (but similar) macros for each bit combination
of parameters as you would with schematics.

That said, there are also algorithmic considerations.   First, while
floating point can be done in FPGAs, it is expensive and usually not
warranted.  Fixed point implementations imply a number of limitations due to
scaling, precision and overflow you need to consider in your design.  Also,
multipliers can be expensive.  Often rearranging the algorithm or trying a
different approach to solving the problem can lead to significant hardware
savings as well as performance gains.

Brian Pedersen wrote:

> "Cemal Coemert (TIP)" wrote:
> >
> > Hi everyone,
> >
> > I would like to implement some DSP functions in a FPGA ( with VHDL ).
> > Where can I get some examples?
>
> The question you might want to ask is "How do i implement DSP
> functionality in FPGA ?". Probably the easiest way is by encoding a
> state machine doing what you want. You can code it in a semi-behavioral
> style, a FIR filter could look like the one I have made available at
> http://www.danbbs.dk/~kibria/brian/dsp/fir_filt_ctrl.vhd (synthesizable
> by Exemplar Leonardo):
>
> I'm sorry for the lack of comments, and that some of the comments are in
> danish. Try to see if you can get anything out of it. For designs just a
> little more sophisticated than a FIR filter, it is necessary to
> partition your design in smaller parts (FSM, Datapath components etc.).
> For methods to do this in a structured manner, you could look at Daniel
> Gajski: Principles of Digital Design.
>
> --
> Brian Pedersen, DSP Student                    _/     _/_/_/  _/_/_/  _/
> Applied Signal Processing and Implementation  _/_/   _/       _/   _/ _/
> Department of Communication Technology       _/  _/   _/_/_/  _/_/_/  _/
> Aalborg University, Denmark                 _/_/_/_/       _/ _/      _/
> URL: http://www.danbbs.dk/~kibria/brian/   _/      _/ _/_/_/  _/      _/



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16171
Subject: Re: BGA Prototyping ?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 07 May 1999 09:11:49 -0400
Links: << >>  << T >>  << A >>
BGA devices are definitely not for the home builder.  Even the adapters that are
available require the BGA to be soldered to them.  There is simply no reliable way
to connect to a BGA other than properly mounting it to a pwb.  There are vendors
that will attach small quantities of BGAs to adapters such as those made by
ironwood and emulation technologies.  Even then, the cost of that service is not
all that cheap.

Waveflow soldering doesn't work for BGAs either.  You need to use IR techniques.


> When you can do it with soldering iron, that's ok for you. But I got a
> problem with it. I guess you don't have the whole waveflow soldering
> machine at home, don't you ?
>
> regards roman



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16172
Subject: Re: BGA Prototyping ?
From: "Stephen Maudsley" <Stephen.Maudsley@esgem.com>
Date: Fri, 7 May 1999 14:33:02 +0100
Links: << >>  << T >>  << A >>

Ray Andraka <randraka@ids.net> wrote in message
news:3732E695.F30AE67D@ids.net...
> BGA devices are definitely not for the home builder.  Even the
adapters that are
> available require the BGA to be soldered to them.  There is simply no
reliable way
> to connect to a BGA other than properly mounting it to a pwb.  There
are vendors
> that will attach small quantities of BGAs to adapters such as those
made by
> ironwood and emulation technologies.  Even then, the cost of that
service is not
> all that cheap.
>
> Waveflow soldering doesn't work for BGAs either.  You need to use IR
techniques.

A hot air gun (professional hair-dryer?) works reasonably well. If the
array of pads is well positioned then the surface tension from the wet
solder tends to self-align the device.

See if you can get your supplier to provide some dead devices to
practise with,


--
Stephen Maudsley mailto:Stephen.Maudsley@esgem.com
Esgem Limited: embedded system design http://www.esgem.com
Tel: +44-1453-521626 Mobile: +44-370-810991
Personal pages: http://www.esgem.com/people/Stephen.Maudsley

Article: 16173
Subject: Re: BGA Prototyping ?
From: husby@fnal.gov (Don Husby)
Date: Fri, 07 May 1999 13:53:46 GMT
Links: << >>  << T >>  << A >>
roman pollak <roman.pollak@Sun.COM> wrote:
> I'm looking for some kind of socket or other tool for bga device.
> Actually, I'm wondering how other people deal with BGA devices as well.

We're at the same juncture here, preapring to use BGA for the first time.
For prototyping, we've found a few companies that can re-work BGA's if
necessary, so it looks like the best all around solution is to take your
chances and pay the price if you goof up.  Some of the sockets are as
expensive as the chips.

One thing we're considering is putting a through-hole under each pad.
For prototypes, this appears to be a better solution than using a socket
because it gives access to every pin without introducing much extra
capacitance or inductance which can be significant at 200 MHz.  The
worry here is that the BGA will not seat well into a donut-shaped solder
bump, or that the through-hole will drain the solder away.  One solution
to this would be to pre-fill each hole with a high-temperature solder.
Obviously, for production we would re-do the boards to eliminate the holes.

I've also seen companies that will solder a BGA device into a PGA chip
carrier.  Then you can use sockets or through-holes.

Article: 16174
Subject: Re: BGA Prototyping ?
From: Helmut Juchems <hj@datus.com>
Date: Fri, 07 May 1999 16:01:17 +0200
Links: << >>  << T >>  << A >>
roman pollak schrieb:

> craig_jacobs@asl-tk.com wrote:
> >
> > In article <373197BB.7986C450@Sun.COM>,
> >   roman pollak <roman.pollak@Sun.COM> wrote:
> > > Hi,
> > >
> > > I'm looking for some kind of socket or other tool for bga device.
> > > Actually, I'm wondering how other people deal with BGA devices as well.
> > >
> > > regards roman
> > >
> >
> > I've never used the following product, but I am looking for bga prototyping
> > devices also and I found a few web sites.  You may want to check out this web
> > site.
> >
> > http://www.emulation.com/catalog/off-the-shelf_solutions/prototyping_adapters/
> >
> > I remember coming across a few other web sites but I disremember the addresses
> >
> > Craig Jacobs
> > Automotive Systems Labs
> >
>
> Thanks, This exactly what I'm looking for. Any Idea about Prices ?
>
> regards roman

Very expencive! The price for an BGA357 (MPC860 - Motorola Power Quicc) is about
$1000 only for the adapter with ZIF-socket.

A much cheaper solution is soldering the BGA-Chip on an adapter (BGA to PGA) and on
the mainboard a socket (PGA to BGA).

Some usefull links:
http://www.advintcorp.com
http://www.arieselec.com
http://www.precisionint.com

We use adapter sockets from Precision Interconnect.
Prices (>50 pieces): Adapter $20, Socket $25
The prototyping adapter for our Tektronix logic analyzer costs about $1200
(Emulation Technologies).

Helmut Juchems

DATUS GmbH
http://www.datus.com




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