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Messages from 26900

Article: 26900
Subject: Re: OT: Xilinx T-Shirt
From: Phil James-Roxby <phil.james-roxby@xilinx.com>
Date: Thu, 02 Nov 2000 16:45:21 -0700
Links: << >>  << T >>  << A >>
Richard Chidester wrote:
> 
> Gentlemen,
> 
> Due to some difficulties, the shirts were held up in manufacturing!  We have
> them in stock now and we will start shipping.

I second that, if I trot out of my cube I can see them right there in
front of me (unless we have 2 loads of t-shirts knocking about).  And I
thought they were for the staff :-(  
Phil

-- 
---------------------------------------------------------------------
 __
/ /\/  Dr Phil James-Roxby         Direct Dial: 303-544-5545
\ \    Staff Software Engineer     Fax: Unreliable use email :-)
/ /    Loki/DARPA                  Email: phil.james-roxby@xilinx.com
\_\/\  Xilinx Boulder                 
---------------------------------------------------------------------

Article: 26901
Subject: Re: OT: Xilinx T-Shirt
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 02 Nov 2000 16:46:56 -0700
Links: << >>  << T >>  << A >>
fred wrote:
> 
> You're hooked matey, they don't need to butter you up.

Yeah, I know.  Sucks, don't it?

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 26902
Subject: Re: OT: Xilinx T-Shirt
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 02 Nov 2000 16:48:33 -0700
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
> 
> On 2 Nov 2000 10:17:10 -0600, "James S." <ads@begone.com> wrote:
> 
> >A few months ago Xilinx had a survey up on their website for their software
> >users, and they said that if you filled it out, you would get a free
> >t-shirt.  I filled out that survey but never got the shirt.  Did anybody
> >else?  I enjoy using Xilinx's products and would love to get a t-shirt.
> 
> A few months ago, a US cable company broadcast a high-profile boxing
> match. During one of the breaks, they ran a commercial offering a free
> T-shirt for the viewers. However, the cable company deliberately
> rigged it so that the signal was scrambled during the ad, so even the
> pay-per-view subscribers couldn't see it.
> 
> Why? Answer tomorrow if no-one gets it...

My guess is that it exposes those who've got illegal converter boxes. 
Instead of getting a shirt in the mail, they get a visit by the local
police department!

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 26903
Subject: Re: Need a PCB speaker driven by XCV100
From: Ray Andraka <ray@andraka.com>
Date: Thu, 02 Nov 2000 23:50:53 GMT
Links: << >>  << T >>  << A >>
I wouldn't drive a conventional speaker directly with the FPGA pins, there isn't
enough drive to get a decent volume. For best results, you'll need a driver, and
with only 3.3v to play with you'll want that to be a full bridge configuration. 
You could do one of several things: 1) roll your own simple driver with discrete
transistors or a transistor array, 2) use a speaker amplifier such as an LM380
(I think that's the number...national makes/made it, it is a low power audio
power amp) 3) use a bridge driver designed for motors.

You might also be able to use a piezo speaker if you drive it using two I/O pins
in a split phase configuration.  At 3.3v, however, I think you'll find the
output levels marginal and will probably wind up trying quite a few speakers to
find one with adequate freqency range and signal level.  For narrower ranges,
the piezos with a resonating chamber do OK on a +5 to -5 volt swing.  


Dan wrote:
> 
> I want to generate a given frequency 40HZ to 5KHZ with counters and output
> this to a speaker mounted on a PCB.
> 
> LowQuality is accepatble.
> Power enough to be heard by human from 10 feet.
> 
> Please recommend a speaker and interface for FPGA.
> 
> Thanks
> Dan

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26904
Subject: Re: Alliance under Linux?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 03 Nov 2000 01:56:40 +0000
Links: << >>  << T >>  << A >>


Duane wrote:The one weak link on Linux is a lack of a synthesis tool. Though

> Synplicity had a job posting for Linux programmer some months back, so
> here's hoping...
>

Its supposed to be out real soon and as far as I've been informed it won't
cost any extra
but that was before the IPO

>
> I actually purchased VMware, since I still need it to run the synthesis
> tools. But that is all I use it for. All my other tools are either
> native Linux or run under wine.

What simulator are you using under Linux & how much extra did you have to
pay over the NT price ?

Article: 26905
Subject: Re: OT: Xilinx T-Shirt
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 03 Nov 2000 02:07:02 +0000
Links: << >>  << T >>  << A >>


Rainer Buchty wrote:

> In article <3a0192f8$0$32688$45beb828@newscene.com>,
>  "James S." <ads@begone.com> writes:
> |> A few months ago Xilinx had a survey up on their website for their software
> |> users, and they said that if you filled it out, you would get a free
> |> t-shirt.  I filled out that survey but never got the shirt.  Did anybody
> |> else?  I enjoy using Xilinx's products and would love to get a t-shirt.
>
> I received one...
>
> Regards,
>         Rainer
>
> --
>

... an incredibly rare event here of a European getting something out of Xilinx
before the Americans - pity it only happens with T-shirts & not useful stuff like
s/w. Be careful though since in a years time you'll only be allowed to wear it on
those dates you wore it the previous year.



Article: 26906
Subject: Re: OT: Xilinx T-Shirt
From: Ray Andraka <ray@andraka.com>
Date: Fri, 03 Nov 2000 05:11:19 GMT
Links: << >>  << T >>  << A >>
Oh, so they're Spartan II T-Shirts then?

Richard Chidester wrote:
> 
> Gentlemen,
> 
> Due to some difficulties, the shirts were held up in manufacturing!  We have
> them in stock now and we will start shipping.
> 
> Best regards,
> Richard Chidester
> 
-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26907
Subject: Re: OT: Xilinx T-Shirt
From: Bob Perlman <bobperl@best_no_spam_thanks.com>
Date: Fri, 03 Nov 2000 05:39:56 GMT
Links: << >>  << T >>  << A >>
On Thu, 02 Nov 2000 19:57:56 GMT, eml@riverside-machines.com.NOSPAM
wrote:

>On 2 Nov 2000 10:17:10 -0600, "James S." <ads@begone.com> wrote:
>
>>A few months ago Xilinx had a survey up on their website for their software
>>users, and they said that if you filled it out, you would get a free
>>t-shirt.  I filled out that survey but never got the shirt.  Did anybody
>>else?  I enjoy using Xilinx's products and would love to get a t-shirt.
>
>A few months ago, a US cable company broadcast a high-profile boxing
>match. During one of the breaks, they ran a commercial offering a free
>T-shirt for the viewers. However, the cable company deliberately
>rigged it so that the signal was scrambled during the ad, so even the
>pay-per-view subscribers couldn't see it.
>
>Why? Answer tomorrow if no-one gets it...

They were all out of cable-knits?

Bob Perlman

>
>Evan


Article: 26908
Subject: Re: Need a PCB speaker driven by XCV100
From: Phil Hays <spampostmaster@sprynet.com>
Date: Thu, 02 Nov 2000 23:05:24 -0800
Links: << >>  << T >>  << A >>
Dan wrote:
 
> I want to generate a given frequency 40HZ to 5KHZ with counters and output
> this to a speaker mounted on a PCB.

Small speakers usually don't output much of anything at 40 Hz.  Resonance
frequency is often 200+ Hz, and there is a steep falloff in acoustic output
below resonance, along with other effects.  Harmonics and distortion will still
be heard, however, so you will hear something, but just not the 40 Hz.


> Power enough to be heard by human from 10 feet.

In a quiet room?  On a busy factory floor?
 

> Please recommend a speaker and interface for FPGA.

You might try Digikey # P9610-ND.

http://www.digikey.com/EC/V3/402.pdf


To drive this to rated power of 0.16 W @8 ohms you need to supply +-140mA at
+-1.1 volts.  The voltage swing isn't a problem, but the current is higher than
rated for a Virtex output.  The best a Virtex output could do is +-24 mA
(LVTTL), which would drive 5 mW into 8 ohms.  Would need to use resisters to
limit AC current and reduce DC currents.  Speakers are reactive, you would want
to check for overshoot.

The question I asked above applies:  How loud does it need to be?  Some real
rough estimates follow.  The above speaker is rated at 93db output (test
conditions not listed, however fairly standard test would be referenced to 1W
input measured at 1 meter away).  The difference in distance would drop the
level by about 6db, and rated power to this speaker would drop sound level
almost another 10db.  This gives a very rough estimate of sound level of 80db at
3 meters.  On a loud factory floor already at 100db, 80db output would probably
not be enough.  In a quiet room at 50db, 80db output would probably be more than
enough.  5 mW would result in around 65 db at 3 meters.  Not loud, but noticable
in a quiet place.


-- 
Phil Hays

Article: 26909
Subject: Re: Need a PCB speaker driven by XCV100
From: "Olaf Birkeland" <Olaf_Birkeland@coldmail.com>
Date: Fri, 3 Nov 2000 09:52:33 +0100
Links: << >>  << T >>  << A >>
"Dan" <daniel.deconinck@sympatico.ca> wrote in message
news:U%gM5.420347$1h3.11445756@news20.bellglobal.com...
> I want to generate a given frequency 40HZ to 5KHZ with counters and output
> this to a speaker mounted on a PCB.
>
> LowQuality is accepatble.
> Power enough to be heard by human from 10 feet.
>
> Please recommend a speaker and interface for FPGA.
>

Using a speaker, I would definitively use some sort of external driver since
speakers are quite nasty loads. National have a wide range of suitable
parts, e.g. LM4862/LM4864
(http://www.national.com/parametric/0,1850,799,00.html) There are also
devices where you can control the gain digitally from the Virtex. But in
your application, a simple NPN/NMOS transistor driver stage will be
sufficient (square wave output, not "audio")

And since it not audio, you should check whether a piezo buzzer/speaker
(e.g. http://www.sonitron.be/) would be usable.

Regards,
- Olaf





Article: 26910
Subject: Re: OT: Xilinx T-Shirt
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 03 Nov 2000 09:42:17 GMT
Links: << >>  << T >>  << A >>
On Thu, 02 Nov 2000 16:48:33 -0700, Andy Peters <"apeters <"@> n o a o
[.] e d u> wrote:

>eml@riverside-machines.com.NOSPAM wrote:
>> 
>> On 2 Nov 2000 10:17:10 -0600, "James S." <ads@begone.com> wrote:
>> 
>> >A few months ago Xilinx had a survey up on their website for their software
>> >users, and they said that if you filled it out, you would get a free
>> >t-shirt.  I filled out that survey but never got the shirt.  Did anybody
>> >else?  I enjoy using Xilinx's products and would love to get a t-shirt.
>> 
>> A few months ago, a US cable company broadcast a high-profile boxing
>> match. During one of the breaks, they ran a commercial offering a free
>> T-shirt for the viewers. However, the cable company deliberately
>> rigged it so that the signal was scrambled during the ad, so even the
>> pay-per-view subscribers couldn't see it.
>> 
>> Why? Answer tomorrow if no-one gets it...
>
>My guess is that it exposes those who've got illegal converter boxes. 
>Instead of getting a shirt in the mail, they get a visit by the local
>police department!

Correct - I'm not suggesting that our favourite vendor would do such a
thing, though...  :)

Evan

Article: 26911
Subject: Re: clock multiplication and Spartan2 DLL placement constraints
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 03 Nov 2000 10:50:52 +0100
Links: << >>  << T >>  << A >>
Steven Derrien a écrit :

> If you're using M2.1, there is a bug in the mapper regarding the DLL
> placement contraints, this problem is (accoridng the xilinx website)
> adressed in M3.1.
> otherwis a workaround is provided in "Xilinx answer #6624" at
> support.xilinx.com (use keyword +dll +virtex +map)

I finally used the WebPack 3.2, which has the fixes too but doesn't cost
as much as the maintenance.
-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01      http://www.IPricot.com/

Article: 26912
Subject: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
From: n55weg@nikhef.nl (Gerard)
Date: Fri, 03 Nov 2000 10:44:33 GMT
Links: << >>  << T >>  << A >>
Currently we are working on a design with an APEX 20K100EBC356-1. We
used Quartus version 2000.05 to fit the design and, with hard effort,
could get it working on 40 MHz in the simulator.

Due to a Dr. Watson Application error problem in Windows NT (or
Illegal Operation in Windows 98 SE) in quartus_cmp.exe (always on
lower address 8901 !?)  with all versions of Quartus up and including
version  2000.05, we installed Quartus 2000.09. We did not see the
crash of Quartus (until now), but the timing results of the fitter are
significantly worse than with version 2000.05!

As an example the timing differences of a simple signal form a fast
input pin (A15) via a combinatorial cell to an output pin (E22):
Version 2000.05 and 2000.09 both seem to fit this signal in the same
way, only 2000.05 uses cell LC1_8_A1 while 2000.09 uses cell LC1_1_A1.
Version 2000.09 has 6.179 ns delay while version 2000.05 only needs
4.239 ns.

After contact with our local Altera distributor, we heard that Altera
has adjusted the timing parameters for the APEX devices in Quartus
2000.09, apparently with nanoseconds worse timing results. We are now
very concerned about the reliability of the Quartus fitter. Can all
timing results of version 2000.05 not be trusted and must version
2000.09 be used for reliable results? We did not receive any
information from Altera about this before we discovered these timing
differences ourselves.

Has anybody else also noticed these timing differences and what about
Altera covertly changing the timing parameters?


G. Kieft
NIKHEF: National Institute for Nuclear Physics and High-Energy Physics

(remove 'weg' from e-mail address when used for reply!)


Article: 26913
Subject: Re: cryptography/Block ciphers
From: Michael Strothjohann <strothjohann@rheinahrcampus.de>
Date: Fri, 03 Nov 2000 11:37:51 +0000
Links: << >>  << T >>  << A >>
for (synopsis-style) VHDL-code see :

         http://csrc.nist.gov/encryption/aes/round2/r2anlysy#NSA

    M.strothjohann

ajd schrieb:

> Hi,
>
> Is anyone writing any cryptographic algorithms or block ciphers on an FPGA.
> I'm interested as to what sort of throughput to aim for on my Xilinx
> Virtex1000 -4.
>
> thanks
> Andrew


Article: 26914
Subject: Re: cryptography/Block ciphers
From: "ajd" <dullrabbit@hotmail.com>
Date: Fri, 3 Nov 2000 11:49:04 -0000
Links: << >>  << T >>  << A >>

Thanks but I don't speak VHDL!

I think I'm looking at 500 MBits plus for Rijndael. Is this good?

Andrew

"Michael Strothjohann" <strothjohann@rheinahrcampus.de> wrote in message
news:3A02A38F.668ADABC@rheinahrcampus.de...
> for (synopsis-style) VHDL-code see :
>
>          http://csrc.nist.gov/encryption/aes/round2/r2anlysy#NSA
>
>     M.strothjohann
>
> ajd schrieb:
>
> > Hi,
> >
> > Is anyone writing any cryptographic algorithms or block ciphers on an
FPGA.
> > I'm interested as to what sort of throughput to aim for on my Xilinx
> > Virtex1000 -4.
> >
> > thanks
> > Andrew
>



Article: 26915
Subject: Re: Alliance 3.2i
From: koch@ultra4.eis.cs.tu-bs.de (Andreas Koch)
Date: 3 Nov 2000 13:38:21 GMT
Links: << >>  << T >>  << A >>
In article <39FFF85C.7768C053@sonyoxford.co.uk>,
Gary Cook  <gc@sonyoxford.co.uk> wrote:
>It's the crashing during p&r bug .... recently reintroduced by
>popular demand ... coming to you at a p&r run soon!
>
>Fixed by setting VCCGND_OFF=1
>
>Gary.
>
>Ray Andraka wrote:
>
>> I'm using it.  It fixes a number of bugs, but there is one that it created.
>> Can't remember off hand which one it was, as I currently have several cases
>> open.  It is supposed to be fixed in the service pack due out next week.

Hmm, but that seems to lead to the VCC and GND nets not being split at all,
and the BITGEN message

WARNING:DesignRules:476 - Netcheck: Improper routing. Signal GLOBAL_LOGIC0 is
   routed with too many unbuffered connections. Some loads on this net may have
   their delay under reported by the timing tools. Rerouting this net is
   advisable. To resolve this error, please consult the answers database at
   http://support.xilinx.com

The final result is the design failing to work in hardware (even
though post-layout simulations run OK). I assume that what we are seeing
here are on-chip `ground bounce' effects.

Tech note #10284 seems to have been revised once again. It now
talks of a service pack 5 which should fix the problem. That SP isn't
linked on the web site, but can be retrieved by directly entering
the URL (use the one for SP4 and change the `4' to a `5').

I sure hope it finally fixes this bug. Otherwise I'll be going back to
SP3 ...

  Andreas Koch
-- 
Andreas Koch                                  Email  : koch@eis.cs.tu-bs.de
Technische Universit"at Braunschweig          Phone  : x49-531-391-2384
Abteilung Entwurf integrierter Schaltungen    Phax   : x49-531-391-5840
Gaussstr. 11, D-38106 Braunschweig, Germany   * PGP key available on request *

Article: 26916
Subject: Re: Alliance under Linux?
From: Jamie Lokier <spamfilter.nov2000@tantalophile.demon.co.uk>
Date: 03 Nov 2000 15:11:22 +0100
Links: << >>  << T >>  << A >>
eml  writes:
> Exactly. And how many of us actually care about whether or not we have
> source code? As far as I'm concerned, it's just wasting valuable disk
> space.

Haven't you ever used a program ("X") that has a simple but critical
bug, and the vendor won't be fixing it for a year?

Never had to avoid certain constructs on your code because the synthesis
tool generates the wrong circuit?

Never had a project where a simple change to X would be simpler than
a big bunch of scripts to pre-process and post-process the files you
pass to/from X?

In my experience, source === if the vendor won't fix their program in a
timely fashion, I can.  Or I look to see if someone else has.  Sure it's
a little extra effort, but weigh that up against the cost of working
around the bugs or lack of critical features.

-- Jamie

Article: 26917
Subject: Re: cryptography/Block ciphers
From: Eric LaForest <ecl@pet.dhs.org>
Date: Fri, 3 Nov 2000 14:13:08 +0000 (UTC)
Links: << >>  << T >>  << A >>
Nicholas Weaver <nweaver@soda.csua.berkeley.edu> wrote:
> In article <3a016161@news2lo.highwayone.net>,
> ajd <dullrabbit@hotmail.com> wrote:
>>Hi,
>>
>>Is anyone writing any cryptographic algorithms or block ciphers on an FPGA.
>>I'm interested as to what sort of throughput to aim for on my Xilinx
>>Virtex1000 -4.

Here are some references:

http://www.counterpane.com/twofish-fpga.html
http://www.cs.berkeley.edu/~iang/isaac/hardware/main.html
http://www.cse.cuhk.edu.hk/~phwl/biography.html
(see Refereed Conference Papers)

HTH

Eric LaForest


Article: 26918
Subject: ACEX1K vs FLEX10K
From: martin.j.thompson@trw.com (Martin Thompson)
Date: Fri, 03 Nov 2000 14:40:55 GMT
Links: << >>  << T >>  << A >>
Can anyone tell me what the difference between the ACEX and FLEX
families of Altera devices is?  As far as I can tell, the only
difference is the number of packages supported...

Anyone from Altera lurking here?

Thanks,
Martin

-- 
Martin Thompson
martin.j.thompson@trw.com

Article: 26919
Subject: High Slice Usage in Virtex-E
From: Bruce Oakley <oakley@amirix.com>
Date: Fri, 03 Nov 2000 14:47:01 GMT
Links: << >>  << T >>  << A >>
We're currently implementing a number of FPGA designs using Virtex-E
parts, and I'm a little curious about "slice usage".  In some cases, it
seems to get fairly high even though flip-flop usage and LUT usage are
pretty moderate.

(Quick review:  A slice is simply two logic cells, sharing some common
structure ... clocks, etc.)

It seems clear that slice usage might be much larger than FF/LUT usage
if there are lots of different clock domains, clock enables, etc.  These
would reduce the degree to which logic could share slices.  However,
we're seeing cases where slice usage explodes without these conditions.
For example, in a design with only two clock domains and a minimum of
complicated clock enabling and reset structures we see:

FF usage:  47%
LUT usage:  26%
Slice usage:  93%

Can anybody explain why slice sharing seems to be so low?  For what its
worth, we're not really pushing hard on speed performance.

More importantly, should I have some level of comfort that I will be
able to access the unused resources in these slices if the design grows?

Thanks for any help,
Bruce.

--
--------------------------------------------------------
Bruce Oakley   [ oakley@amirix.com ]
Principal Hardware Designer
AMIRIX Systems, Inc.             PH: (902)450-1700 x 245
Halifax, Nova Scotia, CANADA     FX: (902)450-1704
http://www.amirix.com
--------------------------------------------------------



Article: 26920
Subject: Re: Alliance under Linux?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 03 Nov 2000 15:13:28 GMT
Links: << >>  << T >>  << A >>
And it is an absolute nightmare for source control, particularly when the work
goes to a third party as it does for most consulting.  Also creates problems if
you have multiple projects with different tweaks in the source code.  No
thanks.  I'd rather work around the bug and have everyone working with the same
set of tools than open this can of worms.

Jamie Lokier wrote:
> 
> eml  writes:
> > Exactly. And how many of us actually care about whether or not we have
> > source code? As far as I'm concerned, it's just wasting valuable disk
> > space.
> 
> Haven't you ever used a program ("X") that has a simple but critical
> bug, and the vendor won't be fixing it for a year?
> 
> Never had to avoid certain constructs on your code because the synthesis
> tool generates the wrong circuit?
> 
> Never had a project where a simple change to X would be simpler than
> a big bunch of scripts to pre-process and post-process the files you
> pass to/from X?
> 
> In my experience, source === if the vendor won't fix their program in a
> timely fashion, I can.  Or I look to see if someone else has.  Sure it's
> a little extra effort, but weigh that up against the cost of working
> around the bugs or lack of critical features.
> 
> -- Jamie

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26921
Subject: Re: High Slice Usage in Virtex-E
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 03 Nov 2000 16:10:16 GMT
Links: << >>  << T >>  << A >>
On Fri, 03 Nov 2000 14:47:01 GMT, Bruce Oakley <oakley@amirix.com>
wrote:

>FF usage:  47%
>LUT usage:  26%
>Slice usage:  93%
>
>Can anybody explain why slice sharing seems to be so low?  For what its
>worth, we're not really pushing hard on speed performance.

The mapper defaults to putting unrelated logic in different CLBs. If
you haven't got a good reason to pack the logic, then you should leave
it this way. Have a look at the '-c' option to map. You could also
play with the '-r' map option - this disables register ordering, which
allows unrelated registers to be packed together. You could also try
turning off logic replication (look at map's '-l' option).

Evan

Article: 26922
Subject: Re: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
From: "Marc" <marc.nospam@iname.com>
Date: Fri, 3 Nov 2000 17:30:05 +0100
Links: << >>  << T >>  << A >>
Gerard,

Got the same problem with designs in 20K400 and 20K600.

An FAE will come to me and have a look, he didn't have an answer ......

Hope old 2000.05 designs are reliable, otherwise I'm in big problems....

Marc

"Gerard" <n55weg@nikhef.nl> wrote in message
news:3a02946f.12819663@news.cern.ch...
> Currently we are working on a design with an APEX 20K100EBC356-1. We
> used Quartus version 2000.05 to fit the design and, with hard effort,
> could get it working on 40 MHz in the simulator.
>
> Due to a Dr. Watson Application error problem in Windows NT (or
> Illegal Operation in Windows 98 SE) in quartus_cmp.exe (always on
> lower address 8901 !?)  with all versions of Quartus up and including
> version  2000.05, we installed Quartus 2000.09. We did not see the
> crash of Quartus (until now), but the timing results of the fitter are
> significantly worse than with version 2000.05!
>
> As an example the timing differences of a simple signal form a fast
> input pin (A15) via a combinatorial cell to an output pin (E22):
> Version 2000.05 and 2000.09 both seem to fit this signal in the same
> way, only 2000.05 uses cell LC1_8_A1 while 2000.09 uses cell LC1_1_A1.
> Version 2000.09 has 6.179 ns delay while version 2000.05 only needs
> 4.239 ns.
>
> After contact with our local Altera distributor, we heard that Altera
> has adjusted the timing parameters for the APEX devices in Quartus
> 2000.09, apparently with nanoseconds worse timing results. We are now
> very concerned about the reliability of the Quartus fitter. Can all
> timing results of version 2000.05 not be trusted and must version
> 2000.09 be used for reliable results? We did not receive any
> information from Altera about this before we discovered these timing
> differences ourselves.
>
> Has anybody else also noticed these timing differences and what about
> Altera covertly changing the timing parameters?
>
>
> G. Kieft
> NIKHEF: National Institute for Nuclear Physics and High-Energy Physics
>
> (remove 'weg' from e-mail address when used for reply!)
>
>



Article: 26923
Subject: Thanks to all for great input EOM
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 03 Nov 2000 16:35:15 GMT
Links: << >>  << T >>  << A >>
Thanks to all for great input EOM



Article: 26924
Subject: I2C bus driven by Xilinx
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 03 Nov 2000 16:52:36 GMT
Links: << >>  << T >>  << A >>
Hi,

I have had a successful design using the XC3042-100PC84C. (In production
years)


Recently tried the same I2C logic in a XCS10-4TQ144C. The results are
intermittent.

The slave device fails to respond by driving the line low when tristated by
the FPGA.


The logic is trivial:

To send a I2C line low:
-endable tristate Ouput buffer
-and drive a 0 onto the IO pin

To send a I2C line high
- disable the tristate Output buffer. (The I2C line has a 10Kpullup)

Am I missing something in this driver logic ?

Dan










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