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Messages from 27750

Article: 27750
Subject: Re: NGDBUILD/UCF Problem
From: Gary Cook <gc@sonyoxford.co.uk>
Date: Wed, 06 Dec 2000 09:11:43 +0000
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:


> Verilog models. I don't know if the same is true of VHDL but I had to hack in
> some ``reduce paranoia'' changes into the 2.1i FF models to get them to work
> right. As for 1.5i, the LUT models were a joke. It looks like the 3.1 stuff is
> much better - maybe, like the FloorPlanner, Xilinx are coming around to the idea
> that ``push the friendly green STA button'' doesn't cut it for timing either. Now
> if I could just get those Virtex-E min timings ...
>
> Rick

I think you'll find the virtex-e min timings in the latest ds022.pdf (v1.8)
databook for virtex-e on xilinx's website ...

Gary



Article: 27751
Subject: Re: Gate Level Simulation Questions
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 06 Dec 2000 10:26:55 GMT
Links: << >>  << T >>  << A >>
On 5 Dec 2000 13:30:17 -0600, "Gary Spivey" <spivey@ieee.org> wrote:

>My question is - what do y'all feel about:
>
>1) The importance of at least being able to run a gate level simulation if
>you wanted to
>
>2) The wisdom of running gate level simulations on FPGA's in general

What's often forgotten about circuit verification is that you have to
verify (at least) *two* things:

1)  Whether the design meets timing, and
2)  assuming correct timing, whether the logic functions as intended.

Tim's link has some useful comments on (1), but not on (2). The only
ways to functionally verify a design are:

1) Simulate it at the *gate* level (assuming that the vendor's
gate-level models are correct, of course). Whether you put timing
information into your gate-level sim depends on whether you have an
STA, whether you trust the STA and your ability to constrain it, and
whether the STA can cope with your particular design; or

2)  If you have the tools, carry out a formal verification or
equivalancy check between your simulated RTL code and the silicon
vendor's gate-level output; or

3)  Put the chip on a board and see if it works.

Evan

Article: 27752
Subject: what's meaning?
From: chsw <chen.songwei@mail.zte.com.cn>
Date: Wed, 6 Dec 2000 03:20:16 -0800
Links: << >>  << T >>  << A >>
Hello:
  Now ,i am simulation witn NC-VERILOG .the warnings occrued:
  Timing violation
  $setup(negedge ENB :14600 PS,posedge CLKB :15460 PS,1040 :1040 ps);
  File:./simlib/X_RAMB4_s4_s16.v,line =668
Scope:test_bench .my.\p1/u4/b2/BU1/INTERNAL_BLOCKRAM
 Time:15460 PS
 what's meaning ? how do i?
 Thanks

Article: 27753
Subject: Re: Issues with Spartan II
From: "Gary Watson" <gary2@nexsan.com>
Date: Wed, 6 Dec 2000 14:01:05 -0000
Links: << >>  << T >>  << A >>
We didn't have any trouble getting a couple hundred XC2S150 in the FG456
package.  Possibly this is because we take care to schedule chip orders
just as soon as we think we might design them in to something.

I wonder if part of the problem is that if you list all the Xilinx FPGAs,
it's something like a thousand individual part numbers.  How can any company
possibly have all of those parts in stock?  It's almost like Xilinx would
have to make them to order, and of course you can forget the so-called
"distributors" keeping more than a fraction of these in stock**.

What I wish they would do, is say "ok, here are our favorite twenty parts,
which we will make by the truckload and promise to keep in stock at all
times".  Then, if we are a "small" customer, we would know better than to
deviate from the most common part numbers, while Compaq would still be able
to buy the optimum part for their application because they buy a million
parts scheduled two years in advance.


** "In Stock", inf., Obsolete term c. 1985 or before, apparently referring
to a practice where companies called "distributors" kept parts in large
boxes in the event orders came in for said parts.  In the modern era,
replaced by the concept of ordering parts five years before product design
commences in the hope that the chip fab line might be built some day; and
the concept of "allocation", which means Cisco and General Motors get parts,
and you don't.

--

Gary Watson
gary2@nexsan.com  (you should leave off the digit two for email)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
UK-based Engineers: See our job postings at
http://www.nexsan.com/pages/careers.htm

"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3A2BD51E.8F0FAA1E@xilinx.com...
> Let me address the two concerns:
>
> SpartanII availability through distribution is limited because these
> devices are being snapped up by the major customers at a faster rate than
> we expected. Xilinx will ship about a million SpartanII devices this
> quarter, so these are not sample quantities. They just don't make in onto
> the distributor shelves in sufficient numbers. This may not help you much,
> but it shows that there really is no fundamental problem. It's "just"
> excessive demand...




Article: 27754
Subject: FPGA starter kit
From: "Bassem" <bassem.abdel-aziz@alcatel.com>
Date: Wed, 6 Dec 2000 11:04:55 -0500
Links: << >>  << T >>  << A >>
Hi,

I am looking for an FPGA starter kit. Atmel's ATSTK40 looks like a perfect
candidate, but it looks like they don't make it anymore (I may be wrong
about that). Any suggestions on alternative kits or about how to buy the
Atmel one?

Thanks
Bassem





Article: 27755
Subject: Re: Issues with Spartan II
From: "John Janssen" <jjanssen@lmint.com>
Date: Wed, 6 Dec 2000 17:27:58 +0100
Links: << >>  << T >>  << A >>
Our distributor said that some Spartan II devices are available only as
engineering samples now. Production volumes are scheduled for January 2001.
He admited that production problems caused a delay for about half a year.

Developping has it's risks ........

John



Article: 27756
Subject: Re: what's meaning?
From: Srinivasan Venkataramanan <srini@realchip.com>
Date: Wed, 06 Dec 2000 17:21:57 GMT
Links: << >>  << T >>  << A >>
Hi,

In article <ee6ef07.-1@WebX.sUN8CHnE>,
  chsw <chen.songwei@mail.zte.com.cn> wrote:
> Hello:
>   Now ,i am simulation witn NC-VERILOG .the warnings occrued:
>   Timing violation
>   $setup(negedge ENB :14600 PS,posedge CLKB :15460 PS,1040 :1040 ps);
>   File:./simlib/X_RAMB4_s4_s16.v,line =668
> Scope:test_bench .my.\p1/u4/b2/BU1/INTERNAL_BLOCKRAM

  It tells you that you have a SETUP violation (for the ENB signal with
respect to CLKB signal). You should see why this happens and how to
rectify this (if necessary)

1.> Are you doing SDF back annotated simulations? If so this makess
sense, else just use " -NOTIMINGCHECKS" during "ncelab"

2.> Take a look at openbook documentation (or whatsoever - guess
Cadence has *upgraded* their docuemnattion from Version LDV 3.2 or so?)
on this topic.

Finally a brief but quite useful description of this problem can be
obtained from

http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book2/CH11/CH11.13.htm

See the Table 11.11

TABLE 11.11    Timing-check system task parameters.

It says

/* $setup (data_event, reference_event, limit [, notifier]);
violation = (T_reference_event)-(T_data_event) < limit */

So just do a one-to-one mapping of this to your report (data_event is
negedge ENB and so on..)

HTH,
Srini

>  Time:15460 PS
>  what's meaning ? how do i?
>  Thanks
>

--
Srinivasan Venkataramanan
ASIC Design Engineer
Chennai, India


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27757
Subject: Re: Using CPLD to configure SpartanII from parallel ROM.
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Thu, 07 Dec 2000 08:51:24 +1300
Links: << >>  << T >>  << A >>
Great, that helps heaps.

Thanks Mike.

Mike wrote:

> Oh, yeah, about the waiting after INIT thing.  The Spartan-II architecture is much different than the Spartan or Spartan-XL architecture, given it's a derivative of the Virtex architecture, and not the 4000 like Spartan and Spartan-XL.  You don't need to wait a set amount of time after INIT goes high.  Once INIT goes high, you can start pumping data at the part with no latency.  If you check out Figure 12 in the datasheet, it should a delay from INIT high to CCLK, but this is only for CCLK *output*, meaning Master Serial configuration.  If you are using Slave Serial or Slave Parallel, there is no required latency.
>
> Mike


Article: 27758
Subject: Re: FPGA starter kit
From: John Tasgal <john@tcl.prestel.co.uk>
Date: Wed, 06 Dec 2000 20:03:34 +0000
Links: << >>  << T >>  << A >>
Hello, 

In the UK it's available from 

http://www.kanda.com/

They've  just published a training kit for it so I assume it's still in
production.

John Tasgal
Manchester
UK

Bassem wrote:
> 
> Hi,
> 
> I am looking for an FPGA starter kit. Atmel's ATSTK40 looks like a perfect
> candidate, but it looks like they don't make it anymore (I may be wrong
> about that). Any suggestions on alternative kits or about how to buy the
> Atmel one?
> 
> Thanks
> Bassem


Article: 27759
Subject: Re: fpga: 32 bit parity generation in 4 ns for virtexE
From: "Walter Haas" <walter_haas@pmc-sierra.com>
Date: Wed, 6 Dec 2000 12:48:40 -0800
Links: << >>  << T >>  << A >>
Hey Nisreen,

Use an AREA_GROUP constraint for the module that does the parity. For example:

INST "parity_module/*" AREA_GROUP = PARITY ;

AREA_GROUP PARITY RANGE = CLB_R1C60:CLB_R10C80 ;

As a rule of thumb, whatever the size of the module you are placing, try to set the range to be 1.25x of 100% utilization (ie 75% utilization)

Cheers,

Wally

Article: 27760
Subject: dual port ram for altera
From: Jerry Pongstaporn <jerryp@enikia.com>
Date: Wed, 06 Dec 2000 21:29:03 GMT
Links: << >>  << T >>  << A >>
has anyone tried to implement a true dual port ram in an altera 20k
device.  by true dual port, i mean you can write and read both ports.
the only lpm they offer is lpm_ram_dp.  but that only allows you to
write one port and read the other.  i also tried the csdpram function
they offer, but i cannot get that to work.  that is a cycle-shared dual
port ram.  xilinx has a true dual port in their libraries, but i would
rather not switch from altera at this point.  has anyone else run into
this before?  btw, i am synthesizing vhdl with synplicity, and using
quartus for place and route.


Article: 27761
Subject: Re: dual port ram for altera
From: quittj@my-deja.com
Date: Wed, 06 Dec 2000 22:32:21 GMT
Links: << >>  << T >>  << A >>
In article <3A2EB079.98A36DD1@yahoo.com>,
  Jerry Pongstaporn <jerryp@enikia.com> wrote:
> has anyone tried to implement a true dual port ram in an altera 20k
> device.  by true dual port, i mean you can write and read both ports.
> the only lpm they offer is lpm_ram_dp.  but that only allows you to
> write one port and read the other.  i also tried the csdpram function
> they offer, but i cannot get that to work.  that is a cycle-shared
dual
> port ram.  xilinx has a true dual port in their libraries, but i would
> rather not switch from altera at this point.  has anyone else run into
> this before?  btw, i am synthesizing vhdl with synplicity, and using
> quartus for place and route.
>
>

Jerry,

I am attempting this very thing.  I was finally able to get csdpram to
work, here is an example off of the Altera web site:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY cycle IS
    PORT (dataa    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          datab    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          addressa : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          addressb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          wea,web  : IN STD_LOGIC;
          clock    : IN STD_LOGIC;
          clockx2  : IN STD_LOGIC;
          qa       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
          qb       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cycle;

ARCHITECTURE lpm OF cycle IS
BEGIN
    U1: csdpram
            GENERIC MAP (LPM_WIDTH => 4, LPM_WIDTHAD => 4)
            PORT MAP (dataa => dataa, datab => datab,
                      addressa => addressa,
                      addressb => addressb, wea => wea,
                      web => web, clock => clock,
                      clockx2 => clockx2, qa => qa,
                      qb => qb);
END;

You can take a closer look at the LPM to see what these ports actually
are, BTW: you will need to setup a PLL or something that can give you
2x of the system clock, since the csdpram needs the multiplied clock.
If you just drop this in it should work though.


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27762
Subject: Re: ADAPTIVE FILTER
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Wed, 06 Dec 2000 14:46:02 -0800
Links: << >>  << T >>  << A >>
Saqib,

Adaptive filters are self adjustable filters which adapt according to
the input signals. The filter
adapts to the input signals by changing  filter coefficients.

You can refer "XAPP55: Block Adaptive Filter" app. note for some basic
information on these filters. This app. note is available at
http://support.xilinx.com/apps/xapp.htm

In addition to this, you may also find some useful information at
www.dspguru.com.

-Vikram
Xilinx Applications


Saqib wrote:

> Hi!
> Any body knows some good sites providing basic information regarding
> the adaptive filter theory..?
>
> --
> --saqib yaqub--
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 27763
Subject: Re: Wide AND function.
From: Duane <junkmail@junkmail.com>
Date: Wed, 06 Dec 2000 15:11:07 -0800
Links: << >>  << T >>  << A >>
Phil James-Roxby wrote:
> 
> erika_uk@my-deja.com wrote:
> > how can i control the use of BX?.can i direct the tool to get 0 or 1
> > from what you said above ?
> 
> The mainstream tools will/should infer the use of this structure.  If
> you need total control and would enjoy messing with CLB resources like
> this, the only tool that works at this level is JBits.
> Phil

And to be slightly more verbose about how to get the tool to infer
this... attach a GND or VCC to the CI input of the first MUXCY in the
chain, and the tools will infer that this is accomplished via the BX
input.

--
My real email is akamail.com@dclark (or something like that).

Article: 27764
Subject: Attention NYC Shoppers & Visitors - Beware of Rip-off SY Stores!!! ...... slNZc2N54
From: Veteran_NYC_Shopper@qudumi.org
Date: 6 Dec 2000 23:37:01 GMT
Links: << >>  << T >>  << A >>
SY stores have been around for about 50 years or so and have only one
objective - TO RIP YOU OFF!
-
They are a constant source of frustration for the NYC Department of
Consumer Affairs, which has been trying to close them down for as long as
I can remember. SY's are the most ruthless merchants in New York. I should
know, I once worked as a stock clerk for one of them.
-
The term "SY" refers to the ethnicity of the shopkeepers. They come from a
small and isolated region of Syria, where for centuries a cult of swindlers
has flourished. Approximately 60 years ago, they started to emigrate to the
U.S. and setup shop along Broadway at Times Square and later moved to some of
the less desirable locations along 5th Avenue.
-
Not surprisingly, SY stores are usually found in areas frequented by tourists.
-
You can always spot an SY store by the odd assortment of merchandise.
Radios, cameras and other assorted electronics on one side of the shop and
on the other; jade, ivory carvings, tablecloths, porcelain figurines,
oriental carpets, etc. 
-
SY stores are singular in their objective... To extract as much money from
the customer as possible, *buy virtually any means at all*. There is no set
price in an SY store. The salesman keeps 1/3 to 1/2 of the profit on everything
he sells (which is a strong incentive to overcharge) and overcharge he will!
It is not unusual for these merchants to charge upwards of  500 - 1000% profit
on an item, while leading you to believe that you're actually getting a bargain
(which is the cornerstone of their craft). 
-
These merchants are masters of deception and one should not try to match wits
with them. This is their lifelong profession... they've been doing it for
generations and most Americans are simply out of their league when it come to
trickery, deceit and high-pressure sales tactics.
-
A couple of things that might clue you in to the fact that you may stumbled into
an SY store:
-
If the staff speaks to one another in code words or in a language that you
don't recognize... if the words "Lot" or "C-Line" are used frequently in
reference to a specific item... if the price tag is marked with a price that
is demonstrably higher then it's being offered to you for, then chances are
your in an SY store.
-
JUST LEAVE!   It will be the best decision you made this holiday season and
both you and your checkbook (as well as your pride) will be all the better
for it.
-
Merry Christmas!
-
-
-
-
-
-
-




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Article: 27765
Subject: FPGA Express & VHDL files
From: V Ram <ipickledthefigsmyself@mrbourns.com>
Date: Thu, 7 Dec 2000 01:36:09 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello.

I am using FPGA Express 3.0 to synthesize some VHDL. I have segmented my
design into multiple blocks (entity&arch pair) each of which resides in a
separate VHDL file. 

If I used ModelSIM to simulate, I can make a "top-level" file and
instantiate "components" which are really the modules I designed. I use a
package to describe the modules and a custom library to hold the modules
and then in the top-level I use the library/components and tie it all
together with signals.

However, I cannot get FPGA Express to understand this, even if I create a
components library that matches my name and compile the smaller parts into
this library. Any suggestions? Any easier way to do a top-level file where
I simply connect blocks together? (Graphically)?

Thanks,
V. Ram.

Article: 27766
Subject: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 06 Dec 2000 17:44:46 -0800
Links: << >>  << T >>  << A >>
I wrote:
> It says "JBits will be available over the web in 1Q99."
>  But I can't seem to actually find it.  Any hints?

Neil Franklin <neil@franklin.ch.remove> writes:
> Mail to the address given on the page (JBits@xilinx.com). They then
> send you an URL (actually 3 URLs, Windows NT, Solaris, Linux) plus
> password. Then download (9MByte), install and have fun.

Too bad they don't answer their email.  I guess they don't need any
new customers.

Article: 27767
Subject: Need help regarding Partial reconfiguration
From: anup <anup@elec.uq.edu.au>
Date: Thu, 07 Dec 2000 13:06:18 +1000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------B4CD2D63CC56F24524CD2AA1
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello, Can someone give me starters on implementing designs that needs
to be partially reconfigured in the Xilinx Virtex FPGAs.
I am usign the Xilinx Foundation 3.1 series tools.
Thanks and regards
Anup

--------------B4CD2D63CC56F24524CD2AA1
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for anup
Content-Disposition: attachment;
 filename="anup.vcf"

begin:vcard 
n:Anup Kumar;Raghavan
tel;home:+61-7-38761962
tel;work:+61-7-33658849
x-mozilla-html:TRUE
url:www.elec.uq.edu.au/~anup
org:University of Queensland;Computer Science & Electrical Engineering
version:2.1
email;internet:anup@elec.uq.edu.au
adr;quoted-printable:;;47/401, Dept. of CSEE, UQ, =0D=0A=0D=0A;St.Lucia, Brisbane ;Queensland;4072;Australia
fn:Anup
end:vcard

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Article: 27768
Subject: verilog and arch
From: yose@wam.umd.edu (Joe Wetstein)
Date: 6 Dec 2000 23:06:27 -0500
Links: << >>  << T >>  << A >>
I am trying to pack alot into a CPLD. Problem is that my functions
are eating up macrocells and the corresponding FFs are then
unavailable for i/o. 

Is there a 'good' way to write Verilog to take best advantage
of my hardware, in some way to distribute the functions (is smaller
better? larger? distributed? as control in the "always @ clk" block
or as async in an "always @ <not-clk>" clock?

Anyone out there with alot of experience in synthesis?

Thanks!

Joe
yose@wam.umd.edu



Article: 27769
Subject: Re: FPGA Express & VHDL files
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 07 Dec 2000 13:06:35 +0900
Links: << >>  << T >>  << A >>
V Ram <ipickledthefigsmyself@mrbourns.com> writes:
> I am using FPGA Express 3.0 to synthesize some VHDL. I have segmented my
> design into multiple blocks (entity&arch pair) each of which resides in a
> separate VHDL file. 
> 
> If I used ModelSIM to simulate, I can make a "top-level" file and
> instantiate "components" which are really the modules I designed. I use a
> package to describe the modules and a custom library to hold the modules
> and then in the top-level I use the library/components and tie it all
> together with signals.

There should be no problem doing what you're trying to do with Express; 
having a top-level entity in a VHDL file, and instantiating your sub-modules.

I think that your problem may be the way that you're using libraries; try 
simply removing the library definitions, and compiling all your files as 
part of the same project.  When you tell Foundation which is your top level 
entity, it will find all the sub-entities as long as they are in files 
included in the same project.   You don't need to mess around with 
library definitions and so on.

Hope this helps.

If it doesn't, feel free to email me the code, and I'll give it a look-see.

-Kent.

Article: 27770
Subject: Re: FPGA starter kit
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Thu, 7 Dec 2000 08:39:51 +0100
Links: << >>  << T >>  << A >>
Hi,

there are two Altera starter kits (MAX/FLEX incl. software) from El Camino.
Check out the details at http://www.elca.de/prode.html . Soon, there'll also
be a new one, featuring an ACEX 1K device (100k gates). It will have audio
in/out, VGA out, NIOS support (16/32bit RISC with RAM/Flash), IDE interface,
RS232, USB and more - ideal for MP3 designs. Details on the new kit will be
released later this month. In the US these kits are sold through Colorado
Electronic Product Designs (CEPD, http://www.synthesize.com ).

Regards
Wolfgang

Bassem <bassem.abdel-aziz@alcatel.com> wrote in message
news:90lo36$n3r$1@kannews.ca.newbridge.com...
> Hi,
>
> I am looking for an FPGA starter kit. Atmel's ATSTK40 looks like a perfect
> candidate, but it looks like they don't make it anymore (I may be wrong
> about that). Any suggestions on alternative kits or about how to buy the
> Atmel one?
>
> Thanks
> Bassem
>
>
>
>



Article: 27771
Subject: Re: Need help regarding Partial reconfiguration
From: John Ayer <john.ayer@xilinx.com>
Date: Thu, 07 Dec 2000 07:21:34 -0800
Links: << >>  << T >>  << A >>
Hi Anup,

There are a couple of APP notes you may find useful.  One is XAPP 138
"Virtex Configuration and Readback" located at:
http://support.xilinx.com/xapp/xapp138.pdf .  Another is XAPP 151"Virtex
Series Configuration Architecture User Guide" located at:
http://support.xilinx.com/xapp/xapp151.pdf .
XAPP 151 goes in to much more detail on performing readback than 138, so
if this is your first attempt I would suggest reading 138 first to get a
feel for what is going on before looking at 151.

Other Virtex APP notes can be found at:
http://support.xilinx.com/apps/virtexapp.htm.


Hope this helps,
Regards,
John


anup wrote:

> Hello, Can someone give me starters on implementing designs that needs
> to be partially reconfigured in the Xilinx Virtex FPGAs.
> I am usign the Xilinx Foundation 3.1 series tools.
> Thanks and regards
> Anup


Article: 27772
Subject: Test Bench
From: Ramanathan <ramank@lucent.com>
Date: Thu, 07 Dec 2000 20:53:41 +0530
Links: << >>  << T >>  << A >>
Hi,

what is meant by a Test Bench?

Regards,
Ramanathan K.

Article: 27773
Subject: Re: Issues with Spartan II
From: sja@world.std.com (Stuart J Adams)
Date: Thu, 7 Dec 2000 17:16:02 GMT
Links: << >>  << T >>  << A >>
> We didn't have any trouble getting a couple hundred XC2S150

 We have not had trouble either. We have been getting 100 XC2S100's
 per month since September. (Of course we placed our order in 
 August with scheduled deliveries every month)

-- Stuart

Article: 27774
Subject: Re: jtag for fpga
From: harveytwyman@my-deja.com
Date: Thu, 07 Dec 2000 17:40:53 GMT
Links: << >>  << T >>  << A >>
We use the Altera MaxPlus II Development Tool in my department.

It has the JTAG facility for configuring individual devices or multiple
devices in cascade. They can be different types of FPGA or even
Configuration storage Devices like the EPC2.

The other nice feature is a limited form of 'Boundary Scan'.

This works with the device installed in Altera's remote programmer. The
programmer can then execute a series of 'Test Vectors' that were
created by the user during Simulation.

The results of the hardware tests are then superimposed within the
Simulator to highlight any differences.

I've not tried it, but it seems the next step forward from Simulation
to be able to evaluate the circuit is ACTUALLY working to specification
INSIDE the chip.

___________________________________________

H A R V E Y     T W Y M A N

Department of Electronics,
University of Kent.
Canterbury. U.K.

ABOUT ME: http://www.Twyman.org.uk/CV.htm
EMAIL ME: H.E.Twyman@ukc.ac.uk

___________________________________________


In article <3311930.975642034772.JavaMail.imail@digger.excite.com>,
  xiao_john@excite.com (frank johson) wrote:
> Can the Jtag interface be used to debug the FPGA (Xilinx or Altera) ?
> We developed some code for ASIC that has JTAG interface.First we want
to
> download to FPGA to verify code function,so I suppose the JTAG
function is
> same as ASIC that I can debug the hardware detail in FPGA.
> Any suggestion are welcome.
>
> Regards
> Frank
>
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