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Messages from 28225

Article: 28225
Subject: Re: Jedec to tms/tdi wiggles
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 02 Jan 2001 08:16:30 -0500
Links: << >>  << T >>  << A >>


Jon Schneider wrote:

> I've been tinkering with Xilinx's Webpack software and am rather
> impressed with it.
>
> If I now make up my own design of board up with a CPLD on it, where is
> it defined exactly how to go from the Jedec file output by the tools
> to doing things to the Jtag signals ?
>
> Ideally I expect to have to solder up a lead from say a standard
> parallel port to my board then ideally take a program and fill in the
> bits that say "insert code for raising tms here" and the like. Is
> there such a thing I can download ?

You can use the Xilnx software to generate SVF from the JEDEC file.  XESS
has tools (http://www.xess.com/downloads/xstools.exe) that will download
an SVF file into an XC9500 CPLD via the parallel port.  You can build your
hardware to match the circuitry of the XS95 Board
(http://www.xess.com/manuals/xs95-manual-v1_3.pdf) and use the XESS
software as is, or you can modify the source code of the downloader
(http://www.xess.com/downloads/xstools-source-v3_0.zip) to match your
hardware.

>
>
> Isn't this a FAQ ?
>
>         Jon

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 28226
Subject: Re: Jedec to tms/tdi wiggles
From: Jon Schneider <jms@geriatrix.circlesquared.cXoXm>
Date: 02 Jan 2001 13:41:27 +0000
Links: << >>  << T >>  << A >>

Dave Vanden Bout <devb@xess.com> writes:
> 
> You can use the Xilnx software to generate SVF from the JEDEC file.  XESS
> has tools (http://www.xess.com/downloads/xstools.exe) that will download
> an SVF file into an XC9500 CPLD via the parallel port.  You can build your
> hardware to match the circuitry of the XS95 Board

Yes I have already noticed Xess and indeed came across the Webpack
software through Xess's site in the first place. That was following
another question you or one of your colleagues kindly answered in one
of these newsgroups.

It is just a shame that the information isn't forthcoming from say Xilinx
or Jtag.org. Or if it is, it is too well hidden.

Rest assured I do have one of your boards on my shopping list anyway
but was just wondering about more of a production environment.

Could you possibly explain what an SVF file is please ?

        Jon

Article: 28227
Subject: Re: XC9500 and unused inputs
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Tue, 02 Jan 2001 10:02:20 -0700
Links: << >>  << T >>  << A >>
Paul Taylor wrote:
> 
> If you have 'programmable grounds' enabled, unused I/O pins will be
> driven to ground when the device is programmed and powered.
> 
> I think you can use PROHIBIT in the ucf file to prevent 'reserved' (unused)
> pins from being driven, while still driving all other unconnected pins
> to GND.
> 
> e.g.  CONFIG PROHIBIT = P3,P45,P99,P121,P143 ;
> 
> See Xilinx Answer 9385.

Prohibit prevents the tools from assigning an I/O port in your design to
a specific pin.

-- 
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."
Article: 28228
Subject: Re: XC9500 and unused inputs
From: "Paul Taylor" <p.taylor@ukonline.co.uk>
Date: Tue, 2 Jan 2001 21:05:09 -0000
Links: << >>  << T >>  << A >>
> > If you have 'programmable grounds' enabled, unused I/O pins will be
> > driven to ground when the device is programmed and powered.
> >
> > I think you can use PROHIBIT in the ucf file to prevent 'reserved'
(unused)
> > pins from being driven, while still driving all other unconnected pins
> > to GND.
> >
> > e.g.  CONFIG PROHIBIT = P3,P45,P99,P121,P143 ;
> >
> > See Xilinx Answer 9385.
>
> Prohibit prevents the tools from assigning an I/O port in your design to
> a specific pin.

But also prohibits PGNDs on specified pins not used in the design, but
connected to driven lines, AFAIK.   e.g. extra (unused) address signals!

Paul


Article: 28229
Subject: Re: Question about programming xcv100
From: Ray Andraka <ray@andraka.com>
Date: Wed, 03 Jan 2001 02:02:36 GMT
Links: << >>  << T >>  << A >>
The dual port mode is one way of updating LUT contents, and will work for 4K as
well as Virtex.  The Virtex SRL16 provides an even better mechanism for
reloading LUTs, as there is very little overhead and the density is the same as
a fixed LUT instead of double the resources.  Many LUTs can be strunct together
and reloaded as a serial shift chain.

Philip Freidin wrote:
> 
> On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote:
> >In article <3A45264E.F4FBE995@xilinx.com>,
> >  peter.alfke@xilinx.com wrote:
> >> David,
> >> let me talk you out of what you seem to be trying.
> >
> >Oh dear :-)
> 
> Well, I wont try and talk you out of it, but I will try and save you some
> time understanding your options.
> 
> First, permuting the bit stream directly (using an XC6200) has been done,
> and there were some interesting results.
> 
> see  http://www.cogs.susx.ac.uk/users/adrianth/ade.html
> 
> >> Xilinx used to make the XC6200 chip that did not have multiple outputs
> >> able to drive the same line, so it was bullet-proof, and it became the
> >> darling of experimenters like you.
> >> Unfortunately, XC6200 did not find a home in commercial applications,
> >so
> >> we stopped making it.
> >
> >Yes, someone recommended me to get one of those chips, however I
> >learned you weren't producing them anymore (and didn't know why they
> >had become so 'legendary' in this use anyway).
> >
> >> If you want to put evolving bitstreams on any Xilinx ( or Altera or
> >Atmel)
> >> FPGAs, don't do it !
> 
> Do it, but be really careful.
> 
> >What I was planning on doing (correct me if i'm way out of line here,
> >which is fairly possible) was taking each 'cell' on the fpga (in a
> >given area, for example an area of 20 x 20 cells) then having some
> >simple rules which i'd follow, deciding what the purpose of a given
> >cell was to be (within the rules, eg only one output to drive a given
> >line) then i'd take this meta design (arrived at through an evolving
> >algorithm) convert it to the bitstreams and pass the bitstream to the
> >chip using the xsload (comes with the Xess cdrom) where it would be
> >evaluated. However i'd need to find out what each bit for a cell
> >specified which I could then use to transfer my meta design to a
> >bitstream - is it possible to get this info [i'm just a hobbyist, no
> >danger of me seeking to get any competitive advantage over xilinx i can
> >assure you :-)]
> 
> What you do depends on how random/constrained you want the
> primordial soup to be, how long it takes to create an individual,
> and how long it takes to evaluate the individual.
> 
> First, the bitstream format is proprietory,and  Xilinx has given no
> indication that this will change. (Others who have seen this
> thread before (and before, and before) might think this is a
> wondeful opportunity to restart this thread again. Please, as my
> holiday wish, dont)
> 
> Since XC6200 is not readily available either, what that leaves
> you are neat products like Virtex, which have a wonderful set
> of features to play with.
> 
> So a typical Flow from a specification to an individual might be:
> 
> VHDL -> EDIF -> NCD -> Placed and routed NCD -> Bitstream.
> 
> For all the following proposals, you probably need to do things
> to make sure your specification of the individual does not specify
> anything illegal.
> 
> If time to create an individual is not an issue, have you individual
> generator create VHDL.
> 
> All the following require less time to create an individual, but have
> progressively more complex generator challenges :-)
> 
> Generate EDIF directly.
> 
> Generate unrouted NCD directly. Use a program called XDL which
> is available from Xilinx, if you ask. You need to do quite a lot of work
> to make this useable, but you do get full access to the chip's
> capabilities.
> 
> Generate routed NCD directly. Use a program called XDL which
> is available from Xilinx, if you ask. You need to do quite a lot of work
> to make this useable, but you do get full access to the chip's
> capabilities. Since you are skipping Place and route, this is faster
> than the previous suggestion, but now P&R is your responsibility
> 
> Edit a P&R NCD with JBITS. This program was created by people
> like you, for you. It is a Java interface to the bitstream. You use it
> either to creat a bitstream from scratch, or to modify an existing
> bitstream.
> 
> The FPGA editor program can be used to modify an NCD file, and
> it can be run in batch mode. Theoretically you could create a base
> individual, and create edit scripts to modify it.
> 
> >I didn't actually want to treat the bitstreams themselves as a piece
> >of 'dna' to mutate/breed etc although now that you've mentioned that
> >idea an XC6200 board would be a nice thing to have (if xilinx have any
> >such boards lying around destined for wastage... :-)
> 
> This is what Adrian Thompson did
> see  http://www.cogs.susx.ac.uk/users/adrianth/ade.html
> and in particular:
>   http://www.cogs.susx.ac.uk/users/adrianth/cacm99/paper.html
> 
> >Thanks for your warning though. Can you can help with that cell
> >programming info, or suggest any other way of approaching this
> >problem ? (i'm _really_ desperate to try this evolving hardware
> >thing...)
> >
> >David
> >
> 
> Here are some ideas for much easier stuff than above that you might
> want to consider, as a way to get started, and maybe get some
> useful results with very fast generation.
> 
> 1) Create a design that uses the LUTs in dual port RAM mode, and
> connect them up in some sort of mesh, with some feedback too.
> Use only one read port for all the logic. I.e. each pair of LUTs that
> run as 16 x 1 DP RAM, use the read port for building your individual.
> Connect all the write ports to the individual generator. For this
> topology, the interconnect is static, but you can vary the gate at
> an extremely fast rate.
> 
> 2) Like 1, but add some flipflops to the soup.
> 
> 3) Like 1 or 2, but allocate some LUTs to implement some muxes,
> and this then gives you some limited ability to change the routing.
> 
> 4) More of the same, add in block RAMs (maybe in dual port mode)
> 
> All of these can be done while avoiding the disaster of creating
> illegal bitstreams. With a careful design, you may be able to create
> individuals in as little as a micro second. If you can test them in the
> same amount of time, you could evolve 500,000 individuals per
> second, which might make up for the constraints of the soup.
> 
> Have fun.
> 
> Philip Freidin
> 
> Philip Freidin
> Fliptronics

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 28230
Subject: More than 4 clocks on VirtexE
From: murray@pa.dec.com (Hal Murray)
Date: 3 Jan 2001 04:37:41 GMT
Links: << >>  << T >>  << A >>

The VirtexE has 8 DLLs but only 4 GBUFs.  For some problems,
4 is not enough.

Anybody got any hints/suggestions/tricks for how to work with
more than 4 main clocks?  Is it a sensible thing to do or should
I just find some other way to get the job done.

One interesting case is when the clocks have the same frequency
but different phase.  I'd like to clock the input data in IOB FFs
and (of course) the clock is running fast enough that I need to
grab the data close to the middle of the bit cell so the normal
DLL/GBUF works nicely.


I tried to make a test design to see what would happen.  It
turned a BUF into a GBUF.  So I added enough logic to use up
both GBUFs.  It still turned my BUF into a GBUF but then said
it couldn't place all 3 of them.

I suspect it's trying to tell me "No".

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 28231
Subject: Re: Newbie question on clock timing generation
From: murray@pa.dec.com (Hal Murray)
Date: 3 Jan 2001 04:45:53 GMT
Links: << >>  << T >>  << A >>

> You route the common clock to all flip-flops.
> Then you design a state machine that generates clock enable signals
> that you route to the appropriate flip-flops' CE inputs..
> For example, a CE signal that is High for one out of three clock periods
> enables your CLK/3 flip-flops.

Do any languages/tools make it easy to write code like that?

I'd really like to write my code so that it uses clock3 rather than
using clock and cycle3 and cluttering things up with "if cycle3" all
over the place.

A simple text preprocessor would probably work, at least for stylized
code.  But I hate doing things like that when the tools don't support it
because you end up with error messages refering to line numbers
in the wrong file and such.

-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 28232
Subject: Re: really fast counter in SpartanXL?
From: murray@pa.dec.com (Hal Murray)
Date: 3 Jan 2001 04:49:40 GMT
Links: << >>  << T >>  << A >>

> To generate "random" test patterns, LFSRs are unbeatable.

They are very good for serial data, a stream that is 1 bit wide.

But how good are they for generating things like memory test
patterns where you need data that is N bits wide?

-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 28233
Subject: Re: FFs in IOBs in XC4000
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Wed, 3 Jan 2001 03:44:01 -0800
Links: << >>  << T >>  << A >>
Hello.
I wrote a small Verilog code, which contains a IFD and direct wire from the same IOB:

module iob ( IN, CLK, OUT, OUT_FF );
  input    IN, CLK;
  output   OUT, OUT_FF;
    ibuf IN_BUF   (.I(IN),.O(without_ff));
    ibuf CLK_BUF  (.I(CLK),.O(clk_in));
    bufg CLK_BUFG (.I(clk_in),.O(clk_ff));
    ifd  IFD      (.D(IN),.C(clk_ff),.Q(with_ff));
    obuf OUT_BUF  (.I(without_ff),.O(OUT));
    obuf O_FF_BUF (.I(with_ff),.O(OUT_FF));
endmodule 

I got no errors:

Design Summary:
   Number of errors:        0
   Number of warnings:      3
   Number of bonded IOBs:       4 out of   336    1%
      IOB Flops:            1
      IOB Latches:          0
   Number of BUFGLSs:           1 out of     8   12%

May be I didn't understand the question?

Jaan

>in a XC40250 design I want to 
>use the DFF for an input in the IOB but I want to use the 
>signal from the PAD directly, too. 
>
>
>Synopsys FPGA compiler generates a FDC symbol which map 
>seems not to be able to push into the IOB (-pr b WAS used!). 
>Using the IFD symbol (by replacing in the XNF using a perl script) 
>gives an error in NGDBUILD. 
>Obviously, the IFD contains the IBUF already. 
>Hence, there is a conflict with the IBUF driving the direct 
>input. 
>
>
>Is there a way to achieve this double usage? 
>Which symbol do I need for the FF?
Article: 28234
Subject: Re: Newbie question on clock timing generation
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 03 Jan 2001 11:46:05 GMT
Links: << >>  << T >>  << A >>
On 3 Jan 2001 04:45:53 GMT, murray@pa.dec.com (Hal Murray) wrote:

>> You route the common clock to all flip-flops.
>> Then you design a state machine that generates clock enable signals
>> that you route to the appropriate flip-flops' CE inputs..
>> For example, a CE signal that is High for one out of three clock periods
>> enables your CLK/3 flip-flops.
>
>Do any languages/tools make it easy to write code like that?
>
>I'd really like to write my code so that it uses clock3 rather than
>using clock and cycle3 and cluttering things up with "if cycle3" all
>over the place.
>
>A simple text preprocessor would probably work, at least for stylized
>code.  But I hate doing things like that when the tools don't support it
>because you end up with error messages refering to line numbers
>in the wrong file and such.

There are tools (Synopsys Powermill, for example) to do it the other
way round - ie. automatically create a gated clock from a clock enable
- but I've never heard of anything that'll generate clock enables from
clocks.

I suspect that it won't be too long before single-clock designs are
impractical on large FPGAs, and we'll have local clocks for different
sectors of the chip, with synchronisation at the boundaries. Power
consumption problems on large designs may also make multiple clocks
much more common.

Evan
Article: 28235
Subject: Re: Newbie question on clock timing generation
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 03 Jan 2001 11:46:29 GMT
Links: << >>  << T >>  << A >>
On Wed, 27 Dec 2000 17:52:30 GMT, Greg Neff <gregneff@my-deja.com>
wrote:

>> - To keep the power low, the clocks for each subcircuit may be gated.
>>
>
>No, they may not be gated.  Unless you know exactly what you are doing,
>and the internal architecture of the FPGA, you *must* clock all flip-
>flops directly from global clock nets.  No gates.

Remember that you can do all your gating *before* the clock buffer -

Evan
Article: 28236
Subject: 2-D DCT implementation
From: "Bo Petersen" <bp@contex.dk>
Date: Wed, 3 Jan 2001 15:07:08 +0100
Links: << >>  << T >>  << A >>
Hello, I am a newbie in FPGAs and am interested especially in
how to implement a 2-D DCT  using FPGA !

Does anyone know where I can find a spec./book which show and explain the
implementation ?

Thanks
Bo Petersen



Article: 28237
Subject: Partial reconfiguration using jbits
From: mlms@fe.up.pt
Date: Wed, 03 Jan 2001 14:14:22 GMT
Links: << >>  << T >>  << A >>
Hi all
I 'm writing a small program that takes two different bit files, created
using Foundation, compares them and them generates a partial
reconfiguration
file that turns one into the other. Using JBits commands I am able to
create
that bit file, but I don't know if it is a valid bit file, when I read
it
using JBits.readPartial a configuration exception is thrown.
Internal error detected in the partialBitstream
com.xilinx.JBits.Virtex.ConfigurationException: Configuration data not
found
(null bitstream).
The same thing happens using Device Simulation.
Using the Dump command I'm able to see that there are configuration
packets
in the file and it has the same structure that the reconfiguration file
used
in XAPP153, because of that I'm not sure that my bit file is not valid.
How can I be sure that my bit file is a valid file and how can I test it
before send it to the FPGA.
Thanks
Miguel


Sent via Deja.com
http://www.deja.com/

Article: 28238
Subject: Hardware Eng IV : FPGA/ASIC Design Engineer/Arch, $80 to $110, Ottawa, Large Telecom
From: "OSFT Inc." <info@osft.com>
Date: Wed, 03 Jan 2001 15:26:10 GMT
Links: << >>  << T >>  << A >>
Hardware Eng IV : FPGA/ASIC Design Engineer/Arch

Typically requires MSEE/CS combined with 3+ years of related experience, or
BSEE/CS combined with 5+ yrs related experience. Specification, design,
development and test of high complexity FPGAs/ASICs is the primary
responsibility. This includes architecture design, functional and design
specs, Verilog/VHDL design entry, simulation, synthesis, etc. Skills also
required for system & FPGA/ASIC lab verification, debug, integration, and
the designs of diagnostics firmware to aid in that verification, etc.

Understanding or previous design experience with high-performance packet
switches or packet processing. Participates on a project team of engineers
involved in the specification, design, development and test of hardware,
that may include any of the following list of responsibilities: Participates
in defining the design and implementation processes and procedures.
Responsible for board level complex architecture design. Writes board level
functional and design specs and hardware manuals. Writes complete unit and
integration test plans. Debugs complex board level problems. Performs
complex board level unit and integration tests. Designs moderate complexity
ASICs and FPGA. Designs board level diagnostics firmware. Resolves issues
with CAD and Manufacturing Engineers in developing new boards. Designs board
level simulation tests. Consults with in-house packaging and other
compliance engineers during design process to ensure compliance requirements
will be met.

Email: info@osft.com
Fax: 416-260-5973

Opensoft Inc. is continuously hiring Java/XML Engineers for their on-going
web-based solutions project work in the financial services, technology
delivery and professional services groups of Opensoft Consulting Group Inc.

Opensoft Inc. enables our Blue-Chip and Start-Up companies to recruit for
the delivery of their E-Commerce, Internet/Intranet, OO and
Client-Server projects. Opensoft Inc. has gained recognition as being able
to define the right candidate for the right job. Unlike other
consulting companies we do not shop your resume; we will however, help you
make the right career decision. Opensoft Inc. has one of the most
prominent Java/XML/Web Solutions Integration, teams in North America.

Please e-mail a version of your resume to info@osft.com in either MS WORD or
ASCII text. Please Note: Your resume will not be forwarded to
any client without your consent. Also due to the large numbers of
exceptional candidates responding to our postings we will only contact
those which are a match on the skills required by our clients. Others will
be added to our database and will be called when a suitable opportunity
comes available.




Article: 28239
Subject: Hardware Engineer/FPGA's for Ruggedized PC/Driver Design, Excellent $$$, Toronto
From: "OSFT Inc." <info@osft.com>
Date: Wed, 03 Jan 2001 15:26:41 GMT
Links: << >>  << T >>  << A >>
Scope of the Position:
To participate in the design, development and integration of hardware
designs for new and existing product lines. To assist in the introduction of
new technologies, processes and standards to realize better performance and
lower cost.

Key Responsibilities:
 Assist in preparing time and cost estimates and project planning.
 Participate in a team to design and develop highly integrated
motherboards, interface and display boards for demanding embedded ruggedized
PC applications.
 Design and develop FPGA's for interface and timing boards.
 Assist in hardware/firmware selection, integration and debugging of third
party hardware.
 develop drivers for custom board designs
 Work with third party suppliers of semi-custom hardware to ensure
compliance with requirements and certification standards.
 Define and set-up test environment for custom boards design and
development.
 Develop and maintain hardware documentation and drawings.

Qualifications:
Knowledge / Experience
 3+ years experience in the design and integration of custom PCBs and FPGAs
and third party hardware.
 Experience with PCB and FPGA design tools
 Working knowledge of electrical/mechanical design for ruggedized PC
applications.
 Experience with Ethernet, SCSI, RS422, SDLC, fiber and USB interfaces
would be an asset.
 Knowledge of computers, peripheral equipment, test, diagnostic and
measuring equipment.
 Knowledge of applicable procedures, specifications and engineering
software/simulation tools.

Education / Training
 a degree in Electrical or Industrial Engineering

Skills / Aptitudes
 Excellent oral and written communications skills.

Email: info@osft.com
Fax: 416-260-5973

Opensoft Inc. is continuously hiring Java/XML Engineers for their on-going
web-based solutions project work in the financial services, technology
delivery and professional services groups of Opensoft Consulting Group Inc.

Opensoft Inc. enables our Blue-Chip and Start-Up companies to recruit for
the delivery of their E-Commerce, Internet/Intranet, OO and
Client-Server projects. Opensoft Inc. has gained recognition as being able
to define the right candidate for the right job. Unlike other
consulting companies we do not shop your resume; we will however, help you
make the right career decision. Opensoft Inc. has one of the most
prominent Java/XML/Web Solutions Integration, teams in North America.

Please e-mail a version of your resume to info@osft.com in either MS WORD or
ASCII text. Please Note: Your resume will not be forwarded to
any client without your consent. Also due to the large numbers of
exceptional candidates responding to our postings we will only contact
those which are a match on the skills required by our clients. Others will
be added to our database and will be called when a suitable opportunity
comes available.




Article: 28240
Subject: ASICS Design, VoIP, FPGA, $70k to $100+relocation, Ottawa
From: "OSFT Inc." <info@osft.com>
Date: Wed, 03 Jan 2001 15:26:59 GMT
Links: << >>  << T >>  << A >>
Job Description
The successful candidate will be a member of a multidisciplinary design team
developing ASICs. These ASICs are a key enabling technology for
leading-edge IP voice systems and VoIP telephone sets.

Specific duties include:
Definition and detailed design of functional modules of complex ASICs.
Testbench development.
Module verification.
System integration and verification.

Qualifications
B.Sc. in electrical engineering or equivalent.
-----------------------------------------------
The candidate should have a minimum of 2 years experience designing and
verifying ASICs or FPGAs.
The job requires a good working knowledge of Synopsis, Verilog HDL, C, Unix,
and the overall ASIC development process.

Experience in the following would be an asset:
ARM microprocessors.
LAN and Ethernet technologies.
Voice processing technologies.

Email: info@osft.com
Fax: 416-260-5973

Opensoft Inc. is continuously hiring Java/XML Engineers for their on-going
web-based solutions project work in the financial services, technology
delivery and professional services groups of Opensoft Consulting Group Inc.

Opensoft Inc. enables our Blue-Chip and Start-Up companies to recruit for
the delivery of their E-Commerce, Internet/Intranet, OO and
Client-Server projects. Opensoft Inc. has gained recognition as being able
to define the right candidate for the right job. Unlike other
consulting companies we do not shop your resume; we will however, help you
make the right career decision. Opensoft Inc. has one of the most
prominent Java/XML/Web Solutions Integration, teams in North America.

Please e-mail a version of your resume to info@osft.com in either MS WORD or
ASCII text. Please Note: Your resume will not be forwarded to
any client without your consent. Also due to the large numbers of
exceptional candidates responding to our postings we will only contact
those which are a match on the skills required by our clients. Others will
be added to our database and will be called when a suitable opportunity
comes available.




Article: 28241
Subject: IC Hardware Design, Telecom company, Ottawa, $70k to $100k+great benefits, relocation
From: "OSFT Inc." <info@osft.com>
Date: Wed, 03 Jan 2001 15:27:25 GMT
Links: << >>  << T >>  << A >>
Our Client:
Major Telecommunications Company

HARDWARE DESIGNER

Job Description
you will be responsible for designing our client's next generation of iPBX
products.
These designs involve Motorola PowerQUICC processor cores, SDRAM,
SSRAM, CPLD/FPGA's, and DSP's, with a mix of TDM and packet switching
fabrics, using T1/E1, 10/100TX, Fiber, and Copper interfaces.

Qualifications
Bachelor's degree in Electrical Engineering or a Technologist with
the equivalent work experience
Minimum of 2 years of relevant experience
-----------------------------------------------
Experience with PowerQUICC processor cores, Xilinx FPGA/CPLDs
Experience in high speed digital design
Good writing skills

Email: info@osft.com
Fax: 416-260-5973

Opensoft Inc. is continuously hiring Java/XML Engineers for their on-going
web-based solutions project work in the financial services, technology
delivery and professional services groups of Opensoft Consulting Group Inc.

Opensoft Inc. enables our Blue-Chip and Start-Up companies to recruit for
the delivery of their E-Commerce, Internet/Intranet, OO and
Client-Server projects. Opensoft Inc. has gained recognition as being able
to define the right candidate for the right job. Unlike other
consulting companies we do not shop your resume; we will however, help you
make the right career decision. Opensoft Inc. has one of the most
prominent Java/XML/Web Solutions Integration, teams in North America.

Please e-mail a version of your resume to info@osft.com in either MS WORD or
ASCII text. Please Note: Your resume will not be forwarded to
any client without your consent. Also due to the large numbers of
exceptional candidates responding to our postings we will only contact
those which are a match on the skills required by our clients. Others will
be added to our database and will be called when a suitable opportunity
comes available.




Article: 28242
Subject: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
From: "OSFT Inc." <info@osft.com>
Date: Wed, 03 Jan 2001 15:27:43 GMT
Links: << >>  << T >>  << A >>
The Company is developing a dedicated, special purpose, intelligent platform
for the following:
Front-end to back-end e-commerce integration Data interoperability across
storage systems.
The Company believes that building an excellent company is as important as
building excellent products.  The core of any company are its people.  We
are looking for people who want a challenge.  We are looking for people who
are passionate about what they do.  We are looking for people who want to
make a difference.
The Company is a well-funded start-up that is looking to shake up the data
storage industry.  We are a hot company in a hot market.

Application Software

Requirements:

5+ years in product management role for application software.
High-level of understanding of networks and protocols.

Experience with data storage and backup/recovery solutions is a plus.

Experience with SANs or Mainframes would be a plus.
FPGA
Birth Trouble shooting
Skematic Capture
Fibre Channel
SCSI Design
VX works


Email: info@osft.com
Fax: 416-260-5973

Opensoft Inc. is continuously hiring Java/XML Engineers for their on-going
web-based solutions project work in the financial services, technology
delivery and professional services groups of Opensoft Consulting Group Inc.

Opensoft Inc. enables our Blue-Chip and Start-Up companies to recruit for
the delivery of their E-Commerce, Internet/Intranet, OO and
Client-Server projects. Opensoft Inc. has gained recognition as being able
to define the right candidate for the right job. Unlike other
consulting companies we do not shop your resume; we will however, help you
make the right career decision. Opensoft Inc. has one of the most
prominent Java/XML/Web Solutions Integration, teams in North America.

Please e-mail a version of your resume to info@osft.com in either MS WORD or
ASCII text. Please Note: Your resume will not be forwarded to
any client without your consent. Also due to the large numbers of
exceptional candidates responding to our postings we will only contact
those which are a match on the skills required by our clients. Others will
be added to our database and will be called when a suitable opportunity
comes available.





Article: 28243
Subject: Re: Partial reconfiguration using jbits
From: Phil James-Roxby <phil.james-roxby@xilinx.com>
Date: Wed, 03 Jan 2001 08:34:15 -0700
Links: << >>  << T >>  << A >>
mlms@fe.up.pt wrote:
> 
> Hi all
> I 'm writing a small program that takes two different bit files, created
> using Foundation, compares them and them generates a partial
> reconfiguration
> file that turns one into the other. Using JBits commands I am able to
> create
> that bit file, but I don't know if it is a valid bit file, when I read
> it
> using JBits.readPartial a configuration exception is thrown.
> Internal error detected in the partialBitstream
> com.xilinx.JBits.Virtex.ConfigurationException: Configuration data not
> found
> (null bitstream).
> The same thing happens using Device Simulation.
> Using the Dump command I'm able to see that there are configuration
> packets
> in the file and it has the same structure that the reconfiguration file
> used
> in XAPP153, because of that I'm not sure that my bit file is not valid.
> How can I be sure that my bit file is a valid file and how can I test it
> before send it to the FPGA.

If it can be read by JBits, then its a 'valid' file, in terms of the
internal structure, but remember its not been through any sort of DRC. 
There's not really enough info for me to go on here, but in general, you
get a configuration exception in JBits when you try to set a resource
which is outside of the legal boundaries, so if you are on an XCV50 and
you try to set a LUT at 100,100 then it'll throw an exception.  Or if
you fail to correctly instantiate a JBits object, it'll hurl too.
What I suggest you (and anyone else having JBits related problems) is to
zip up all your relevant sources, and send them over to
jbits@xilinx.com   One of our poeple can take a look at it for you. 
What you are doing is possible, I described my implementation of this
function at FCCM last year.
Phil

-- 
---------------------------------------------------------------------
 __
/ /\/  Dr Phil James-Roxby         Direct Dial: 303-544-5545
\ \    Staff Software Engineer     Fax: Unreliable use email :-)
/ /    Loki/DARPA                  Email: phil.james-roxby@xilinx.com
\_\/\  Xilinx Boulder                 
---------------------------------------------------------------------

Article: 28244
Subject: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
From: Jon Schneider <jms@geriatrix.circlesquared.cXoXm>
Date: 03 Jan 2001 16:17:19 +0000
Links: << >>  << T >>  << A >>
OSFT Inc. <info@osft.com> wrote:
> Skematic Capture

I did my first (1.2u) ASIC years ago with schematic capture when that
was the way to do it. Is this similar ?

> Birth Trouble shooting

Now I _know_ I'm completely out of touch with semiconductor technology.

        Jon

Article: 28245
Subject: Re: Question about Xilinx pins at high-frequency
From: "Pascal C." <>
Date: Wed, 3 Jan 2001 11:04:11 -0800
Links: << >>  << T >>  << A >>
Finally, I relaxed the constraints and all is well when I reduce the drive.

Also, using active-low OEs on I/O does work: after FEXP has dealt with it, the Xilinx tools are able to use the register within the IOB.  Thanks Andy!
Article: 28246
Subject: Re: Virtex and metastability
From: bob elkind <eteam@aracnet.com>
Date: Wed, 03 Jan 2001 11:36:26 -0800
Links: << >>  << T >>  << A >>
I beg to differ.

Consider three cases:

The first case is a long (or "slow") rise/fall time, monotonic asynchronous input;
where the window of metastability is large.  In this case, gain applied to the
input provides a buffered signal with a much shorter rise/fall time, and (therefore)
a much smaller metastability window.  On a monotonic signal, hysteresis (in and
of itself) provides nothing more or less than *delay*, not gain.  In any case,
whether or not the input buffer incorporated hysteresis is irrelevant to the
system's metastability failure (incidence) rate.  What matters (all other factors
being equal) is the slew rate of the incoming signal being acquired.  The signal
was originally asynchronous to the system clock, and after buffering it is still
asynchronous with respect to the system clock.

Now consider a case where the input signal has a short rise/fall time, and is
still monotonic.  In this case, an input buffer stage provides gain that is not
needed, since the rise/fall time of the buffer's output is no different than
that of the raw input.  The window of metastability is unchanged.  Since the input
is asynchronous, the delay of the input buffer (or its absence) is irrelevant.
Applying hysteresis, in and of itself, doesn't affect the metastable susceptibility
of the system.

Finally, let's consider a non-monotonic input signal.  The is the classic ratty
signal.  There is a continuous spectrum of non-monotonic behaviour, and there
is a continuous spectrum of "rattiness".  Let's vaguely define "rattiness" as a
signal characteristic exhibiting reversals of signal slewing while in the
"switching region" between defined "high" and "low" input thresholds.

Think of a runt pulse.  At one extreme of runtiness (or amplitude), the pulse
doesn't affect the output of a buffering stage.  At the other extreme of runtiness,
the input pulse provokes a solid (full-amplitude) pulse at the output of a buffering
stage.  At some point in between the two extremes, the runt pulse will provoke a
very similar runt pulse at the output of a buffering stage.  Here's the challenge
to (possibly) our closely held beliefs...  even if the buffering stage incorporates
hysteresis, there *is* an input pulse amplitude that *will* result in a run pulse
at the buffer's output, somewhere between the two extremes in the input pulse
amplitude range that yield either no output pulse or a full amplitude output pulse.
Hysteresis will change (shift) the amplitude of the input runt pulse required to
provoke a runt pulse at the buffering stage output, but the susceptibility to "failures"
from runt pulses (or "ratty" signals) is fundamentally inescapable.

This is a great opportunity for applying SPICE simulations to convince yourself of
this concept.  Build two circuits (buffer H and buffer K), one with hysteresis and
one without, but both with the same gain-bandwidth.  Drive the circuit from an input
buffer Y.  The input to Y is a primary input to the spice deck, where you specify
the the pulse width (i.e. transition timepoint).  When the pulse input to Y becomes
narrow enough, you get a runt pulse at the output of Y which is representative (in
shape, slew rate, voltage, etc.) to a real-life signal generated in your system.
This runt pulse (output Y) will be applied (alternately) to circuit K (no hysteresis)
and circuit H (with hysteresis).

For any runt pulse output you can generate from buffer/circuit K (the one without
hysteresis), you can come up with a primary input waveform for circuit H that will
provoke a (practically) identical runt pulse output, even though circuit H has
hysteresis.

You can't eliminate the susceptibility to runt pulses, or susceptibility to metastable
conditions.  You can narrow the range of input signals (i.e. range of pulsewidths
of primary input, to input of buffer Y) which will result in runt pulses and
metastable conditions -- primarily by changing the gain of the H or K.  Adding
hysteresis doesn't affect the susceptibility of the system to either runt pulses or
metastable conditions.

Use the spice simulation to "play" with gain changes, input pulse width changes, and
degrees of hysteresis.  The results are fascinating, and when you're done, you will
appreciate once again that the laws of physics really are laws of physics, and everything
is working as it should be.

Boy this is long-winded, but this characterises a mind-set-changing event that I had
to overcome some 17 years ago.  When the light turned on in my brain, I was a different
person (as an engineer, of course).

-- Bob Elkind, a humbled engineer with renewed confidence in the laws of the universe.


Ron Cline wrote:
> 
> In the interest of POE (Peace On Earth, for those who never saw Doctor
> Strangelove) ... everybody's right.  Actual implementations of
> hysteresis consequentially increases input gain because of the positive
> feedback...  (The noise immunity also certainly helps the measurement.)

Short summary:  hysteresis doesn't increase gain.  It shifts the switching point
until a magical point is reached, where gain is exactly the same as a circuit
without hysteresis. As the switching point is passed, positive feedback (i.e.
hysteresis) once again shifts the switching point to a different voltage.

You could call this increased gain (via positive feedback), but the hysteresis
completely disappears (and gain "change" completely disappears) near the
circuit's switching point.  The hysteresis simply (bimodally) changes the
switching point.  Sometimes!

-- Bob Ekind

> - RLC
Article: 28247
Subject: Fixing pins on Spartan II
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Wed, 03 Jan 2001 20:17:53 GMT
Links: << >>  << T >>  << A >>
Hi all,

Egg-chicken kind of problem. I have to give my board design out to a layout
person but I haven't yet had chance to start my FPGA work. Usually I do some
draft FPGA design and run tools at least once to fix the pins before giving
it out to do a layout but this time the schedule is really tight and if I go
this route it will be too late. This is not a very demanding design neither
in terms of complexity nor in terms of speed and I am using Spartan II
family device. Scary part is that the pins utilization is almost 100%.

Nonetheless, do you guys think that I can get away with pins fixed
beforehand without too much thought (I put my clocks on global clock lines)?


Thanks in advance,

--
============================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: 1 (613) 271-0044 ext.231
Fax: 1 (613) 271-3007
http://www.squarepeg.ca



Article: 28248
Subject: Re: driving color VGA from FPGA ??
From: Steve Nordhauser <digital@nycap.rr.com>
Date: Wed, 03 Jan 2001 20:40:36 GMT
Links: << >>  << T >>  << A >>
Wow,  am I glad I didn't invest the time and money to create a board
with those IBM RAMDACs.  Ouch.
Steve

Arrigo Benedetti wrote:

> IBM used to make some nice RAMDACs. I just checked out
> www.chips.ibm.com and it seems that they are not making them anymore.
> Another vendor is Analog Devices.
>
> Good luck,
>
> -Arrigo

Article: 28249
Subject: Re: Jedec to tms/tdi wiggles
From: Neil Glenn Jacobson <neil.jacobson@xilinx.com>
Date: Wed, 03 Jan 2001 13:27:49 -0800
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Please check this app. note for a Xilinx-supplied solution:
<br>&nbsp;<a href="http://www.xilinx.com/apps/xappsumm.htm#xapp058">Xilinx
XAPP Note Summaries</a>
<br>The accompanying software is available from here:
<br>&nbsp;<a href="ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_pc.zip"> eisp_pc.zip</a>
<p>Jon Schneider wrote:
<blockquote TYPE=CITE>Dave Vanden Bout &lt;devb@xess.com> writes:
<br>>
<br>> You can use the Xilnx software to generate SVF from the JEDEC file.&nbsp;
XESS
<br>> has tools (<a href="http://www.xess.com/downloads/xstools.exe">http://www.xess.com/downloads/xstools.exe</a>)
that will download
<br>> an SVF file into an XC9500 CPLD via the parallel port.&nbsp; You
can build your
<br>> hardware to match the circuitry of the XS95 Board
<p>Yes I have already noticed Xess and indeed came across the Webpack
<br>software through Xess's site in the first place. That was following
<br>another question you or one of your colleagues kindly answered in one
<br>of these newsgroups.
<p>It is just a shame that the information isn't forthcoming from say Xilinx
<br>or Jtag.org. Or if it is, it is too well hidden.
<p>Rest assured I do have one of your boards on my shopping list anyway
<br>but was just wondering about more of a production environment.
<p>Could you possibly explain what an SVF file is please ?
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Jon</blockquote>
</html>




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