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skitz, BUFG's are still supported. If you do not constrain the resources, the software will choose the 'best' ones in that quadrant. If you need to lock something down (like an input clk pin to an IBUFG), then the clock rules get a bit arcane. I will leave it to a software expert to explain it. The on-line handbook does discuss the primary and secondary clock pins, and the shared nature of the BUFGMUX. One advantage of using the BUFGMUX explicitly is that if you try to do something wrong, it will error out, rather than give you a poor implementation with no warning (being fixed for future releases). We had 16 clock resources, with up to eight per quadrant, and in retrospect, we should have made the implementation a little more complex to make the software simpler. Please call the hotline to get pointed to the right info, or you can do like I do, and use FPGA_editor to view the results, and make sure there are no hidden doubles or switchboxes getting inserted in the BUFG resource (which will affect the skew and timing). Any BUFGMUX/BUFG in the quadrant is as good as (identical clock H tree) to any other in that quadrant. Austin skitz wrote: > hi. > i am a new user to the virtex2 and i am having trouble finding > documentation on how to set up the clocking. here is my configuration: > i have an input clock going to an IBUFG and then to a DCM. On the DCM, > i am using the CLK0, CLK180, and CLKDV outputs. these three outputs > are going to three BUFGMUX's (i would rather use BUFG's but i am not > sure if they are still supported). my goal is to constrain the > placement so that all of the BUFGMUXs are on the same edge of the chip > (or quadrant if that is possible) along with the DCM. any assistance > would be greatly appreciated. > skitzArticle: 34001
Peter, I'll bet you a six-pack of Bass Ale that it's the Atmel programmable reset/OE pin that's backwards -- it's in reset when the FPGA wants to read it! Been there, done that, where's my t-shirt! --andy Peter Alfke wrote: > > I suspect a problem during power-up. > Both FPGA and PROM each have a sensor that decides when Vcc is high enough to > start operating. If the PROM is slower than the FPGA, then CCLK pulses will > start kicking before the PROM is ready to receive them. As a result, the > bitstream is wrong. > > I have never seen that problem with Xilinx PROMs, that's why I don't have a > ready answer. You would have to delay the FPGA's wake-up sequence somehow, to > make it as slow as the PROM. > > More deviously: > Check that the PROM output is constantly High immediately after Vcc is applied. > If it is, then you can increase the length-count value by any reasonable number > ( 100 or even 1000 ). This effectively gives the FPGA a long, even unknown, > sequence of 1s preceding the bitstream. The FPGA ignores that, but the > length-counter counts ever single CCLK tick, so you must increase the > length-count value. > > Try it, it's simple. > > PeterAlfke > > ============ > > Markus Meng wrote: > > > Hi all, > > > > concerning a prototype board serie we do have a configuration > > problem with ~ 50% of the board produced. The problem > > looks that the serial configuration in Master Mode does not take > > place the first time. An external Watchdog does reinitiate the > > configuration process ~ 1.6sec by forcing the program pin low. > > Then the Spartan-II device XC2S150 restart the configuration > > in Master Mode. Since there is no possibility the 'see' that the > > CRC for example is wrong, nothing happens the DONE-pin > > remains low. We use the ATMEL part 17LV010. Are there > > any known issues regarding this combination? > > > > In the Xilinx Tool chain I did NOT select anything special, just > > the defaults. Looking into the details with a scope I saw that the > > CCLK ~3.1 MHz. This is maybe a reasonable value. > > > > Any help would be appreciated! > > > > markus > > > > -- > > ******************************************************************** > > ** Meng Engineering Telefon 056 222 44 10 ** > > ** Markus Meng Natel 079 230 93 86 ** > > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > > ******************************************************************** > > ** Theory may inform, but Practice convinces. -- George Bain **Article: 34002
Well, I would have said that, but he gets it to work on the second attempt... Note also that I was nice and did not post: "Why the hell do you use an Atmel part, when Xilinx (now) has reprogrammable PROMs". BTW, I made a mistake in referring to lengthcount, which no longer exists on Virtex ( and Spartan-II) families. These parts now sync on a special incoming data pattern. Old habits die slowly... Peter Alfke =========================================== "Andy Peters > Peter, > > I'll bet you a six-pack of Bass Ale that it's the Atmel programmable > reset/OE pin that's backwards -- it's in reset when the FPGA wants to > read it! > > Been there, done that, where's my t-shirt! > > --andy > > Peter Alfke wrote: > > > > I suspect a problem during power-up. > > Both FPGA and PROM each have a sensor that decides when Vcc is high enough to > > start operating. If the PROM is slower than the FPGA, then CCLK pulses will > > start kicking before the PROM is ready to receive them. As a result, the > > bitstream is wrong. > > > > I have never seen that problem with Xilinx PROMs, that's why I don't have a > > ready answer. You would have to delay the FPGA's wake-up sequence somehow, to > > make it as slow as the PROM. > > > > More deviously: > > Check that the PROM output is constantly High immediately after Vcc is applied. > > If it is, then you can increase the length-count value by any reasonable number > > ( 100 or even 1000 ). This effectively gives the FPGA a long, even unknown, > > sequence of 1s preceding the bitstream. The FPGA ignores that, but the > > length-counter counts ever single CCLK tick, so you must increase the > > length-count value. > > > > Try it, it's simple. > > > > PeterAlfke > > > > ============ > > > > Markus Meng wrote: > > > > > Hi all, > > > > > > concerning a prototype board serie we do have a configuration > > > problem with ~ 50% of the board produced. The problem > > > looks that the serial configuration in Master Mode does not take > > > place the first time. An external Watchdog does reinitiate the > > > configuration process ~ 1.6sec by forcing the program pin low. > > > Then the Spartan-II device XC2S150 restart the configuration > > > in Master Mode. Since there is no possibility the 'see' that the > > > CRC for example is wrong, nothing happens the DONE-pin > > > remains low. We use the ATMEL part 17LV010. Are there > > > any known issues regarding this combination? > > > > > > In the Xilinx Tool chain I did NOT select anything special, just > > > the defaults. Looking into the details with a scope I saw that the > > > CCLK ~3.1 MHz. This is maybe a reasonable value. > > > > > > Any help would be appreciated! > > > > > > markus > > > > > > -- > > > ******************************************************************** > > > ** Meng Engineering Telefon 056 222 44 10 ** > > > ** Markus Meng Natel 079 230 93 86 ** > > > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > > > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > > > ******************************************************************** > > > ** Theory may inform, but Practice convinces. -- George Bain **Article: 34003
Todd Brown wrote: > > Hi All, > > I'm new to this group but I was wondering if anyone here knows of a > low cost FPGA or PLD. It needs to be less than one dollar in volumes > of 100K. As far as requiements go, six i/o and room for a 16 bit > timer. Depends a little on package, and Vcc/Freq/Icc targets. Some that we use for similar apps are Atmel ATF750CL - 20 registers, and down to TSSOP24 package Atmel ATF1502AS - 32 registers, and down to QFP44 package The ATF1502 allows you to bury a counter, and still use the pin as IO, or even a Pin-Latch, so you can get more logic in a finite number of macrocells. Both can be supplied factory programmed, and have << 1mA static Icc -jgArticle: 34004
Kamal Patel <kamal.patel@xilinx.com> writes: > Hello Petter, > > As I stated in my initial response the functionality > will be the same, only the GUI will change. So > Solaris support and implementation options will not > be removed. Great! I'm very happy to hear that. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 34005
I did not know Xilinx had a reprogrammable part for the S150 part. Could you tell me the part number? Thanks Dave Colson Peter Alfke wrote: > Well, I would have said that, but he gets it to work on the second attempt... > > Note also that I was nice and did not post: > "Why the hell do you use an Atmel part, when Xilinx (now) has reprogrammable PROMs". > > BTW, I made a mistake in referring to lengthcount, which no longer exists on Virtex > ( and Spartan-II) families. These parts now sync on a special incoming data pattern. > > Old habits die slowly... > > Peter Alfke > =========================================== > "Andy Peters > > > Peter, > > > > I'll bet you a six-pack of Bass Ale that it's the Atmel programmable > > reset/OE pin that's backwards -- it's in reset when the FPGA wants to > > read it! > > > > Been there, done that, where's my t-shirt! > > > > --andy > > > > Peter Alfke wrote: > > > > > > I suspect a problem during power-up. > > > Both FPGA and PROM each have a sensor that decides when Vcc is high enough to > > > start operating. If the PROM is slower than the FPGA, then CCLK pulses will > > > start kicking before the PROM is ready to receive them. As a result, the > > > bitstream is wrong. > > > > > > I have never seen that problem with Xilinx PROMs, that's why I don't have a > > > ready answer. You would have to delay the FPGA's wake-up sequence somehow, to > > > make it as slow as the PROM. > > > > > > More deviously: > > > Check that the PROM output is constantly High immediately after Vcc is applied. > > > If it is, then you can increase the length-count value by any reasonable number > > > ( 100 or even 1000 ). This effectively gives the FPGA a long, even unknown, > > > sequence of 1s preceding the bitstream. The FPGA ignores that, but the > > > length-counter counts ever single CCLK tick, so you must increase the > > > length-count value. > > > > > > Try it, it's simple. > > > > > > PeterAlfke > > > > > > ============ > > > > > > Markus Meng wrote: > > > > > > > Hi all, > > > > > > > > concerning a prototype board serie we do have a configuration > > > > problem with ~ 50% of the board produced. The problem > > > > looks that the serial configuration in Master Mode does not take > > > > place the first time. An external Watchdog does reinitiate the > > > > configuration process ~ 1.6sec by forcing the program pin low. > > > > Then the Spartan-II device XC2S150 restart the configuration > > > > in Master Mode. Since there is no possibility the 'see' that the > > > > CRC for example is wrong, nothing happens the DONE-pin > > > > remains low. We use the ATMEL part 17LV010. Are there > > > > any known issues regarding this combination? > > > > > > > > In the Xilinx Tool chain I did NOT select anything special, just > > > > the defaults. Looking into the details with a scope I saw that the > > > > CCLK ~3.1 MHz. This is maybe a reasonable value. > > > > > > > > Any help would be appreciated! > > > > > > > > markus > > > > > > > > -- > > > > ******************************************************************** > > > > ** Meng Engineering Telefon 056 222 44 10 ** > > > > ** Markus Meng Natel 079 230 93 86 ** > > > > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > > > > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > > > > ******************************************************************** > > > > ** Theory may inform, but Practice convinces. -- George Bain **Article: 34006
Hi All, I'm new to this group but I was wondering if anyone here knows of a low cost FPGA or PLD. It needs to be less than one dollar in volumes of 100K. As far as requiements go, six i/o and room for a 16 bit timer. Thanks in advance, Todd Brown tbrown@infineer.comArticle: 34007
I can understand the confusion. Xilinx has the XC18V01 reprogrammable PROM, that is only listed as compatible with the Virtex XCV150, but therefore is also compatible with the corresponding Spartan-II part. So there is no technical problem, but it looks like Marketing wants to emphasize the cheaper one-time programmable part. This is a price-perception issue, and I can see how we confuse the world. Sorry. I try to stay out of pricing issues, but Xilinx has an erasable PROM that fits the XC2S150 ( with 1,040,128 configuration bits). Peter Alfke Dave Colson wrote: > I did not know Xilinx had a reprogrammable part for the S150 > part. Could you tell me the part number? > > Thanks > Dave Colson >Article: 34008
Hello everyone, iam using virtex E device for my Design, my design has block memories its outputs are registered. even if i place the register near to the block memory, the net delay from the block memory output to the register input is 3.ns how can we redude the net delay ? Thanks in Advance, Regards, ManjunathArticle: 34009
Dave Colson wrote: > Hi, > > You might try connecting the Atmel READY pin to the Xilinx PROGRAM pin. > This guarantees that > the Atmel will hold off the Xilinx until it (the Atmel) is ready to > operate. It is suggested in the Atmel Apps. This > is the way I have it and I have had no config problems. > > Dave Colson > There's one thing I remember from using ATMEL parts a few years ago. This may be out of date but here goes: What used to happen is that the first byte of data *and the RESET polarity bit* was loaded into the output shift register by the power-on reset logic. In fact after changing the RESET polarity a power cycle was required to put the new value into the NV cells. What I found was that with a slow ramping VDD this power-on process failed for the first few FPGA loads after changing the EEPROM's contents & the first byte could be anything from 0->ff. ATMEL admitted this was a bug & were planning to fix it on an ``A'' rev part. Now this was with 4K series parts so if a Virtex/SpartanII bit stream has a long enough 1's preamble it shouldn't matter but ....Article: 34010
Jim Granville wrote: > Todd Brown wrote: > > > > Hi All, > > > > I'm new to this group but I was wondering if anyone here knows of a > > low cost FPGA or PLD. It needs to be less than one dollar in volumes > > of 100K. As far as requiements go, six i/o and room for a 16 bit > > timer. > > Depends a little on package, and Vcc/Freq/Icc targets. > > Some that we use for similar apps are > Atmel ATF750CL - 20 registers, and down to TSSOP24 package > Atmel ATF1502AS - 32 registers, and down to QFP44 package > The ATF1502 allows you to bury a counter, and still use the pin > as IO, or even a Pin-Latch, so you can get more logic in > a finite number of macrocells. > Both can be supplied factory programmed, and have << 1mA static Icc > > -jg Or the Xilinx XC9536XL-VQ44. $0.99 at 25-off so 100K pieces is going to be much cheaper. 36 Macrocells, 34 I/Os. Not as low power as the Atmel or CoolRunner parts & they are JTAG (re)programmable. Design s/w is free.Article: 34011
The apparent low speed and complexity of your design affords you many options all of which can work. So other factors may help you decide which componant to use such as power, package, security of design, availability of tools, familarity, etc. A few hints are to resynchronize your inputs to the master system clock (10MHz) and use them as enables to flip-flops, don't directly connect them to the clock pins as intuitive as this sounds. This is standard synchronous design stuff. If you remember one thing from this message is that the clock pin of a flop goes only one place, the global clock net, thats it. For this kind of small stuff, the Altera free tool set would do nicely. If the speed is slow enough, use the printer port, you can stay out of the guts of the PC, and even get an interrupt if you want one I think. "Jay" > "Ali" <aelmousa@yahoo.com> wrote in message > news:4eede02c.0108090350.1cc58020@posting.google.com... > > Hello all, > > > > I need to fulfil the following requirements and I would appreciate any > > help in deciding whether the use of an FPGA will be feasable. > > > > I have 40 sensors whose outputs are pulses but with a slow repitition > > rate. > > Each 4 (four) of these pulses i.e. from four different sensors, are > > related to a specific event. What I need is to capture accurately the > > time difference between the arrival of these pulses in each group. > > > > I am thinking of using a very fast free running reference counter and > > latches. I will let the pulses act as a strobe to capture the output > > values of the counter. By comparing the values in the latches I can > > calculate the time difference between the arrival of the pulses. > > > > By my calculation, I need at least a 24 bit counter and thus 24 bit > > latches. Also, I will need a precise 10Mhz clock. > > > > Thus I will require 40 (forty) 24 bit latches, and a free running 24 > > bit binary counter. I wil need to be able to read all the output of > > the latches. Also, 40 different inputs should be available. > > > > The question is: Is there a single FPGA or CPLD that has the > > capability to implement the above? If no, how many will I need and > > which types and makes? > > > > Also, will it be easy to connect the FPGA to a PC bus and control it? > > I will also probably need a link to hardware interrupts to notify the > > PC of the availability of data to be read from the latches. > > > > Any help or better ideas to implement the above will be greatly > > appreciated. > > > > > > Thank You > > > > AliArticle: 34012
Hello All, I have a very conservative customer for whom I want to use an fpga in place of an asic. Part of the chip needs to be "instant on" so I'm thinking about Quicklogic and Actel. The design is too flip flop intensive for PLD architectures like Coolrunner, etc. The main challenge of the job is to prove that the design is verified. They are uncomfortable with the idea that everything is randomized with each small change of the design. It would go a long way to convincing them if I could directly control the mapping, placement and routing in the fpga design. My experience is with the Xilinx floorplanners and chip editors that allow you to view and control everything. Does anyone have experience with the floorplanner/chip editor tools for Actel or Quicklogic? Is it possible to gain fine control of these architectures through source constraints or floorplanning? With time I will educate these guys about techniques such as synchronous design, static timing analysis and testbenching but for now I just want to be able to control the layout. -- Pete Dudley Arroyo Grande SystemsArticle: 34013
System Generator allows the dsp analyst to simulate with the xilinx coregen macros in their familiar simulink environment. Generally we throw out the systems that they generate because they are not really practical to just synthesize and drop into a chip but at least filter cores are fully specified. What SG really lacks to make it a practical design entry tools are the complete unsim library of components. Thinks like flip flops with clock enables are missing. -- Pete Dudley Arroyo Grande Systems "Robert Myers" <rjmyers@raytheon.com> wrote in message news:3B73D97B.F6B61804@raytheon.com... > Hi; > > I'd like to find out if anyone has been using this > tool suite from Xilinx, along with Matlab/Simulink and > either Alliance or Foundation tool suite from Xilinx. > > There are some engineers that I work with that have > shown some interest in this package and I'd like to > hear/relay any current experiences that others have > had to my users. > > Thanks, > BobArticle: 34014
If you search using google or altavista, you can find quite a few designs in ahdl to learn from. Also search the newsgroups history using google. Abhimanyu Rastogi wrote: > > Thx again.... for all the suggestions.... i'm sure they'll help me a > lot.... and yeah....i like the way u use humour....with the words of > knowledge... > > Well, i'm just a 2nd yr student....and i love to take challenging jobs..... > and in engineering u know that nobody gives up...... -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 34015
Todd Brown <tbrown@infineer.com> wrote in message news:19c0d01d.0108101251.3af5b2ce@posting.google.com... > Hi All, > > I'm new to this group but I was wondering if anyone here knows of a > low cost FPGA or PLD. It needs to be less than one dollar in volumes > of 100K. As far as requiements go, six i/o and room for a 16 bit > timer. > > Thanks in advance, > Todd Brown > tbrown@infineer.com Altera's solution is the MAX 3032A. Quantity 1 pricing is $1, so for 100K units you'll do even better. Design software is free and the devices are JTAG programmable.. The details are here: http://www.altera.com/products/devices/max3k/m3k-index.html -Pete-Article: 34016
You will find some relevant observations about this at http://www.fpgacpu.org. The real short version is that the PCI bus interface is so slow relative to the speeds of the cpu and accelerator that it usually isn't worth adding an accelerator if the interface is via the PCI bus. But if the accelerator and the cpu chip are directly connected (possibly by the AMD HyperTransport bus) things improve considerably "Jason" <jhmorris47@hotmail.com> wrote in message news:97fd5b24.0108070324.58067f8@posting.google.com... > What is the best reconfigurable PCI processor board to use as a > computation accelerator? > > Jason MorrisArticle: 34018
Allan Herriman wrote: > > On Wed, 08 Aug 2001 13:22:48 +0100, Gary Cook <gc@sonyoxford.co.uk> > wrote: > > >I've read the previous threads relating to source control for > >FPGA designs (RCS,CVS,CC etc. etc..) but would like > >to discuss more of a general topic around this.... > > [snip description of the sort of thing I do in Clearcase at least a > few times each week.] > > You set up a "view" which contains the appropriate versions of each > element. When you are happy with your design, you can label all the > elements (after you've checked them in, of course), and then you can > always get that exact set of elements back by refering to them by that > label. > > With Clearcase under NT, you can map a view to a drive letter. For > example, on my laptop, I have my Z: drive looking at the latest > version of everything. My Y: drive looks at my development branch for > the particular set of files I'm working on at the moment. When I'm > finished, I'll merge them to the main branch and label the lot. Oh, > these particular files are shared by an international development > team, and Clearcase synchronises everyones views correctly. Well, > most of the time, anyway. > > It's expensive, but if you want to play with the big boys... > > Regards, > Allan. Allan, I would not recommend Clearcase to anyone working on FPGAs. Clearcase has a lot of capabilities (and added complexities) that are just not needed by someone doing FPGA work. To be honest, I am not sure it is needed by anyone doing software work. But if you are a carpenter, you use a lot of fancy wood in your tools. If you are a machinist, you use a lot of fancy metal tools in your work. Software people tend to use a lot of fancy software tools in their work that are often a matter of guilding the lily. I have used PVCS in the past and it worked very well for both software and hardware. I expect that a new user would find this much easier to use than an overly complex tool like Clearcase. The way we worked in PVCS was to add labels to mark the exact version of every file used in a make. Then to repeat the make, the label was used as a reference. This tool was quite powerful enough for all of our needs and still was relatively easy to use. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 34019
> The way we worked in PVCS was to add labels to mark the exact version of > every file used in a make. ... I should have put that on the list when we were dreaming about great FPGA tools. Thanks for the reminder. I'd like a set of tools that are make friendly. I'd like to be able to make a few edits (text and/or GUI, my choice) and then say "make" and have everything work. That means I have to know what files each tool reads and which ones it writes. And where all the magic parameters are hidden so I can check to see if any of them have changed so that steps have to be rerun. This also means that it is not reasonable to have any step in the normal make-new-bits tool chain be GUI only. -- These are my opinions, not necessarily my employeers. I hate spam.Article: 34020
"Dave Feustel" <dfeustel1@home.com> wrote in message news:1jad7.235147$mG4.108848519@news1.mntp1.il.home.com... > You will find some relevant observations about this > at http://www.fpgacpu.org. The real short version is > that the PCI bus interface is so slow relative to the > speeds of the cpu and accelerator that it usually > isn't worth adding an accelerator if the interface > is via the PCI bus. But if the accelerator and > the cpu chip are directly connected (possibly > by the AMD HyperTransport bus) things improve considerably > > "Jason" <jhmorris47@hotmail.com> wrote in message > news:97fd5b24.0108070324.58067f8@posting.google.com... > > What is the best reconfigurable PCI processor board to use as a > > computation accelerator? > > > > Jason Morris I posted a rather long reply on this subject to the FPGA CPU News web site, www.fpgacpu.org. Jan Gray, Gray Research LLCArticle: 34022
Block RAMs are going to be your limiter. The access times are just too slow without having output registers available in the Block RAM. If your memory isn't large, consider CLB SelectRAMs. If you don't need most of your BlockRAMs, duplicate the RAM - both are written at the high speed but the reads are split for odd-cycles in one RAM and even cycles in the other. A 2:1 mux gives you the high, pipelined speeds. Twice the memory - ouch. Manjunathan wrote: > Hello everyone, > > iam using virtex E device for my Design, my design has block memories its outputs are registered. > > even if i place the register near to the block memory, the net delay from the block memory output to the register input is 3.ns > how can we redude the net delay ? > > Thanks in Advance, > > Regards, > > ManjunathArticle: 34023
Dave Feustel wrote:
> The real short version is
> that the PCI bus interface is so slow relative to the
> speeds of the cpu and accelerator that it usually
> isn't worth adding an accelerator if the interface
> is via the PCI bus.
This is often, but not necessarily true. Accelerator architecture
totally depends on your application. This is exactly what Philip
meant by "how long should a piece of string be". Not ridicule,
just maybe a little drier wit than we're used to...
If your application depends on lots of back-and-forth
between the host and the card in its core kernel, PCI is usually
a barrier. Many early research projects in this field found this
out the hard way. It's not the bandwidth that matters in such
cases, it's the latency, the round-trip time for a single operation.
PCI, especially as implemented in modern PCs and workstations,
can be very bad at that. Mark Shand gave an excellent and
most useful paper about this at FCCM '97, that anyone using PCI
must study:
Laurent Moll and Mark Shand. Systems performance measurement on
PCI Pamette. In FPGAs for Custom Computing Machines
(FCCM'97). IEEE, April 1997.
http://www.research.compaq.com/SRC/staff/shand/bib.html
If, on the other hand, your app is a self-contained kernel that
grinds away mostly on its own, PCI can be fine. Often signal
processing apps are like this, with the signal I/O direct to
the card.
I believe a very big win for reconfigurable computing is for
apps that demand lots of parallel memory bandwidth, since the
processor-memory bottleneck is so fundamental to conventional
computing. I'm working with a project at Oregon Graduate Institute
lately to develop a neural network accelerator. In our case, it's all
about memory bandwidth. I/O to/from the host is orders of
magnitude less. We're planning a PCI card with as many SDRAM DIMMs
as we can hook up to some FPGAs for them to grind away on matrix-
vector multiplies in parallel at 100 MHz. PCI will just control
and program the card, and feed inputs and collect results at a
lazy and latency-insensitive pace.
So tell us more about your application, and maybe we can give you
better advice.
--Mike
Article: 34024On Fri, 10 Aug 2001 18:01:18 -0600, "pete dudley" <padudle@spinn.net> wrote: >Hello All, > >I have a very conservative customer for whom I want to use an fpga in place >of an asic. Part of the chip needs to be "instant on" so I'm thinking about >Quicklogic and Actel. The design is too flip flop intensive for PLD >architectures like Coolrunner, etc. > >The main challenge of the job is to prove that the design is verified. They >are uncomfortable with the idea that everything is randomized with each >small change of the design. It would go a long way to convincing them if I >could directly control the mapping, placement and routing in the fpga >design. > >My experience is with the Xilinx floorplanners and chip editors that allow >you to view and control everything. Does anyone have experience with the >floorplanner/chip editor tools for Actel or Quicklogic? Is it possible to >gain fine control of these architectures through source constraints or >floorplanning? Dunno about Actel, but the last time I looked QuickLogic easily allowed you to place I/O cells (of course) and flip-flops explicitly in various ways - synthesis constraints, cloning of a previous P&R run, the usual stuff. OTOH I don't think there's any way to get identical routing, nor identical use of combinational logic resources, from one P&R run to the next if there is even a tiny source design change, although successive P&R runs with exactly the same parameters will always yield identical results. Do they have a graphical floorplanner yet? I haven't checked recently - it's a while since I did a QuickLogic design in anger. Their tech support folk are usually pretty responsive. As you say, time to get your client to wise up, or perhaps, pay you to get hold of some equivalence checking tools :-) Jonathan Bromley
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