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Hi... well i suppose the floor planning of the slices within a CLB is driven by the fact that they were going to have two carry chains through it... so they put two this side & two that side... other wise why not all four in a column...? Ciao, Nitin. Neil Franklin <neil@franklin.ch.remove> wrote in message news:<6ulmhefodz.fsf@chonsp.franklin.ch>... > ndeshmukh@yahoo.com (nitin) writes: > > > Anybody have any ideas why Virtex II CLB has two carry chains passing > > through it linking two slices and each and propagating in columns from > > top to bottom...? > > > > Why didn't they link all fourslices in just one chain and joined CLBs > > in one column together and so on in different columns... > > Well this is spaeculation (but well founded). > > In the original Virtex there ae 2 slices and also 2 carry chains, > each going CLB to CLB taking only one slice per CLB. > > Studying the info in XAPP151 is becomes obvious that the actial > transistors are layed out in an "butterfly" configuration, with the 2 > slices left and right of the routing! > > Sort of like this: > > > .----|----|||||----|----. > | .--|--. ||||| .--|--. | > | | C | ||||| | C | | > | `--|--' ||||| `--|--' | > | Slice 1 ||||| Slice 0 | > | | ||||| | | CLB > | | ||||| | | > -----|-----||------|----- > -----|-------|-----|----- > -----|------|||----|----- > -----|-----||------|----- routing - and | > -----|-------||----|----- > -----|----||-------|----- > | | ||||| | | > `----|----|||||----|----' > carry1^ ^carry0 > > > So having carry going through both slices would require it to meander > through the chip, massively increasing distance and so slowing it down. > > I suspect Virtex-2 to have 2 slices each side of routing, so I assume > this to also apply there. > > > > It would be nice if some one with some insight into this matter can > > shed some light on it... > > Hope it helped.Article: 36551
In Altera's Apex20K devices with speed grades -1X and -2X there is a PLL integrated. But how about the other devices? Are there also PLLs inside which are just not operational within the specifications, but still might work within lower limits? And how are the power-pins for the PLL treated?Article: 36552
Hi, srinas wrote: > Dear All, > I have to implement a Reed Solomon Encoder and a convolutional > Interleaver. > Could anybody send me some examples for a (208,188)or DVB standard RS > coder (only the encoder) and the Interleaver. > > Note: > The link > http://www.fokus.gmd.de/research/cc/mobra/products/fec/content.html > > is unavailable now. > Does anybody know where it is know? Try this: http://www.fokus.gmd.de/research/cc/mobis/products/fec_old/content.html -- EdwinArticle: 36553
You could extend the idea with a log floor and ceiling functions; or, put
another way, the floor is the log rounded down and the ceiling the log
rounded up.
-- purpose: computes ceil(log2(n))
function log2ceil (n : integer) return integer is
variable m, p : integer;
begin
m := 0;
p := 1;
for i in 0 to n loop
if p < n then
m := m + 1;
p := p * 2;
end if;
end loop;
return m;
end log2ceil;
-- purpose: computes floor(log2(n))
function log2floor (n : integer) return integer is
variable m, p : integer;
begin
m := -1;
p := 1;
for i in 0 to n loop
if p <= n then
m := m + 1;
p := p * 2;
end if;
end loop;
return m;
end log2floor;
Article: 36554Alan Fitch wrote: > > In article <3BEE8C3D.CF9EBE7D@iprimus.com.au>, Russell Shaw > <rjshaw@iprimus.com.au> writes > >Hi all, > > > >I got this counter from: > > http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlexmp.html > > > >Does this get synthesized as a ripple counter, or synchronous > >counter? Is it tool/technology dependant? > > > >If i wanted to make something using T flip-flops, do you make > >a separate entity/architecture just for a T flop and use that, > >or are there easier ways? > > > > > >LIBRARY ieee; > > USE ieee.Std_logic_1164.ALL; > > USE ieee.Std_logic_unsigned.ALL; > > ENTITY cntrnbit IS > > GENERIC(n : Positive := 8); > > PORT(clock, reset, enable : IN Std_logic; > > count : OUT Std_logic_vector((n-1) DOWNTO 0)); > > END cntrnbit; > > > > ARCHITECTURE v1 OF cntrnbit IS > > SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0); > > BEGIN > > > > PROCESS > > BEGIN > > WAIT UNTIL rising_edge(clock); > > IF reset = '1' THEN > > count_int <= (OTHERS => '0'); > > ELSIF enable = '1' THEN > > count_int <= count_int + 1; > > ELSE > > NULL; > > END IF; > > END PROCESS; > > count <= count_int; > > END v1; > > It is a synchronous ripple counter with a synchronous reset and a > synchronous enable. I assume that means ripple-carry to the flip-flop D inputs, rather than a ripple clock. The reason i asked is that i've seen a bit of conflicting naming of counters on the web. > It should synthesise fine, though most people in this group would use > numeric_std for arithmetic rather than std_logic_unsigned. Also you Unless there's tristate gates, i now just use numeric_bit. I just got the counter example off the web. > shouldn't really need the null; branch in the if, as you know that you > are synthesising flip-flops and they have memory. Thought so... > Therefore, I would write > > library IEEE; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity cntrnbit is > generic(n : positive := 8); > port (Clock : in std_logic; > Reset : in std_logic; > Enable : in std_logic; > count : out std_logic_vector( n-1 downto 0) ); > end cntrnbit; > > architecture v1 of cntrnbit is > signal count_int : unsigned(n-1 downto 0); > begin > process > begin > wait until rising_edge(clock); > if reset = '1' then > count_int <= (others => '0'); > elsif enable = '1' then > count_int <= count_int + 1; > end if; > end process; > count <= std_logic_vector(count_int); > end; > > On your second question, is it tool/technology independent, the answer > is maybe! It should be OK with most tools, except Altera Max+PLUS II > doesn't support numeric_std, so your original code would be better than > mine (!). Maxplus2 baseline doesn't compile vhdl, so i'm doing it with leonardo. Despite the user-interface bugs, leonardo-spectrum seems to be quite good at synthesizing/optimizing (its vhdl-93). > Secondly, not all FPGAs support synchronous resets built in to the logic > blocks, so you may find you use extra resources to implement gating to > support the synchronous resets. > > kind regardsArticle: 36555
Hi all,
I've got funny problems of code like this not working well
in the chip (acex 1k30 with 5MHz clock).
When the state machine enters state 2 and gets to <1>, then
ptr_en<='1'. Can i assume the counter at <2> will be clocked
in advance of ptr_en being tested at <3> ? I don't know
what to assume about the closeness of timing between the
counter clock <2>, and the state machine clock <4>.
Is there a way of keeping the clocks closely aligned? How
do you specify to use a global clock path from within
vhdl code? (i'm using leonardo)
TIA
library ieee;
use ieee.numeric_bit.all;
entity host is
port(
reset: in bit;
clk: in bit);
end host;
architecture arch of host is
subtype stype is integer range 0 to 2;
signal state,next_state: stype;
signal ptr_reset,ptr_en: bit;
signal ptr: integer range 0 to 16;
begin
ptr_cntr:
process
begin
<2> wait until clk'event and clk='1';
if ptr_reset='1'
then
ptr<=0;
<3> elsif ptr_en='1'
then
ptr<=ptr+1;
end if;
end process;
host_proc:
process(state,ptr)
begin
report "Ans= " & integer'image(ptr);
case state is
when 0=>
ptr_reset<='1'; -- reset ptr
ptr_en<='0';
next_state<=1;
when 1=>
ptr_reset<='0';
ptr_en<='0';
next_state<=2;
when 2=>
if ptr<16
then
<1> ptr_en<='1'; -- inc ptr
next_state<=1;
else
next_state<=0;
end if;
end case;
end process;
state_proc:
process(reset,clk,next_state)
begin
if reset='1'
then
state<=0;
<4> elsif clk'event and clk='1'
then
state<=next_state;
end if;
end process;
end arch;
Article: 36556Xilinx has added a neat feature to the floorplanner, letting you see a top or bottom package view of the I/O pins, rather than just the die view: http://www.xilinx.com/ise/entry/fp_techtip.htm Which should help with the usual "is it cavity up, or cavity down?" pinout mirroring confusion. BrianArticle: 36557
Russell Shaw wrote: > > Hi all, > > I compiled a vhdl design with leonardo/maxplus2 into an acex 1k30 > device, and found that as well as the normal 3.3V outputs, there > were also some pulses at 1.5V and 0.3V. The pins are unloaded. > The signals come from a bit of code i've been trying to debug. > Can tools let these kinds of conflicting designs happen without > warnings? > > There's no tristate buses or gates in the design, and only one > clock. Russell, The only time I've seen this sort of output is when the device has been damaged. Do you use any sort of EMC protection when working with the devices? I don't think you'll ever get this sort of output from logical conflict within the chip, the tools shouldn't finish a build if there are internal conflicts. Have you tried Altera's Baseline Quartus? I've an altera subscription so have the full tools but have found Quartus much easier to use than Maxplus2 with the Acex devices. Nial.Article: 36558
Hi all, Russell Shaw <rjshaw@iprimus.com.au> wrote: > Is there a way of keeping the clocks closely aligned? How > do you specify to use a global clock path from within see below [..] > <2> wait until clk'event and clk='1'; I wouldn't use this in synthesizeable code. This is eqivalent to process(Clk) and leed to synchronous FF. [..] > when 2=> > if ptr<16 > then > <1> ptr_en<='1'; -- inc ptr > next_state<=1; This is a Mealy description in a mainly Moore automate. First place to get problems, but should do in this case.. > state_proc: > process(reset,clk,next_state) This is your problem. If you want to sysnthesize your code, you've got two [1] kinds of proces: one for Logik and one for Register. If you want to get Register, your process should be sensitive to Clk and Reset, if you want to get logik, you should be sensitive to every signal that effects the signals changed during the process. Mixing both styles like your process creates latches. Your code mixes synch. FF and asynch Latches (I wonder, that you get no errors or warnings during synthesis) something you should use _very_ carefully. bye Thomas [1] actually two an a half, because sometimes you want Latches. -- Thomas Stanka BC/EMD4 Space Communications Systems Bosch SatCom thomas.stanka@de.bosch.comArticle: 36559
Nial Stewart wrote: > > Russell Shaw wrote: > > > > Hi all, > > > > I compiled a vhdl design with leonardo/maxplus2 into an acex 1k30 > > device, and found that as well as the normal 3.3V outputs, there > > were also some pulses at 1.5V and 0.3V. The pins are unloaded. > > The signals come from a bit of code i've been trying to debug. > > Can tools let these kinds of conflicting designs happen without > > warnings? > > > > There's no tristate buses or gates in the design, and only one > > clock. > > Russell, > > The only time I've seen this sort of output is when the > device has been damaged. Do you use any sort of EMC > protection when working with the devices? Its going better now. I had some particularly crappy code that involved counters inside of state-machines. Trying to get a state-machine to control an external counter now. > I don't think you'll ever get this sort of output from > logical conflict within the chip, the tools shouldn't > finish a build if there are internal conflicts. > > Have you tried Altera's Baseline Quartus? I've an > altera subscription so have the full tools but have > found Quartus much easier to use than Maxplus2 > with the Acex devices. If its the web-edition thing, i don't think it does the acex devices: http://www.altera.com/products/software/sfw-quarwebmain.html BTW, i've never bothered to do any routing or timing constraints, because i've only just got to the stage of understanding vhdl->hardware, and i really couldn't think of anything that needed timing done when the clock was only 5MHz. However, i think there might be a clock-alignment problem somewhere. Think its time to go thru the maxplus2 floor-plan help files again...Article: 36560
Thanks all the response to my former question of converting integers to std_logic. Here suggestions are needed on how to convert one fixed-point number into another customized fixed-point data format, for instance, Suppose we have a signed fixed-point number A (mA, expA), where width(A) = mA+expA+1. Now we need to convert A into format B(mB, expB), where width(B) = mB+expB+1. note that mA, expA represent the bit width of the mantissa and exponent of number A respectively, and mB, expB base on the same rule. the data width of A and B would probably be different. Is there mature vhdl code to perform this kind of conversion? Thanks very much in advance! -- Jianyong Niu -------------------------------- Rolls-Royce UTC ACSE, Univ of Sheffield B20 Amy Johnson Building Mappin St. Sheffield S1 3JD, UK Tel: +44 (0)114 2225236 Fax: +44 (0)114 2225138 Email: jyniu@acse.shef.ac.ukArticle: 36561
I'd be interested, but I'd suggest maybe an enhanced version like at http://apollo.spaceports.com/~bodo4all/index.htm. Anyone else ever tried Mandelbrot sets on a ZX81? http://www.hanssummers.com/computers/mandelbrot/ ------------------ Hans Summers http://www.HansSummers.Com "McMeikan" <mcmeikan@touch88.com.au> wrote in message news:3BEC9A9B.2D0EA6EB@touch88.com.au... > I recently had the link > http://www.howell1964.freeserve.co.uk/ZX81/ZX81_FPGA/ZX81_FPGA.htm > pointed out to me, as I love the ZX81 and happen to have a bag of the > XC3042 used to replace the ULA in this design, I am thinking of getting > some boards made and putting together some machines. > > Is there much interest? Obviously the more the cheaper. I am in > Australia but postage of the PCB should not be too expensive. > > I have not started on this yet, but once I get some more info it should > not take long at all and having some feedback from others interested > will help me to scale the cost of making boards down. > > cya, Andrew... >Article: 36562
In article <3BEFB55C.B50020F0@iprimus.com.au>, Russell Shaw
<rjshaw@iprimus.com.au> writes
<snip>
>>
>> It is a synchronous ripple counter with a synchronous reset and a
>> synchronous enable.
>
>I assume that means ripple-carry to the flip-flop D inputs, rather
>than a ripple clock. The reason i asked is that i've seen a bit of
>conflicting naming of counters on the web.
>
Sorry, the word "ripple" was a complete mistake (whoops!). The carry
chain will be implemented by the synthesis tool as appropriate. I must
be suffering from Monday morning effect
<snipped the rest>
regards
Alan
P.S. Using Spectrum, you normally find that the tool says "that's a
counter", and if you've got the license for the graphical viewer, you
see a big box labelled as a counter.
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 36563Russell, You must enjoy dangerous living .... And, the inductance of the flip chip packages is 5 to 8 times less than that of the wire bonded packages as there are no wires, just hundreds and hundreds of tiny solder balls over the entire top surface of the die connecting to ground and Vcc's. Austin Russell Shaw wrote: > pete dudley wrote: > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > > tantalums. > > > > We use terminated differential signalling for the high speed stuff if > > possible to cancel the ground bounce and use slew rate control on the rest. > > > > On the highest end of the switching spectrum the ground/power planes help > > you and my guess is that 100pF or smaller chip caps do nothing for you. > > > > Once we built some multiprocessor boards that ran about 150MHz but the caps > > were bad so we removed all of them. The boards ran fine without any > > decoupling. I'd like to try that experiment again with high speed fpga's. > > > > I like Austin's idea of tuning the caps to the operating frequency. > > With *thin* layers (such as in 8 layer boards etc), all the caps > can be left off except one electro per board. The VCC and GND planes > must be adjacent to provide very low planar transmission line > impedance (lumped capacitance is meaningless at fast edges). > > A bit of track to bypass caps and vias hardly matters relative > to the inductance in many internal bond wires.Article: 36564
Austin F, As in shipments of parts? 2V40, 2V1000, 2V3000, 2V4000, 2V6000 .... Maybe someone didn't get their order in on time? Austin L Austin Franklin wrote: > Peter, what EXACTLY do you mean by "people are receiving"??? Could you > please elaborate? > > "pete dudley" <padudle@spinn.net> wrote in message > news:tuoaa680e35ocb@corp.supernews.com... > > People here in Albuquerque are receiving their XC2V6000CES parts but > forget > > about the XC2V10,000 parts. I think Xilinx has given up on doing them > until > > the next process shrink. > > > > -- > > Pete Dudley > > > > Arroyo Grande Systems > > > > "Austin Franklin" <austin@dark98room.com> wrote in message > > news:tuo027tbr1fn64@corp.supernews.com... > > > Hi, > > > > > > What is the largest Virtex 2 part that anyone physically has in hand? > > > > > > What promises have you received for delivery of parts? > > > > > > I have a client who wants to use the large V2 parts (6000), but we can't > > get > > > a consistent answer from the distributor WRT delivery. I got VERY badly > > > burnt last year with promises for V3200 delivery that never > > > materialized...so I am leery of making any commitments to clients about > > > parts that I don't have in hand. > > > > > > Any info would be appreciated. > > > > > > Thanks! > > > > > > > > > > > > >Article: 36565
Markus, Altera has patents regarding the use of lasers to trim out, and select redundancy. I suspect that if the PLL isn't mentioned, it has been 'disabled'. Oh, as for the power pins, the answer is "carefully." http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf Austin Markus Fras wrote: > In Altera's Apex20K devices with speed grades -1X and -2X there is a PLL > integrated. > But how about the other devices? Are there also PLLs inside which are just not > operational within the specifications, but still might work within lower limits? > And how are the power-pins for the PLL treated?Article: 36566
I really hope we get somewhere, I have been downloading like mad with some
files giving trouble and the odd dead links.
It seems as if all the features have not been brought together, indeed it seems
as if some coding needs to be done so it might not be the swift job I thought
:(
Will probably wirewrap up a test unit and try out some of the stuff I have
downloaded and see what happens, I am a bit new at VHDL and its cousins so it
may be a bumpy road.
cya, Andrew...
Hans Summers wrote:
> I'd be interested, but I'd suggest maybe an enhanced version like at
> http://apollo.spaceports.com/~bodo4all/index.htm. Anyone else ever tried
> Mandelbrot sets on a ZX81? http://www.hanssummers.com/computers/mandelbrot/
>
> ------------------
> Hans Summers
> http://www.HansSummers.Com
>
> "McMeikan" <mcmeikan@touch88.com.au> wrote in message
> news:3BEC9A9B.2D0EA6EB@touch88.com.au...
> > I recently had the link
> > http://www.howell1964.freeserve.co.uk/ZX81/ZX81_FPGA/ZX81_FPGA.htm
> > pointed out to me, as I love the ZX81 and happen to have a bag of the
> > XC3042 used to replace the ULA in this design, I am thinking of getting
> > some boards made and putting together some machines.
> >
> > Is there much interest? Obviously the more the cheaper. I am in
> > Australia but postage of the PCB should not be too expensive.
> >
> > I have not started on this yet, but once I get some more info it should
> > not take long at all and having some feedback from others interested
> > will help me to scale the cost of making boards down.
> >
> > cya, Andrew...
> >
Article: 36567Hi Anon7864, why do you use a state machine ? Just sample the input signals A and B. Call them Sig_A and Sig_B. Delay Sig_A and Sig_B by one clock. Call them A_Delayed and B_Delayed. Use the following combinatorial process: DirectionProc: process (Sig_A, Sig_B, A_Delayed, B_Delayed) begin CountEnable <= (A_Delayed XOR Sig_A) XOR (B_Delayed XOR Sig_B); Direction_Up <= A_DELAYED XOR B_DELAYED; Error <= (A_Delayed XOR Sig_A) AND (B_Delayed XOR Sig_B); end process; The signals CountEnable and Direction_Up can be used to control a counter. Error shows that something is wrong with the input signals. Its very simple. -Manfred anon7864 <anon7864@hushmail.com> schrieb in im Newsbeitrag: 385a6ee1.0111071641.6fe7244b@posting.google.com... >Article: 36568
"#BASUKI ENDAH PRIYANTO#" <PH892987@ntu.edu.sg> schrieb im Newsbeitrag news:8D5C8824989A21458FFF1C3CE9902036058AF145@mail12.main.ntu.edu.sg... > Dear all, > > My circuit need various frequency clock. Is it common to built Clock > Multiplier ? Depends on the application. In general its easier to distribute a low speed clock on the PCB and to multiply it inside the FPGA. > I think it is easier to built clock divider rather than clock > multiplier. Yes. > For examples, My circuit need clock source 60 MHZ and 80 MHz, Therefore So just use a 80 MHz clock and generate a clock enable with 3/4 duty cycle. This gives you 60 Mhz too. -- MfG FalkArticle: 36569
Russell Shaw wrote: > > If its the web-edition thing, i don't think it does the acex devices: > http://www.altera.com/products/software/sfw-quarwebmain.html You're right, Acex support's just appeared in the last edition of Quartus, so the web version should support it fairly soon. > BTW, i've never bothered to do any routing or timing constraints, > because i've only just got to the stage of understanding > vhdl->hardware, and i really couldn't think of anything that > needed timing done when the clock was only 5MHz. You should be able to add a 5MHz clock constraint easily, although unless you've written code with 30 odd levels of logic I'm sure your design should work OK. > However, i > think there might be a clock-alignment problem somewhere. There shouldn't be. If you've used a global clock input pin for your clock they guarantee set up and hold times from egister to register. it's then just a matter or making sure you're writing good synchronous code. > Think its time to go thru the maxplus2 floor-plan help files again... You shouldn't have to worry about the floor planner at 5MHz. I'd worry about the front end, ie your design and code first. You should only have to resort to the floor planner if you're really pushing the limits of the FPGA. Nial.Article: 36570
There are thousands of ways to design any one function. Some people like state machines, some like algorithms, some like gates, some like counters. Wasn't original issue that he's "trying to deduce the minimal sampling rate?" While I provided a design alternative, it addressed the specific issue of sampling; you don't have to sample based on the fastest change between two counts (like under shock or other impulse conditions) but instead on a much longer average. Does use of your signals address the issues in the original post? I can see where one might monitor the error signal and get a value empirically, but other than that I can't see that the new approach addresses the issues. Empirical values are difficult to rely on sometimes.Article: 36571
Hi Austin, Can you give a hint as to quantity of each? Hundreds, a half dozen... What packages? As far as the 3200 goes, we ordered and were given a delivery date well within our schedule...but were later told that the part was not available...after we were done with the design! I can tell you the story off line if you like. As a note, no user has actually answered my question as to whether they have seen an XC2V...only one "speculation". That makes me nervous. Austin "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3BEFF38C.C6ABABAD@xilinx.com... > Austin F, > > As in shipments of parts? > > 2V40, 2V1000, 2V3000, 2V4000, 2V6000 .... > > Maybe someone didn't get their order in on time? > > Austin L > > Austin Franklin wrote: > > > Peter, what EXACTLY do you mean by "people are receiving"??? Could you > > please elaborate? > > > > "pete dudley" <padudle@spinn.net> wrote in message > > news:tuoaa680e35ocb@corp.supernews.com... > > > People here in Albuquerque are receiving their XC2V6000CES parts but > > forget > > > about the XC2V10,000 parts. I think Xilinx has given up on doing them > > until > > > the next process shrink. > > > > > > -- > > > Pete Dudley > > > > > > Arroyo Grande Systems > > > > > > "Austin Franklin" <austin@dark98room.com> wrote in message > > > news:tuo027tbr1fn64@corp.supernews.com... > > > > Hi, > > > > > > > > What is the largest Virtex 2 part that anyone physically has in hand? > > > > > > > > What promises have you received for delivery of parts? > > > > > > > > I have a client who wants to use the large V2 parts (6000), but we can't > > > get > > > > a consistent answer from the distributor WRT delivery. I got VERY badly > > > > burnt last year with promises for V3200 delivery that never > > > > materialized...so I am leery of making any commitments to clients about > > > > parts that I don't have in hand. > > > > > > > > Any info would be appreciated. > > > > > > > > Thanks! > > > > > > > > > > > > > > > > > > >Article: 36572
We've been using 10's of 2V1000's (XC2V1000-4FG), and have had no trouble with deliveries, and the prices have even been coming down! We recently asked about some 2V3000's and I think the quote was quite reasonable with respect to price and delivery. Austin Lesea wrote: > Austin F, > > As in shipments of parts? > > 2V40, 2V1000, 2V3000, 2V4000, 2V6000 .... > > Maybe someone didn't get their order in on time? > > Austin L > -- ******************************************************************** * Jim Bittman * Tel: 603-226-0404 * * BittWare, Inc. * Fax: 603-226-6667 * * 33 North Main Street * E-Mail: jmbj@bittware.com * * Concord, NH 03301 * WWW: http://www.bittware.com * ********************************************************************Article: 36573
A 5-MHz design should not have any performance issues. But there are still plenty of things to go wrong: • Clock reflections on the pc-board causing double-triggering • Hold-time issues due to internal clock delays that are longer than the best-case clock-to-out delay of flip-flops. • Uncontrolled combinatorial feedback loops. Such things actually get worse and cause more trouble as the inherent circuit speed gets better. You used to worry that the chip wasn't fast enough. Now you have to worry that it might be faster than you wish, and perhaps even faster than you can observe... Peter Alfke =========================== Nial Stewart wrote: > Russell Shaw wrote: > > > > > If its the web-edition thing, i don't think it does the acex devices: > > http://www.altera.com/products/software/sfw-quarwebmain.html > > You're right, Acex support's just appeared in the last edition of > Quartus, so the web version should support it fairly soon. > > > BTW, i've never bothered to do any routing or timing constraints, > > because i've only just got to the stage of understanding > > vhdl->hardware, and i really couldn't think of anything that > > needed timing done when the clock was only 5MHz. > > You should be able to add a 5MHz clock constraint easily, although > unless you've written code with 30 odd levels of logic I'm sure > your design should work OK. > > > However, i > > think there might be a clock-alignment problem somewhere. > > There shouldn't be. If you've used a global clock input pin > for your clock they guarantee set up and hold times from > egister to register. it's then just a matter or making > sure you're writing good synchronous code. > > > Think its time to go thru the maxplus2 floor-plan help files again... > > You shouldn't have to worry about the floor planner at > 5MHz. > > I'd worry about the front end, ie your design and code first. > You should only have to resort to the floor planner if you're > really pushing the limits of the FPGA. > > Nial.Article: 36574
We have a real simple sch/vhdl design done under 3.1 that has encountered a number of problems. I can't imagine these being unique, but I also don't see how everyone could have them and not be screaming.... We are using the 2V1000, and this design uses only ~4% of the logic with mostly schematic blocks, some VHDL blocks, and a CoreGen memory module. List of compatibility issues: o Vcc and Gnd, in sch. Old had net=Vcc or Gnd worked fine, now there is a component called Vcc and Gnd, which allowed a bit file to be generated, but no simulation. Does Xilinx really expect everyone to have to change their schematics by hand to replace the nets with the symbols? We still haven't figured out the MTI problem, but I assume we'll get past it. o Schematic symbols. Worked just fine before, but either the I/O ports weren't checked or there was a translation error because there was all kinds of hand-editing required for the pin fields. o Signal names. Old design had blocks with ports dat[15:8], dat[7:0], etc. but 4.1 won't let this go, and again the sch. had to be hand-edited to create a single port with the entire bus dat[31:0]. Again a silly little problem, but if we had a "real" design, this could take days of UNnecessary hand-editing. o Text notes. Cosmetic only, but any notes on page-1 of a multi-page schematic, were duplicated on all schematic pages. o I/O config. Default changed to 2.5V? For whatever reason, all sorts of signals when the tools were first run switched to 2.5V that were 3.3V in last design. Again, wasn't a big deal, but all this hand-editing is getting ridiculous! o PROM programmer. Old CDF file didn't work, had to recreated from scratch, and we could NOT use 3.1 bit file because it now requires JTAG clock option. Really annoying, but not catastrophic because we have another way to load a bit file. (Another annoying aspect that did exist before is that any Virtex device in the chain *requires* a bit file even if you're not going to do anything to the device. For instance if you are going to write a PROM that happens to be in the same JTAG chain as the Virtex. We had to tell the software that the Virtex was a non-Xilinx device to make it work |-). I could go on, but here we have a seriously under-utilized device and a LOT of work to upgrade the software. What gives - are we unique or is everyone just accepting this as the necessary pain to upgrade??? Thanks in advance! Jim. -- ******************************************************************** * Jim Bittman * Tel: 603-226-0404 * * BittWare, Inc. * Fax: 603-226-6667 * * 33 North Main Street * E-Mail: jmbj@bittware.com * * Concord, NH 03301 * WWW: http://www.bittware.com * ********************************************************************
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