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Ray Andraka <ray@andraka.com> writes: >You need to understand what block floating point means. A block floating >point means that all the points of a set share a common exponent. This is >commonly done in FFTs because the FFT can have a fairly high dynamic range, >especially with longer transforms. It is a compromise between fixed point >and floating point implementations (the hardware cost is little more than >the fixed point case, but it allows a much larger dynamic range) Hmmm. There are questions in comp.arch.fpga sometimes about doing floating point in FPGA's. One of the things that make it hard is doing normalization. It is possible that block floating point might be easier to implement in an FPGA, assuming one wanted to implement FFT in an FPGA. I think multiply is still hard (expensive in cells) to do in an FPGA, so that might be the limiting step, as FFT has a lot of multiplies. Then there is the ICT, Integer Cosine Transform, a transform specifically designed for doing video compression on processors that can't multiply, like the CDP1802. (A google search on "integer cosine transform" will find it.) -- glenArticle: 37301
gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > Even the PDP-8 may be more > complicated than the 6502. No. Speaking from experience, the 6502 takes MUCH more logic to implement than a PDP-8. > Now, how much of an Apple II can one put on an FPGA? > > I would expect external RAM, but the video, serial and disk > controller maybe could be included. And perhaps external EPROM or Flash to substitute for the masked ROM of the real Apple II. There was masked ROM for the firmware, character generator, and keyboard encoder. Some of the largest FPGAs actually have enough block RAM to implement all of the ROM, though that wouldn't be cost-effective. > Unless you need a 200MHz Apple II, I can't > see why you would want an FPGA version. It's difficult to get an FPGA implementation of a 6502 to run faster than 50 MHz. Even that fast is a challenge.Article: 37302
"Kiyoung SON" <elcielo0@hitel.net> wrote in message news:W2BP7.58$H3.252301@news.bora.net... > designed FPGA for Apple II computer... > I want it... > > A 6502 core has been implemented in VHDL. That could be used to start the project off. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 37303
Sul Weh wrote: > > Also, why would one choose to use opencores instead of the Xilinx logicore > PCI? Why? It's free, perhaps? -aArticle: 37304
Kiyoung SON wrote: > > designed FPGA for Apple II computer... > I want it... Shit, go to any University's cast-off auction and you can find pallets of 'em for sale or for free. -aArticle: 37305
Nick wrote:
> I am using 2 clocks. Both are global, and this path actual uses both
> clocks.
> The second clock is derived from the first ( twice period)
> always @(posedge clk) s_clk = ~s_clk;
>
> > > Are you (Nick) clocking on both edges of the clock?
> >
> > I hope not.
> >
>
> Yes i do in one circumstance, is this so bad...? What i wanted to do
> is to provide a state like the following
> clk 101
> s_clk
Your choices are:
1. Redo your design and timing analysis
along the lines of Brian's suggestions
to correct the correct the clock skew
you introduce by using two clocks.
2. Redo your design with a single clock
on a global line so you can use a simple
register to register static timing analysis.
--Mike Treseler
Article: 37306Well, if you're willing to use an external CPU and ROM, you can make it yourself for free. Just get the Apple ][ Owner's manual - it has complete schematics. Then enter 'em into your favorite FPGA toolset and have fun. Even the monitor source code listing is in that manual. The disk interface and optional printer card / 16k additional RAM / 80 column video / etc. cards are extra, of course. I've got a schematic for the 16k "Language card" (we made a bunch for ourselves at HP back in '81 or so). But even using an external RAM, Flash (for ROM), and CPU you'd only have a few chips on the board - and small, surface mount ones at that. Complete with backplane. Jim Horn, WB9SYN/6Article: 37307
Hello all, i just installed Xilinx ISE 4.1i, when i create a new project i have ONLY ONE option (the EDIF ) in the design flow drop down bar. I want to use a VHDL file for input but its absent, how can i overcome this problem? plz help me because i cant find the solution in xilinx's support pages Harris L.Article: 37308
The unique aspect of the XC6200 was that it tolerated any "garbage" bitstream, since there was no possibility of contention. No other FPGA has that feature. Peter Alfke Jason wrote: > Is there anything that is comparable to the Xilinx XC6200 RPU? > > JasonArticle: 37309
gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > "Kiyoung SON" <elcielo0@hitel.net> writes: > > >designed FPGA for Apple II computer... > > I know that people are working on FPGA implementations of > the PDP-8, PDP-11, and PDP-10. Even the PDP-8 may be more > complicated than the 6502. PDP-8/I already exists, in form of DGCs PDP-8/X (using XCS10+XCS05): http://www.spies.com/~dgc/pdp8x/ Dito also PDP-4, in form of DGCs PDP-4/X (using XC4010E+XCS05): http://www.spies.com/~dgc/pdp4x/ -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 37310
The hardware to do a PDP-8 is really quite minimal. As I recall, the
6502 had quite a few bells and whistles in the instruction set. I'd
also be vey impressed if you got a 6502 clone running at even 100 MHz in
an FPGA. The structure is not well matched to the FPGA, and designs
that are specifically tailored to the FPGA architecture have difficulty
running above about 100 MHz.
glen herrmannsfeldt wrote:
> "Kiyoung SON" <elcielo0@hitel.net> writes:
>
> >designed FPGA for Apple II computer...
> >I want it...
>
> I know that people are working on FPGA implementations of
> the PDP-8, PDP-11, and PDP-10. Even the PDP-8 may be more
> complicated than the 6502.
>
> Now, how much of an Apple II can one put on an FPGA?
>
> I would expect external RAM, but the video, serial and disk
> controller maybe could be included.
>
> I think, though, it could be done in C and run on any current
> processor instead. Unless you need a 200MHz Apple II, I can't
> see why you would want an FPGA version.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37311Caution, We once programmed an Apple II on an FPGA perhaps seven years ago. It ran far, far, too fast. The disk interface is done in software, so all of the timing was off. Everything worked fine, but it couldn't talk to the disk drives. Austin Kiyoung SON wrote: > designed FPGA for Apple II computer... > I want it...Article: 37312
Not true, Xilinx supports 66 Mhz 64 bit pci in a Virtex I - 6 grade. (they were the first device family to have the PCI_LOGIC block) lots of the back end dma code had to be hand placed to make it work - but I did get timing closure on it. of course, if you are going to make a card that will work in a 5v as well as 3v3 environment you Have to use a Virtex 1 / Spartan 2 part to get 5v tolerance. Regards, MikeJ<nospam>@freeuk.com "Ray Andraka" <ray@andraka.com> wrote in message news:3C0C6F9E.A0E69473@andraka.com... > IIRC, the VirtexE was the first family they claimed for 66MHz 64 bit. To > get there, you need to use the TRDY logic that is embedded along the sides > of the array. The synthesis tools and even the mapper and pAR don't know > about this little added logic, so if you need to use it, you have to go into > the FPGA editor and add it to the design. Without it, I think you'll find > that you won't hit the 66 MHz 64 bit PCI spec, certainly not for the > original 2.5v Virtex, and I'm pretty sure not for the Virtex E either. > > sdfjsd wrote: > > > > http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html > > > > > > I used this kit to develop my own PCI IP core, and although the PCI IP > > > core doesn't meet 33MHz PCI's timings (Tsu < 7ns and Tval < 11ns), the > > > card somehow (barely) worked in two computers I tested it. > > > It would have been nice if the Insight Electronics Spartan-II > > > Development Kit used a 200K system gate part (XC2S200) instead of a > > > 150K system gate part (XC2S150) even if the kit cost another $50 more, > > > but overall I am very happy with the Insight Electronics Spartan-II > > > Development Kit. > > > > What does "barely" worked really mean? I'm not intimately familiar > > with PCI-protcol...I know that the PCI bus outputs (on a device) > > are unregistered, to respond to the bus-protocol. Are you saying that > > the XCS2-150-5 device was barely fast enough to meet 33MHz timing? > > > > Xilinx brazenly boasts that their Virtex family (the old 0.25micron > > family) supports PCI66MHz/64-bit. Your experience suggests that > > while this can certainly be true, it's not an easily achievable > > target for someone not designing specifically for FPGA. > > > > Someone I know wants to develop a PCI-core for an in-house project. > > He threw around the idea of prototyping it on an FPGA-board. > > I advised him against it, simply because a lot of his design > > implementation would be governed by the FPGA's architectire > > (vs the actual production goal of a standard cell ASIC process.) > > > > I reasoned he'd be wasting a lot of dev time making the core > > work on an FPGA-device, i.e. wasting dev-time "designing for > > FPGA", instead of just designing for the final project goal. > > > > sorry if this is a redundant question... > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 37313
Hi, I installed ISE 4.1i onto a Windows NT 4.0 server as a network floating license. I also added the new Service Pack 2. Running the software directly on the server didn't cause any problems. But when synthesizing a design on a client, FPGA Express cannot be called. Following error message occurs: "Starting: 'expresscli top.epfx' Unable read the Constraint Editor GUID Done: failed with exit code: 0001." When starting FPGA Express directly outside ISE, the following error message pops up: "System registry is not initialized - please run FPGA Express setup" According to answer record #12274 this problem should be fixed in service pack 1. But what about service pack 2? Do I have to install service pack 1 first of all? By the way, I couldn't find service pack 1 anymore. According to answer record #9379 there existed a batch "setFEXPenv.bat" fixing that problem for ISE 3.1i. Is there a similar patch available for ISE4.1i? I couldn't find one. Just as background: 1) Server is a NT 4.0 machine 2) Clients are Windows 2000 Laptops with wireless LAN cards 3) Licensing mechanism seems to work properly. Licenses are checked in and out on the license server ( = program server) 4) Environment variables are set. 5) I executed setXenv.bat before and after service pack installation. Of no use :-( 6) Rebooting server and clients didn't help I'd be very grateful, if anybody could help me! Cheers, Bernd e-mail: scheuermann@aifb.uni-karlsruhe.deArticle: 37314
Ditto, without the part numbers there isn't a way to tell if they would be usable. Andy Holt wrote: > Jim Stewart wrote: > > > > You'd be doing yourself and us a favor if you'd post full part numbers > > of all the parts. > and accepted international bids > > AndyArticle: 37315
The 6502 is surpisingly complicated. I made an initial stab at implementing a 6502 in an FPGA. I decided not to pursue it because it doesn't map that well to an FPGA architecture. Synthesis estimated 35MHz and 30% of a spartanII XC2S200 I think. It's on my website http://www.birdcomputer.ca/ untested and undebugged, but it might make a starting point. I think a better approach might be to develop a simple RISC processor customized for efficiently implementing a 6502 emulator in software. You could probably get almost the same performance, and it would be a whole lot easier. Rob "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhk7w017yt.fsf@ruckus.brouhaha.com... > gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > > Even the PDP-8 may be more > > complicated than the 6502. > > No. Speaking from experience, the 6502 takes MUCH more logic to > implement than a PDP-8. > > > Now, how much of an Apple II can one put on an FPGA? > > > > I would expect external RAM, but the video, serial and disk > > controller maybe could be included. > > And perhaps external EPROM or Flash to substitute for the masked ROM > of the real Apple II. There was masked ROM for the firmware, character > generator, and keyboard encoder. > > Some of the largest FPGAs actually have enough block RAM to implement > all of the ROM, though that wouldn't be cost-effective. > > > Unless you need a 200MHz Apple II, I can't > > see why you would want an FPGA version. > > It's difficult to get an FPGA implementation of a 6502 to run faster > than 50 MHz. Even that fast is a challenge.Article: 37316
The normalization is not awful, although it takes up resources. Fortunately, it
can be pipelined to very high clock rates with only a few (log2(bits) clocks of
latency. We've done a number of larger FFTs in FPGAs based on our 16 and 8 point
kernels. Our kernels are the fastest possible (70 ns transform time for 16
point in virtexE-8) in a single threaded FPGA design (single threaded meaning
all the data passes through the same data path), as the speed is limited by the
FPGA's SRL16 minimum clock pulse width, not propagation delays like most other
designs. Ours also happen to be among the smallest, at a mere 20x25 Virtex CLBs
(it fits in an XCV100). THe data sheet for the 16 point core is on our
website. The 8 point core is similar.
We did a number of algorithmic and architectural tricks to get the speed and
density. The multipliers occupy about 1/3 of the area, and they are not the
slowest path in the design. For detail on how to do multiplication in FPGAs,
look at our website; there is a page there dedicated to multiplication in
FPGAs. Also, the VirtexII family has dedicated multipliers that make it easier
than ever to do mutliplication in FPGAs (although you can significantly
outperform those with a CLB based pipelined multiplier)
glen herrmannsfeldt wrote:
> Hmmm. There are questions in comp.arch.fpga sometimes about doing
> floating point in FPGA's. One of the things that make it hard is
> doing normalization. It is possible that block floating point
> might be easier to implement in an FPGA, assuming one wanted to
> implement FFT in an FPGA.
>
> I think multiply is still hard (expensive in cells) to do in an
> FPGA, so that might be the limiting step, as FFT has a lot
> of multiplies.
>
> Then there is the ICT, Integer Cosine Transform, a transform
> specifically designed for doing video compression on processors
> that can't multiply, like the CDP1802. (A google search on
> "integer cosine transform" will find it.)
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37317Hello all, i just installed xilinx ise 4. I decided to run the tutorial but when i create a new project (named tutorial) i have a big problem : the ONLY design flow i can select is the EDIF, i want to use the XST VHDL design flow fot the tutorial's purposes but its absent. Can anyone help me? Harris L.Article: 37318
This newsgroup has been very helpful the short time I've been here. I've been on IRC for 6 years and maybe only once or twice found other hardware engineers to talk to that actually know something. Are there any channels on efnet that comp.arch.fpga people hang out in? AndyArticle: 37319
>From the e-bay page: "The lot includes 4003 (3), 4004 (4), 4010 (20) and 4013 (51)units." Is that 20 XC4010 FPGAs? "Jose I Quinones" <joseiq@mcumaster.com> wrote in message news:3C0E1EB3.A67493BF@mcumaster.com... > Hi all, > > I have two huge Xilinx FPGA lots advertised on ebay. Some of the chips > are used, but others I believe are new. Check the link below. Enjoy! > > JIQ > > http://cgi6.ebay.com/aw-cgi/eBayISAPI.dll?ViewListedItems&userid=avayan&incl ude=0&since=-1&sort=2&rows=25Article: 37320
Oops, that should have read "...and _microprocessor_ designs that are
specifically...". We routinely do other designs well beyond 100 MHz.
Microprocessors can be a challenge at the high rates because there is
limited opportunity for deep pipelining.
Ray Andraka wrote:
> an FPGA. The structure is not well matched to the FPGA, and designs
> that are specifically tailored to the FPGA architecture have difficulty
> running above about 100 MHz.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37321
Thanks for the clarification. Memory must be getting the better of me. It was
the 4K series that supported PCI33, and you are correct, virtex -6 supported
PCI66.
"Mike Johnson
> Not true, Xilinx supports 66 Mhz 64 bit pci in a Virtex I - 6 grade.
> (they were the first device family to have the PCI_LOGIC block)
> lots of the back end dma code had to be hand placed to make it work - but I
> did
> get timing closure on it.
> of course, if you are going to make a card that will work in a 5v as well
> as 3v3 environment
> you Have to use a Virtex 1 / Spartan 2 part to get 5v tolerance.
>
> Regards,
>
> MikeJ<nospam>@freeuk.com
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3C0C6F9E.A0E69473@andraka.com...
> > IIRC, the VirtexE was the first family they claimed for 66MHz 64 bit. To
> > get there, you need to use the TRDY logic that is embedded along the sides
> > of the array. The synthesis tools and even the mapper and pAR don't know
> > about this little added logic, so if you need to use it, you have to go
> into
> > the FPGA editor and add it to the design. Without it, I think you'll find
> > that you won't hit the 66 MHz 64 bit PCI spec, certainly not for the
> > original 2.5v Virtex, and I'm pretty sure not for the Virtex E either.
> >
> > sdfjsd wrote:
> >
> > > > http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html
> > > >
> > > > I used this kit to develop my own PCI IP core, and although the PCI IP
> > > > core doesn't meet 33MHz PCI's timings (Tsu < 7ns and Tval < 11ns), the
> > > > card somehow (barely) worked in two computers I tested it.
> > > > It would have been nice if the Insight Electronics Spartan-II
> > > > Development Kit used a 200K system gate part (XC2S200) instead of a
> > > > 150K system gate part (XC2S150) even if the kit cost another $50 more,
> > > > but overall I am very happy with the Insight Electronics Spartan-II
> > > > Development Kit.
> > >
> > > What does "barely" worked really mean? I'm not intimately familiar
> > > with PCI-protcol...I know that the PCI bus outputs (on a device)
> > > are unregistered, to respond to the bus-protocol. Are you saying that
> > > the XCS2-150-5 device was barely fast enough to meet 33MHz timing?
> > >
> > > Xilinx brazenly boasts that their Virtex family (the old 0.25micron
> > > family) supports PCI66MHz/64-bit. Your experience suggests that
> > > while this can certainly be true, it's not an easily achievable
> > > target for someone not designing specifically for FPGA.
> > >
> > > Someone I know wants to develop a PCI-core for an in-house project.
> > > He threw around the idea of prototyping it on an FPGA-board.
> > > I advised him against it, simply because a lot of his design
> > > implementation would be governed by the FPGA's architectire
> > > (vs the actual production goal of a standard cell ASIC process.)
> > >
> > > I reasoned he'd be wasting a lot of dev time making the core
> > > work on an FPGA-device, i.e. wasting dev-time "designing for
> > > FPGA", instead of just designing for the final project goal.
> > >
> > > sorry if this is a redundant question...
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37322"Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in> writes: > Hi, > I want to use > > ncvlog -file ncvlog.args Why not something like: yourfilter < ncvlog.tmpl > ncvlog.args && ncvlog -file ncvlog.args Where yourfilter is a small script written in your favorite scripting or programming language to subsitute the environment variables. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 37323
sdfjsd <kljfsdlkfskljfds@kjflsdkjlfsdklfdslfsdklsdf.com> wrote in message news:<3C0C6D5E.AC5972FC@kjflsdkjlfsdklfdslfsdklsdf.com>...
> > http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html
> >
> > I used this kit to develop my own PCI IP core, and although the PCI IP
> > core doesn't meet 33MHz PCI's timings (Tsu < 7ns and Tval < 11ns), the
> > card somehow (barely) worked in two computers I tested it.
> > It would have been nice if the Insight Electronics Spartan-II
> > Development Kit used a 200K system gate part (XC2S200) instead of a
> > 150K system gate part (XC2S150) even if the kit cost another $50 more,
> > but overall I am very happy with the Insight Electronics Spartan-II
> > Development Kit.
>
> What does "barely" worked really mean? I'm not intimately familiar
> with PCI-protcol...I know that the PCI bus outputs (on a device)
> are unregistered, to respond to the bus-protocol. Are you saying that
> the XCS2-150-5 device was barely fast enough to meet 33MHz timing?
What I meant from "'barely' worked" is that the PCI IP core I
developed had Tsu of around 11ns if I remember it correctly, but it
somehow worked in two computers I tested it.
Some people said in this newsgroup that Xilinx devices run around 40%
faster in room temperature (20 degrees celsius), so perhaps that is
the reason it worked.
I think the trick of a PCI IP core to meet 33MHz timings in my opinion
will be to keep the levels of logic as low as possible, and take
advantage of IOB FFs.
Of course, if that doesn't work well, the LUTs will have to be
floorplanned, but if there is about six levels of logic (one for input
pin, one for IOB FF, and four levels of LUTs), even floorplanning
won't help (that's the case in my case).
In this case, I am using Spartan-II speed grade -5, but speed grade -6
should meet timings if I floorplanned it.
>
> Xilinx brazenly boasts that their Virtex family (the old 0.25micron
> family) supports PCI66MHz/64-bit. Your experience suggests that
> while this can certainly be true, it's not an easily achievable
> target for someone not designing specifically for FPGA.
I guess it depends on the skill of the designer, but I think
even 33MHz PCI's Tsu (Tsu < 7ns) is hard to meet for my design . . .
>
> Someone I know wants to develop a PCI-core for an in-house project.
> He threw around the idea of prototyping it on an FPGA-board.
> I advised him against it, simply because a lot of his design
> implementation would be governed by the FPGA's architectire
> (vs the actual production goal of a standard cell ASIC process.)
>
> I reasoned he'd be wasting a lot of dev time making the core
> work on an FPGA-device, i.e. wasting dev-time "designing for
> FPGA", instead of just designing for the final project goal.
>
> sorry if this is a redundant question...
Although I will not make any guarantees, even if the FPGA
prototype doesn't meet 33MHz PCI Tsu, if it somehow works in actual
system, I think that lowers the risk of an ASIC not working properly
from the first time.
Since the ASIC respin costs time and money, making sure it sort of
works in an FPGA before ASIC tapeout might save time and money in the
long run.
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Article: 37324Even if it is free, it might require some effort on the user's side to make sure the PCI interface meets timings (Tsu < 7ns, Tval < 11ns). Tval is easy to meet (in my case, in retrospect . . .), assuming the designer knows that rules on the IOB merging. Because Xilinx doesn't really explain IOB FF merging rules on the device datasheet (their support page tell finally mentions it), it took me severals months to figure that out . . . However, Tsu is much harder to meet from my experience, since even counting clock skew of 2.4 ns for Spartan-II 150K gate speed grade -5 (the chip Opencores.org team used), Tsu will only be 9.4 ns (7ns + 2.4ns). Out of 9.4ns, high fanout signals like FRAME# and IRDY# have to go through an input pin, several levels of LUTs, and IOB output FFs. The interconnect delay is not zero, and that can easily account for 50% of more of the delay from my experience. Kevin Brace (don't respond to me directly, respond within the newsgroup) "Sul Weh" <sweather1999@yahoo.com> wrote in message news:<v%GP7.282$L51.3735@rwcrnsc54>... > Also, why would one choose to use opencores instead of the Xilinx logicore > PCI? > > thanks > > SW
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