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For some reason, Xilinx does not make this information available. It is some kind of deep dark secret that mere mortals are not allowed to possess. I believe it is a way for Xilinx to limit the number of design wins so they don't have to bother making so many parts. I want basic pricing information so I can quickly compare families and parts within families and trade off size and pins. This is made more difficult when I have to ask my distributor (with a one or two day turnaround) for each and every price. I don't expect the pricing information to be very accurate. I know that pricing depends heavily on volume and that it changes. But I assume the prices relative to each other will not change much. Altera does make price lists available. TI puts bugetary pricing on their web site. Alan Nishioka alann@accom.com Jim Raynor wrote: >Does anyone know where to get a complete price list for all the Xilinx's >FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have >to be accurate 'cause I just want to get an idea which FPGAs I am going to >use in the new design in term of processing power and $$$. >Article: 41951
This is my choice: http://www.cesys.com/deutsch/XC2S_EVAL.htm Looks very good. Dedicated PCI chip, no licencing for a PCI core, very low price (349 Euro, which is about 380 $). I just have to make sure it's kept busy... Frank "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a921pk$4ot$2@newsreader.mailgate.org... > So, that German company's (Wasn't it Cesys or something like that?) PCI > card is not going to do the job.Article: 41952
On 11 Apr 2002 05:39:31 -0700, meng.engineering@bluewin.ch (Markus Meng) wrote: >Hi all, > >I need to design a special mini version of a HDLC controller >for a E1 PCM bus. The HDLC controller shall provide flag >recognition, bit stuffing, but no CRC checking is required. > >What I lack are general infos regarding the timings, and the >format on such a E1 PCM bus. Where can I find some useful >'engineering-ready' infos for that topic in order to implement >the HDLC controller easily ... The E1 is standardised, but the "E1 Bus" isn't. The exact format of the bus is determined by the chip set that sits between the E1 and your HDLC controller. The information you require will be in the datasheet for the E1 framer chip. BTW, many E1 framers already contain HDLC controllers built in. Regards, Allan.Article: 41953
Hello Verplex-LEC can read in edif netlists. RTL to FPGA netlist (xilinx or altera) can be done to a certain extent. There are also a handful of customers who use Verplex-LEC in a FPGA to ASIC verification flow. This way the silicon can be rapidly prototyped in an FPGA and then mapped to an ASIC and its vendor's library along with equivalency checking ( EC ) of the functionality. Nonetheless, the static timing will have to be done. If you need more information on how to accodomate and RTL to FPGA equivalency checking, please contact support@verplex.com. Cheers Masood Makkar ================================== Masood Makkar, Verplex Systems-TX Central Apps Engineering Manager makkarm@verplex.com ================================== strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0204081930.4ac14e6b@posting.google.com>... > has anyone ever used an equivalence checker to check a synthesized > netlist with the RTL code? i am thinking i can save a lot of time if i > follow this approach instead of doing exhaustive gate level sims. if > anyone has done this kind of thing, do the tools accept EDIF format > (Verplex, Formality)?Article: 41954
Jim, Go to any Xilinx distributor web-site. The pricing info is there. Theron Hicks Jim Raynor wrote: > hi, > > Does anyone know where to get a complete price list for all the Xilinx's > FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have > to be accurate 'cause I just want to get an idea which FPGAs I am going to > use in the new design in term of processing power and $$$. > > Thanks > > JimArticle: 41955
Is that what you really want? I heard that that PCI board can handle only 1MB/s to 2MB/s (Something close to an ISA bus card.) because supposedly it cannot handle burst transfers. I don't have anything against the company, but I just think it is not the right choice for your application. Go with Insight Electronics Spartan-II PCI 200 or the Nallatech Spartan-II PCI board (I forgot the name.), and if you cannot afford LogiCORE PCI, use Opencores.org's free PCI IP core. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Frank de Groot wrote: > > This is my choice: > > http://www.cesys.com/deutsch/XC2S_EVAL.htm > > Looks very good. Dedicated PCI chip, no licencing for a PCI core, very low > price (349 Euro, which is about 380 $). > I just have to make sure it's kept busy... > > Frank >Article: 41956
In article <6Bjt8.529$UH1.98590@news2.telusplanet.net>,
"Jim Raynor" <chris@ultrasonix.com> writes:
|> Does anyone know where to get a complete price list for all the Xilinx's
|> FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have
|> to be accurate 'cause I just want to get an idea which FPGAs I am going to
|> use in the new design in term of processing power and $$$.
A rough pricecheck is possible with http://www.avnetmarshall.com, simply enter
the partnumber in the search field on the left.
--
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 41957
Martin Czamai wrote:
>
> Hello,
>
> I'm planning to buy the Spartan-II T 200 PCI eval kit
> (DS-KIT-2S200-PAK-EURO) from Insight Electronics, but since a board
> without a good description and service is no good choice to get
> started, I'm interested your experience with Insight and especially
> the demo kit.
I have used the older Spartan-II PCI Development Kit with
XC2S150-5CPQ208 (A smaller chip than the board you are interested.) for
my own PCI IP core development, and I will call myself a happy customer
of that board considering how cheap it was. ($145 for the older one. The
newer one is a little more expensive.)
I used the free ISE WebPACK throughout the development, and when I did
some simple testing of the PCI card with my PCI IP core inside using two
computers I had, the PCI card worked fine in both computers.
> Additionally, has somebody already tried to implement den PCI core
> from OpenCores? Will this core work on this board?
Because I did my own, I haven't tried the Opencore.org's one.
The website has a sample application for the older Spartan-II PCI card
(It uses a DIME expansion slot.), and it said it worked in a real
computer, so I will assume that is true.
In theory, if you specify the the PCI pin out of the new Spartan-II PCI
board to match the signals coming out of their PCI IP core, the IP core
should work.
You can do so in a .UCF file.
> How does it look like about documentation of the P160 expansion
> module?
Once you purchase any Insight Electronics development kit, you
can register to gain access to their reference design center.
I checked out the reference design center recently, and they had a P160
expansion module specification available, but the documentation for the
new Spartan-II PCI 200 card wasn't there yet.
> Does the kit include some description about it, e. g. infos about
> timing
> contraints?
> I hope to receive a lot of feedback,
>
> thanks
>
> Martin
> MCzamai@gmx.net
Opencores.org PCI IP core's sample application should come with
a constraint file. (A .UCF file.)
You will likely have to modify the pin out and get rid of constraints
related to their sample application.
Insight Electronics might also have a constraint file, but it will be
for LogiCORE PCI.
You can write your own constraint file using a UCF Editor, and once you
learn the UCF file syntax, you can use a text editor.
All you have to make sure is,
Setup Time (Tsu) : Tsu < 7ns
Clock-to-Output Valid (Tval) : Tval < 11ns
Hold Time (Th) : Th = 0ns
Clock Frequency : Tperiod < 30ns (fmax > 33.3MHz)
You should also specify the pin out and I/O buffer. (Since most
computers still use 5V PCI, specify PCI33_5 as the I/O buffer.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41958The idcode for the xcv100 is 0x0614093. The last nibble you have (the 3) does not count. So it is reading out the correct idcode (well plus). After looking into it the xc2s100 also has the same idcode!!! I'd say if it asks to go ahead just say yes... Steve "Stefano M" <stefano.mora@antispam.libero.it> wrote in message news:rRit8.18176$m41.473318@twister2.libero.it... > Hi all, > i'm trying to download a simple code on Spartan II Demo Board > (by Insight) via JTAG cable. > The problem is that iMPACT detects a xcv100 instead of > xc2s100, warns me and if i go ahead and try to program > i receive a lot of difference. > This is the log (if it can be helpful...): > > Checking for System Ace MPM device... > ---------------------------------------------------------------------- > Position PartName Version FileName > 1 xc18v01 0 NOT YET ASSIGNED > 2 xcv100 3 NOT YET ASSIGNED > ---------------------------------------------------------------------- > > Validating chain... > Boundary-scan chain validated successfully. > '2': IDCODE is '00110000011000010100000010010011' > '2': IDCODE is '30614093' (in hex). > > Can someone help me to solve ? > Thanks a lot, > regards > -- > Stefano Mora > email: stefano.mora@*libero.it > (remove *) > >Article: 41959
> I have used the older Spartan-II PCI Development Kit with > XC2S150-5CPQ208 (A smaller chip than the board you are interested.) for > my own PCI IP core development, and I will call myself a happy customer > of that board considering how cheap it was. ($145 for the older one. The > newer one is a little more expensive.) > I used the free ISE WebPACK throughout the development, and when I did > some simple testing of the PCI card with my PCI IP core inside using two > computers I had, the PCI card worked fine in both computers. > a credit to your design. > > Once you purchase any Insight Electronics development kit, you > can register to gain access to their reference design center. > I checked out the reference design center recently, and they had a P160 > expansion module specification available, but the documentation for the > new Spartan-II PCI 200 card wasn't there yet. > I spoke to an apps engineer and he was vague as to what was available via the design center. can you help in explaining? If I purchase this kit , do I get a working PCI design ?/ Thanks for your help Dave (reply direct if you like, the spammers do :-) )Article: 41960
Hello, Well, everything is in the title, what are the main differences between the Virtex and Virtex II families of FPGA? regards, CyrilleArticle: 41961
I am currently thinking about using the Opencores PCI Bridge as a starting point for development. I need to develop a PCI bridge with a switchable backend (or maybe just the IBM CoreConnect bus, depending on how easy it would be to drive it with an FSM instead of a processor). My question: Has ANYONE had ANY experience, good or bad, with the Opencores bridge? I notice that a lot of people decide to write their own, and I'm all for that normally, but I would like to try and minimize the amount of work that goes into the PCI interface. As you can see from my project description below, there is a LOT more to do here than just the PCI. (I do realize that yes, I could buy the Xilinx core, but two things concern me with that route: i would like to perform some of the PCI central resource functions in the FPGA alongside the master core--it would be ideal to have the Xilinx board drive a bus outside of a PC, and there is some custom wiring to do here as well as FPGA programming--, and the price is a little steep for me--at least until I can justify it.) (My application: On a Xilinx FPGA, there will be the PCI bridge, a processor core, and a state machine. The Xilinx board talks to a digital transciever (basically a nice A/D and D/A with Intersil (formerly Harris) DDC and DUC chips) over the PCI bus. The processor will be used for some configuration tasks, but while no configuration is going on, the state machine will send data to and gather data from the transciever. Probably on another FPGA I will do some coding/decoding operations.) thanks! j. ------------------- Jason W. ZimmermannArticle: 41962
Paul, In this case it is a matter of style. You like longer names, I prefer shorter. You prefer to constrain anything that might be used as an index to unsigned, I prefer to impose types only to insure portability. I like general-purpose functions. My concept on types is that they exist to eliminate ambiguity, period. Anything that can be done by a std_logic_vector that is not subject to interpretation should be. That means, that I am not a great fan of unsigned, as I have never heard a decent argument for why std_logic_vector cannot always be treated as unsigned with MSB on the left. Look at all the users who still invoke the Synopsys "IEEE" arithmetic libraries for a clue on consensus opinion on that subject. It's JMO, but that is why I see encode and decode functions as std_logic_vector in and out. If constraining the function works for you, that's great. Regards, "Paul Butler" <Paul.Butler@ni.com> wrote in message news:ubavicjb91s794@corp.supernews.com... > "sweir" <weirsp@yahoo.com> wrote: > > > Paul, why are you comparing a declaration with instantiations? > > Personally, I prefer simple names and appropriate comments > > in the source code. > > I listed the function declaration (as opposed to its instantiation) to > highlight the fact that my function does not take or return > std_logic_vector. I didn't find fnEncBin to be a self descriptive name. > Its behavior is like a type converter so I created a new type and chose a > name consistent with existing type converters. > > The instance alone doesn't tell the whole story: > > o <= fnEncBin(a) ; > vs. > o <= to_unsigned(a) ; > > That's a small change but don't forget the declarations: > > signal a : std_logic_vector(7 downto 0); > signal o : std_logic_vector(2 downto 0); > vs. > signal a : OneHot(7 downto 0); > signal o : unsigned(2 downto 0); > > My version has the usual benefits of compile-time type checking. Comments > near the function declaration are great but, unlike function signatures, > compilers ignore comments (most of the time). > > My view is based on the idea that OneHot and unsigned both represent integer > values as an array of bits but that their encodings are different. > Functions like to_integer(OneHot) and to_OneHot(integer,integer) might also > come in handy. > > Paul.Butler@ni.com > > >Article: 41963
Speedy Zero Two wrote:
>
> > I have used the older Spartan-II PCI Development Kit with
> > XC2S150-5CPQ208 (A smaller chip than the board you are interested.) for
> > my own PCI IP core development, and I will call myself a happy customer
> > of that board considering how cheap it was. ($145 for the older one. The
> > newer one is a little more expensive.)
> > I used the free ISE WebPACK throughout the development, and when I did
> > some simple testing of the PCI card with my PCI IP core inside using two
> > computers I had, the PCI card worked fine in both computers.
> >
>
> a credit to your design.
>
Thanks.
>
> I spoke to an apps engineer and he was vague as to what was available via
> the design center.
> can you help in explaining?
>
As of now, the reference design for Spartan-II PCI 200 hasn't
been uploaded yet, although the reference design for the older
Spartan-II PCI 150 card is still there.
The older reference design included a one that turns on and off an
on-board LED connected to one of the Spartan-II's pin, and another one
that makes the Spartan-II PCI card an 8MB memory card.
There were both written in VHDL, and it was for LogiCORE PCI only.
I don't know what the new reference design is going to be like, but I
will guess that it will likely be an 8MB memory card reference design
for LogiCORE PCI again.
Unless you are going to shell out $2,000 for a one project license or a
$5,000 regular license, the reference design will be pretty useless.
Although you should be able to use Opencores.org PCI IP core with it.
> If I purchase this kit , do I get a working PCI design ?/
>
> Thanks for your help
>
> Dave
>
> (reply direct if you like, the spammers do :-) )
Not really, unless you are going to use Opencores.org PCI IP
core or do your own PCI IP core.
The previous Spartan-II PCI card came with a .mcs file for the
Configuration PROM on the card that contained the LED reference design I
mentioned, but you cannot carve out the LogiCORE PCI from it, and attach
your own backend design. (Maybe it is not absolutely impossible to do
so, but to do that, you will have to deal with the bit stream fuse map.
I will rather develop my own PCI IP core than doing so risking the
chip.)
When I first plugged in the PCI card into a computer around August of
2001, the card already had the LED design bit stream installed, so if
you buy the card, and plug it into a computer, the card will work, but
it will be pretty useless because you won't be able to modify the
design.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41964Martin Thompson wrote: > Well, I've finally taken the plunge and started to play the the > Webpack software - and my first attempt has a DCM in it. From the > docs I've seen, it would appear that I have to specify the various > setup parameters for the DCM in both "attribute" form and "generic" > form! > Is this really the case in this day and age (and software - Synplify > 7.0 and Modelsim 5.5)? Sounds like a recipie for disastrous > simulation/synthesis mismatches to me! You're right. I prefer to write my own code. If you use their modules, you follow their rules. -- Mike TreselerArticle: 41965
"Steve Casselman" <sc.nospam@vcc.com> wrote in message news:<lAjt8.3377$Dp2.1695132711@newssvr14.news.prodigy.com>... > The patent has to do with adding the reconfigurable logic in parallel with > the current chip function. Basically a system where you can seem like the > device designed for the socket then behave like a fpga the next, take over > the system and do what you want. The idea is to build a chip that you could > just drop into an existing slot/socket and it would have a built-in > reconfigurable subsystem, yet it could do exactly what the original chip was > supposed to do. The vision is to take a Pentium out of the socket and be > able to plug in a reconfigurable computer (which today would include a > Pentium IV, a Virtex II Pro and a custom controller....) > > As far as patent rights go, a patent only gives you the right to stop > someone from selling a product if there is a violation. > > Steve So wouldn't the Pilchard only violate the patent if it pretended to be an SDRAM? It can't "do exactly what the original chip was supposed to do" and additionally it can't even pretend a little bit: "The Pilchard board does not have SPD so the BIOS identifies the slot as an empty slot." So they have to muck with the chipset to enable the slot after the fact. FYI - I have heard rumors to the effect that not all motherboard manufacturers follow Intel's DIMM spec and mix-up some of the address and data lines anyhow. (They obviously have to do some of the address lines to spec.) Compatibility for non-SDRAM devices would be a nightmare. So this is not the way to deliver reconfigurable computing to the masses. (Plus motherboards usually don't have that many DIMM sockets.) Anyways I really don't think that they are ripping off your idea, or violating your patent. If you had a "Pentium IV, a Virtex II Pro and a custom controller" chip for sale I would seriously consider buying it... Regards, KeithArticle: 41966
I need to prototype an ASIC design and am looking for advice on type of FPGA and on FPGA board as well. The board needs to have an ARM9, external memory, an interface to a PC (serial is ok), the FPGA (or ASIC), and a header to plug in a daughter card with some pins routed to the FPGA. The ASIC will have between 100K and 500K ASIC Logic Gates. It will run at about 150 MHz. It needs about 200 KB of internal RAM. And it will have a lot of multipliers. There will probably be some pipelining in the ASIC to meet speed - and probably deeper pipes in the FPGA. We want to match the FPGA to the ASIC as closely as possible. I think the key factors in FPGA selection are: - Capacity. We want to fit in one FPGA. - Performance. We want to run at speed. - "ASIC-like" synthesis library (see below)? - Availability of board described above. "ASIC-like" synthesis library... The datapath content on the ASIC may force us to use one of the datapath synthesis tools. These tools don't support FPGA architectures directly. I've heard that since the Actel architecture is "fine-grain" that it works best for these types of designs. Any advice will be much appreciated. Thanks, GilArticle: 41967
In article <a94m6t$j6$1@newsreader.mailgate.org>, Kevin Brace wrote: > Is that what you really want? > I heard that that PCI board can handle only 1MB/s to 2MB/s (Something > close to an ISA bus card.) because supposedly it cannot handle burst > transfers. I've read some of the documentation for this card and the PCI-bridge seems to be designed with a small 8-bit CPU in mind. The interface to the bridge is only one byte, so the card will silently ignore reads/writes to the remaining 3 bytes. The datasheet for the PITA-2 bridge is available here: http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/prod_ov.jsp?oid=16802 Anyway, the bridge is probably very interesting if it is used in conjunction with a small microcontroller. Not so interesting for most FPGA solutions. /AndreasArticle: 41968
Not sure if it will meet your gate count requirement, but how about Actel's ProASIC? Actel claims the architecture resembles standard-cell ASIC, but I don't have any direct experience using it. (I am very poor. I have only used Xilinx Spartan-II.) Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 41969
Thanks. At least you have used Xilinx Spartan-II. I've never done an FPGA and don't know Spartan-II from a Virtex from a ... (I'm an ASIC guy). Maybe you can comment on capacity and performance with the Spartan-II? Gil Kevin Brace wrote: > Not sure if it will meet your gate count requirement, but how about > Actel's ProASIC? > Actel claims the architecture resembles standard-cell ASIC, but I don't > have any direct experience using it. (I am very poor. I have only used > Xilinx Spartan-II.) > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) >Article: 41970
Nope,
If you were working with a virtexII or virtexII-pro then you can instantiate
the mult18x18s. VirtexE does not have the dedicated multipliers. You need to
either roll your own or use the Xilinx coregen to create a multiplier macro
which you can then put in your design. The multipliers in virtexE are created
from the general purpose logic in the fabric, not from special multipliers.
That said, there is an added AND gate in the carry logic that is useful for
reducing the logic required to make a 2xN partial product multiplier, which is
then used to create a larger multipler as shown on my website.
Kevin Neilson wrote:
> Instantiate MULT18X18S. Some synthesizers might be able to just infer them
> (with '*') but I've been instantiating them.
>
> Make sure you have the most current data sheet for multiplier timing.
> (They've been getting progressively slower.)
>
> "Max Edmand" <maxedman3503@yahoo.com> wrote in message
> news:3a30996f.0204101958.2df0945c@posting.google.com...
> > Could someone please give a hint how to instantiate built in
> > multipliers that Xilinx claims are available in Virtex 2000E?
> >
> > I need to exploit them in my VHDL design. should I use something
> > like primitives or components from Xilinx Library? but they seem
> > to be lower level functions like multiplexers, registers,
> > comparators,...
> >
> > Thanks,
> > Max Edmand
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41971
Even if you write your own you run into the attributes and generics
issue. Attributes pass through to the edif netlist but generally have no
meaning within VHDL. It is through user attributes that we can set
parameters that do not appear in the code. Generics are used to pass
parameters into VHDL components, but can't be passed out to the netlist
(generics can be thought of as parameter INPUTs to your code). The
requirement for both comes up because there are primitives in the FPGA
which require some sort of parameterization , be it an initialization
value (sucha s for RAMs, LUTs) or to set up a mode in a black box (such as
a DCM) that is set outside of the context of the netlist of your design.
The safest way to deal with these, I think, is to use a proxy that your
code reads and generates both the attribute and the generic value from.
Then to update, change the proxy so that the change automatically
propagates to both parameters.
Mike Treseler wrote:
> Martin Thompson wrote:
>
> > Well, I've finally taken the plunge and started to play the the
> > Webpack software - and my first attempt has a DCM in it. From the
> > docs I've seen, it would appear that I have to specify the various
> > setup parameters for the DCM in both "attribute" form and "generic"
> > form!
> > Is this really the case in this day and age (and software - Synplify
> > 7.0 and Modelsim 5.5)? Sounds like a recipie for disastrous
> > simulation/synthesis mismatches to me!
>
> You're right. I prefer to write my own code.
>
> If you use their modules, you follow their rules.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41972
The SpartanII and 5v Virtex share identical bitstreams for similar sized
parts, and have identical ID codes. Just ignore the warning in this case.
Stefano M wrote:
> Hi all,
> i'm trying to download a simple code on Spartan II Demo Board
> (by Insight) via JTAG cable.
> The problem is that iMPACT detects a xcv100 instead of
> xc2s100, warns me and if i go ahead and try to program
> i receive a lot of difference.
> This is the log (if it can be helpful...):
>
> Checking for System Ace MPM device...
> ----------------------------------------------------------------------
> Position PartName Version FileName
> 1 xc18v01 0 NOT YET ASSIGNED
> 2 xcv100 3 NOT YET ASSIGNED
> ----------------------------------------------------------------------
>
> Validating chain...
> Boundary-scan chain validated successfully.
> '2': IDCODE is '00110000011000010100000010010011'
> '2': IDCODE is '30614093' (in hex).
>
> Can someone help me to solve ?
> Thanks a lot,
> regards
> --
> Stefano Mora
> email: stefano.mora@*libero.it
> (remove *)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41973To tell you the truth, I don't really trust the gate count number Xilinx's MAP reports (MAP is one of the backend tools before PAR. (P&R)) because it counts RAM bits as "equivalent gates." (I personally call this "System Gate marketing.") Anyhow, if I totally trust the numbers MAP reports when I don't use Block RAM or Distributed RAM, I will say that Spartan-II XC2S150 has about 25,000 ASIC gates, and the largest XC2S200 has about 33,000 ASIC gates. If you don't care about 5V I/O, you can use the newer Spartan-IIE, which the biggest chip has 300,000 system gates. The system gate marketing seems to inflate the realistic gate count by a factor of 6, so the actual ASIC gates will be around 50,000. Also, when you say ASIC gates, do you mean, 1 ASIC gate = 1 NAND gate? (1 NAND gate I believe uses 4 transistors.) I am sure about the performance because it can vary by design. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Gil Herbeck wrote: > > Thanks. At least you have used Xilinx Spartan-II. I've never done > an FPGA and don't know Spartan-II from a Virtex from a ... (I'm an > ASIC guy). > > Maybe you can comment on capacity and performance with the Spartan-II? > > Gil >Article: 41974
On 10 Apr 2002 10:34:43 -0700, 13378988@qub.ac.uk (almost_a_gnome) wrote: >Hi Folks, > >I am having problems with the Virtex Block RAMs. I want to >implement a 4096 bit shift register using Virtex Block Rams. I >used a 12 bit counter to address a dual ported BlockRAM: >RAMB4_S1_S1. The write port is addressed by an output that is '1 >clock cycle' behind the counter's output. That way the >WRITE will occur 1 cycle behind the READ at any instance. >Whenever I simulate the circuit, I am getting the following >error each time the RAM address reaches 1024: >/*** >Memory Read - Exceeds memory Bounds >**/ >i.e. each time the 11th bit turn to 1, it complains about memory >bounds being exceeded although the RAM configuration is 4096x1 >bit!!?? > > >Any help??? Does setting this bit make the number negative? If the bits are numbered 11..0 , then the boundary is 2048, not 1024, and bit 11 makes it look negative if treated as a two's comp number. Philip Freidin Fliptronics
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