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In article <87adrfiwky.fsf@filestore.home.gustad.com>, newsmailcomp2@gustad.com says... > kayrock66@yahoo.com (Jay) writes: > > > It appears that on a fully utilized XC2V6000, there is no solution to > > be able to run the FPGA Editor. The program hits the 2GB memory limit > > and quits. How did Xilinx test there code? I know that the memory > > Maybe on a SUN UltraSPARC III under 64-bit Solaris :-) AMD's Hammers will be out soon. I'd give them the inside odds on success for the 64bit desktop. > I pray for a native ISE running under X86-64 Linux soon. Check out > http://www.x86-64.org. I'd go there, though it's a PITA to have multiple systems just to get things done. ---- KeithArticle: 42851
Hi all, In webpack 4.2 floorplanner, i can place a bunch of logic how i want, then group and bind it to make an RPM (relationally placed macro). At this point, you can move the whole block of parts as a unit. What i can't figure out, is how do you make this macro known to other vhdl files higher in the hierarchy? I can write the constraints to a .ucf or .mfp file, but when i recompile and open floor-planner for the next file up in the hierarchy, all the primitives are listed, but how do i get and place the previously built RPM macro instances? If i instantiated the lower level design 4 times, i should be able to place 4 'blocks' of parts. I know how to do it by manually editing the text .ucf files, but it's a bit tedious. Is every vhdl file in the project associated with its own .ucf and .mfp file, or are these just global options?Article: 42852
i have a doubt about the way the XST synthesis tool will intrepret the following code for a state machine : ( please ignore any syntax errors, the construction is more important) ....... --signal declarations process(......sensitivity list....) begin -- default signal assignment signal_1 <= '0'; signal_2 <= '1'; signal_3 <= '0'; -- conditional signal assignment --not all signals assigned in each state case curr_state is when state_1 => signal_1 <= '1'; next_state <= state_2; when state_2 => signal_3 <= '1'; next_state <= state_3; when state_3 => signal_3 <= '0'; next_state <= state_1; end case; end; well, the code is not for anything in particular, what i wanted to know was, since all signals are given "default" values, am i allowed to do something like what is done above, and not assign each output in each state, assuming that it will get its default value? This works in leo-spec, but will it also work in webpack4.2 ? we are using spartan2 xc2s50, by the way. thanks in anticipation --SumeetArticle: 42853
nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) writes: > Since the only reason why x86 survives is compatability and cost, why > would someone pay Ultrasparc prices for something which runs the old > code slowly? Since it's the only 64-bit architecture where you can run the Xilinx ISE 4.2i *today*... But hopefully that will change in the not so distant future. Altera tools might be available on X86-64 before Xilinx since they already have a native Linux version of Quartus II 2.0. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 42854
http://www.xilinx.com/xcell/xl31/xl31_32.pdf Noddy wrote: > > Hi, > > I am trying to design a high precision (30 bit) frequency synthesiser inside > a Spartan II. Of course, normal way to do this is with a charge pump, > voltage controlled oscillator and a phase lock loop. > > Can anyone point me to some good references? I have a very high precision > 5Mhz which is generated from a hydrogen maser and will be used as the input > clock signal. > > thanks > adrianArticle: 42855
Hi, The Xilinx LogiCORE program provides both T1/E1 Framer and T1 Deframer functions for communications applications. Please visit http://support.xilinx.com/ipcenter/ipevaluation/t1e1_framer_deframer_evaluation.htm Regds. SANKET. dainis@saftehnika.com wrote in message news:<aatfpd$qad$1@news.netmar.com>... > I am looking for PDH MUX (E2,E3) VHDL and > any frame (E1,T1,E2 ...) based device VHDL examples. > > Thanks. > Dainis > dainis@saftehnika.com > > > ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- > http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups > NewsOne.Net prohibits users from posting spam. If this or other posts > made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 42856
Hi, If you love saving board-space then go for Spartan-IIE instead of Spartan-XL. Get rid of the converters. Regards, SANKET. Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3CD2886F.F6A09686@egr.msu.edu>... > Hi, > I still need to get an answer to my original concern. I am > considering using the LVPECL capability of the Spartan2E to distribute a > clock signal at 102.4 MHz. The system consists of up to 34 boards. > Board 1 is a clock generator, board 2 sets sytem timing, and board 3 > thru 34 are counter/timer boards. Board 1 buffers the clock and > provides outputs to drive the other 33 board clock inputs. In the > current system board 1 is all LVPECL and the other boards use a > SpartanXL with an external LVPECL to LVTTL conversion for the clock. > (Clock is 204.8 MHz). In the new system I was considering using a > Spartan2E on the new board for the LVPECL outputs (and clock de-skewing) > and a Spartan2E on the other boards for the LVPECL input and the > clockDLL. After the last discussion, I am wondering if I should dump > the LVPECL clock distribution altogether and use LVCMOS or etc. > > Thanks, > TheronArticle: 42857
Hi, Take a risk for your FIFO memory;-) M and D can be any integer from 1 to 4096. The CLKFX Jitter Calculator is available on-line; it can be accessed from the interactive data sheet site at: http://www.xilinx.com/applications/web_ds/index_top.htm -> Virtex-II CLKFX Jitter Calculator The direct link is: http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm (NOTE: Generally, using CLKDV or CLK2X will allow better output jitter than using CLKFX.) One more thing---Once upon a time even you were a JUNIOR and were given a chance and so you are here. Regards, SANKET. "Martin E." <0_0_0_0_@pacbell.net> wrote in message news:<DZLA8.915$K%7.775202997@newssvr13.news.prodigy.com>... > A couple of problems: > > 1- SelectRAM being used for FIFO memory. > The application in question has the read side of the FIFO read input data in > packets. The input side signals the output side when packets are available. > No problems there. Under certain conditions (startup, reset, etc.) both the > write and read pointers will be looking at the same memory and the write > side will write a word. The read side, as I understand it, will either read > corrupt data or old data while parked at this address waiting for a packet > to be available. This is not a problem as long as valid data is actually > written to that initially common location such that when I go to use it, > some 128 writes later, the data read will be valid. > The Virtex II documentation isn't all that clear on this particular > condition. Anybody know if I'll have problems? > > 2- DCM frequency synth. > The Virtex II "Detailed Description" document states that the M and D > parameters have a range of 1 to 4095. Somebody at Xilinx is telling me that > the range is 2 to 32 ... he sounds like a junior guy 'cause he has to go > check and research every answer. > Could an experienced DCM end-user let me know which it is? Also, what is > the precision of the resulting frequency? If I set M to 2000 and D to 367 > and the input frequency is 25 MHz, what do I get? How much jitter? > > Thanks,Article: 42858
"Xilinx FAE from Insight SANKET" <sanket@insight.memec.co.in> schrieb im Newsbeitrag news:84bd8d50.0205050105.536b90a0@posting.google.com... > Hi, > Take a risk for your FIFO memory;-) > M and D can be any integer from 1 to 4096. I dont think so. AFAIK these where very preliminary numbers for the first silicone, and they where reduced to 2..32 in the series production. -- MfG FalkArticle: 42859
"Xilinx FAE from Insight SANKET" <sanket@insight.memec.co.in> schrieb im Newsbeitrag news:84bd8d50.0205050030.112dd3fa@posting.google.com... > dainis@saftehnika.com wrote in message news:<aatfpd$qad$1@news.netmar.com>... > > I am looking for PDH MUX (E2,E3) VHDL and > > any frame (E1,T1,E2 ...) based device VHDL examples. I was looking for such things too, a half year ago. Nothing found :-( -- MfG FalkArticle: 42860
HI, Better if you use a three process state-machine.That's how you are better-off. regds. SANKET. cavallino-rampante@mschumacher.com (Sumeet) wrote in message news:<67b681bf.0205042236.53df06f1@posting.google.com>... > i have a doubt about the way the XST synthesis tool will intrepret the > following code for a state machine : > > ( please ignore any syntax errors, the construction is more important) > > ....... > --signal declarations > > process(......sensitivity list....) > > begin > > -- default signal assignment > > signal_1 <= '0'; > signal_2 <= '1'; > signal_3 <= '0'; > > -- conditional signal assignment > --not all signals assigned in each state > > case curr_state is > > when state_1 => > signal_1 <= '1'; > next_state <= state_2; > > when state_2 => > signal_3 <= '1'; > next_state <= state_3; > > when state_3 => > signal_3 <= '0'; > next_state <= state_1; > end case; > > end; > > well, the code is not for anything in particular, what i wanted to > know was, since all signals are given "default" values, am i allowed > to do something like what is done above, and not assign each output in > each state, assuming that it will get its default value? > > This works in leo-spec, but will it also work in webpack4.2 ? > > we are using spartan2 xc2s50, by the way. > > thanks in anticipation > --SumeetArticle: 42861
> We've comitted to it (but haven't gotten it yet) I'm getting worried... Should > we have gone with NIOS??!? Don't worry ;) I've been waiting for my piece of Nios for 3 weeks. jerryArticle: 42862
cavallino-rampante@mschumacher.com (Sumeet) wrote in message news:<67b681bf.0205042236.53df06f1@posting.google.com>... > i have a doubt about the way the XST synthesis tool will intrepret the > following code for a state machine : > > ( please ignore any syntax errors, the construction is more important) > > ....... > --signal declarations > > process(......sensitivity list....) > > begin > > -- default signal assignment > > signal_1 <= '0'; > signal_2 <= '1'; > signal_3 <= '0'; > > -- conditional signal assignment > --not all signals assigned in each state > > case curr_state is > > when state_1 => > signal_1 <= '1'; > next_state <= state_2; > > when state_2 => > signal_3 <= '1'; > next_state <= state_3; > > when state_3 => > signal_3 <= '0'; > next_state <= state_1; > end case; > > end; > > well, the code is not for anything in particular, what i wanted to > know was, since all signals are given "default" values, am i allowed > to do something like what is done above, and not assign each output in > each state, assuming that it will get its default value? > > This works in leo-spec, but will it also work in webpack4.2 ? > > we are using spartan2 xc2s50, by the way. > > thanks in anticipation > --Sumeet I've done that for leonardo, but haven't run it in webpack yet. I've seen them say in books that just having defaults before the case statement is adequate. It is all procedural in a process statement, so should be ok.Article: 42863
I use Altera's LPM in my project,and I want to stimulate it by modelsim, but I do not know how to do because modelsim can not interpret the LPM?please help me,thanks.Article: 42864
Hold on...there is no need for a DDS (is there?). All I want to do is generate a +/- 32 MHz [down to mHz resolution] frequency output to be used as a clock frequency for the FPGA. What I need to do is generate this clock frequency using a 5MHz input signal. The 5 MHz clock is highly stable, generated by a hydrogen maser. If I was using Virtex II I could simply use the digital clock manager which appears to have a PLL inside it. Unforunately, I only have a Spartan II. I need the resolution to do coherent signal averaging. Adrian > > Manfred, you are describing DDS, Direct Digital Synthesis, and that can > give you > > impressive values for the average output frequency, down to milliHertz > > granularity. > > But you pay for that with output jitter. > > In the particular case, about 30 MHz was requested with mHz resolution. > > The period of 30 MHz is roughly 30 ns. The difference in period length for > a 1 > > Hz deviation is 1 femtosecond. For 1 mHz it is thousand times less... > > > > Running the phase accumulator at 500 MHz would create an output time > granularity > > of 2 ns. This means the output transition would often be up to 1 ns away > from > > the right moment. In other words, there is 1 ns of peak jitter, thousand > times > > the required timing resolution at 1 Hz granularity, a million times the > required > > resolution at 1mHz granularity. > > Why reinvent the wheel? The problem described here is common and , since it > is already present for a while, solved in many way. > > DDS can give you mHz resolution for almost no cost and phase continuity when > modulated. BUT you have a big amout of jitter when it comes to high > frequencyies (whatever high means here). > A classig analog PLL can give you superior jitter performance (ok, not the > best know to man, but much better than plain digital DDS). > So simply combine both. Generate a high frequency resolution using a DDS and > smooth out the jitter using an analog PLL. > There are special tricks possible to transform the jitter (phase noise) of > the DDS into high frequency regions, so it is easier for the PLL, to clean > up the signal. > > -- > MfG > Falk > > > >Article: 42865
"Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag news:1020608359.481993@turtle.ru.ac.za... > Hold on...there is no need for a DDS (is there?). All I want to do is > generate a +/- 32 MHz [down to mHz resolution] frequency output to be used So what do you mean with "mHz resolution" ? For me it sounds like that you need a clock generator, locked to the high stable 5Mhz clock, but which can be adjusted in its output frequency. This would require a DDS plus analog PLL to filter the jitter. Or do you just need a conversion from the 5Mhz to the 32 Mhz with the fixed frequency ratio? This would just take a analog PLL. -- MfG FalkArticle: 42866
I've received bug reports againts Icarus Verilog that the example below
does not ever generate a LOCKED output. I dug around the DCM module and
found taht the lock_period reg within the DCM module is never set. I dug
a little deeper and find that the only place that signal is set is here:
if (period < clkin_edge[0] - clkin_edge[1] - 500)
lock_period <= 0;
else if (period > clkin_edge[0] - clkin_edge[1] + 500)
lock_period <= 0;
else if ((clkin_edge[0] != 1'bx) && (clkin_edge[1] != 1'bx))
lock_period <= 1;
Now the astonishing bit of this is the "!= 1'bx" in the last if
statement. According to the Verilog standard, != is supposed to have
an unknown (x) value if there are unknown bits in the operands, and
in fact (clkin_edge[1] != 1'bx) has exactly that so can be reduced
to (1'bx). Therefore, the whole && expression reduces to (1'bx), the
if expression is never true and "lock_period <= 1;" never gets executed.
When I change the != to !== in this expression, the program below
does generate a lock_period, and Plocked gets set. The !== exists
to support comparisons of values that include x and z bits.
So what's the story here? I'm responding to bug reports against
Icarus Verilog, yet, while Icarus Verilog does have bugs, I think
this is not one of them; but people do occasionally want to simulate
this model. What do other Verilog compilers do with this?
`timescale 1ns / 1ps
module main;
wire PLocked;
wire clk0, clk2x;
reg clk_in;
always #5 clk_in = !clk_in;
wire PCLK;
buf #1 (PCLK, clk0);
DCM dcm3 (.CLKFB (PCLK),
.CLKIN (clk_in),
.DSSEN (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (1'b0),
.LOCKED (PLocked),
.CLK0 (clk0),
.CLK2X (clk2x));
initial $monitor("%t: clk_in=%b clk0=%b clk2x=%b PLocked=%b",
$time, clk_in, clk0, clk2x, PLocked);
endmodule // main
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
steve at picturel.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
abuse@xo.com
uce@ftc.gov
Article: 42867I just need a conversion from 5Mhz to an adjustable frequency ratio which will always be between 31.5 and 32.5 MHz. When I say mHz resolution, I mean I need to be able to set my 32 MHz frequency down to mHz accuracy ie. 32.031 Mhz, and of course there should be no jitter at this level of accuracy. I mentioned in earlier posts that it is quite easy to do it using an analogue PLL [an external VCO, a digital PLL and a large XOR gate to act as a charge pump to the VCO], however I was looking to see if it could be done digitally, thus reducing the need for external components. Adrian > So what do you mean with "mHz resolution" ? For me it sounds like that you > need a clock generator, locked to the high stable 5Mhz clock, but which can > be adjusted in its output frequency. This would require a DDS plus analog > PLL to filter the jitter. > Or do you just need a conversion from the 5Mhz to the 32 Mhz with the fixed > frequency ratio? This would just take a analog PLL. > > -- > MfG > Falk >Article: 42868
Noddy wrote: > > I just need a conversion from 5Mhz to an adjustable frequency ratio which > will always be between 31.5 and 32.5 MHz. When I say mHz resolution, I mean > I need to be able to set my 32 MHz frequency down to mHz accuracy ie. > 32.031 Mhz, and of course there should be no jitter at this level of > accuracy. What you have written here, has 1 KHz LSB. When you write mHz, and MHz, most readers assume MilliHertz (32031000.001Hz ), and MegaHertz (32MHz) Digital solutions, by nature, are quantized, so must have jitter. For 32MHz / 1KHz LSB, a 74HC4046 or derivatives should be a good starting point. -jgArticle: 42869
"Xilinx FAE from Insight SANKET" <sanket@insight.memec.co.in> wrote in message news:84bd8d50.0205050105.536b90a0@posting.google.com... > One more thing---Once upon a time even you were a JUNIOR and were > given a chance and so you are here. Just to clarify, the term "junior" was not used as a pejorative at all. The bottome line is that I need current information because it affects electrical design. I am new to FPGA's myself, so you could call me a "junior" in that regard just as well ... and that's the more reason to obtain accurate information. The data sheet I got off the Xilinx site, document DS031-2 (v1.3) dated January 25, 2001, calls out a range of 1 to 4095 for M and D. If this is not true, and the range is 2 to 32, I will have to use externally generated clocking. Being that the board goes to layout next week ... Thanks for your input. -- Martin E. To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 42870
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:ab2utp$es5mh$1@ID-84877.news.dfncis.de... > > M and D can be any integer from 1 to 4096. > I dont think so. AFAIK these where very preliminary numbers for the first > silicone, and they where reduced to 2..32 in the series production. I guess I'll plan for external clocks just in case. Nobody seems to have a straight answer on this one. If the DCM's don't work for me I'll just revert back to external oscillators. -- Martin E. To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 42871
Martin, I am very sorry that you got mislead. Here is the official answer: Xilinx supports and gurantees any M and D value (in any combination) between 2 and 32. 4096 was an original intent that is clearly impossible to meet. I will check our web-sites and make sure we eradicate any "4096". It was a nice idea, but it has no chance of being real :-( Peter Alfke, Xilinx Application "Martin E." wrote: > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:ab2utp$es5mh$1@ID-84877.news.dfncis.de... > > > > M and D can be any integer from 1 to 4096. > > > I dont think so. AFAIK these where very preliminary numbers for the first > > silicone, and they where reduced to 2..32 in the series production. > > I guess I'll plan for external clocks just in case. Nobody seems to have a > straight answer on this one. If the DCM's don't work for me I'll just > revert back to external oscillators. > > -- > Martin E. > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 42872
Loi, the highest Vccio for that part is 3.3 V. The inputs are 5-V tolerant, so there is no problem receiving data from a 5-V CMOS device. The Spartan-II outputs can, obviously, not actively pull higher than their own supply voltage, which might be as low as 3.0 V. If the device you are driving has CMOS-type ( not TTL-type) input thresholds, this interface is marginal at best, most likely unreliable. Your solution can be to 3-state the Spartan-II outputs and use an external pull-up resistor to 5V. That is a reliable albeit slow interface, sensitive to capacitive loading when the pull-up resistor is a few hundred ohms. If you are interested in higher speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask me for it. Peter Alfke, Xilinx Applications ( writing from home) peter@xilinx.com Loi Tran wrote: > I need someone to explain to me which IBUF/OBUFs I should be using for 5V CMOS > interfacing. The part I'm using is XC2S200PQ208-5. I would appreciate any > and all help that comes my way. > > Thank you. > > LTArticle: 42873
On Mon, 06 May 2002 00:15:42 GMT, Peter Alfke <palfke@earthlink.net> wrote: >That is a reliable albeit slow interface, sensitive to capacitive loading when >the pull-up resistor is a few hundred ohms. If you are interested in higher >speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask >me for it. OK, Peter, what is the trick circuit? JohnArticle: 42874
It's a bit tedious in words: Put an external pull-up to 5 V on the pin. Drive the output signal as usual. Now comes the trick: Drive the output T signal ( Tristate active High) with an AND of the internal data signal AND the input signal coming from your output. (Remember, any pin is always an input) When you drive a Low output, the buffer is active (T is Low). When you start driving a High output, the buffer remains active until the output pin is crossing the threshold. Then the AND goes true, and the output goes 3-state. That means you got an active (<10 Ohm) output helping you on the way up. Obviously, it is in your interest to delay the input signal from reaching the AND gate too soon. You cannot get any help >3.3 V, but you may get a much faster rise time for the first 2 to 2.5 V, and that reduces the rising delay significantly. The falling delay is short anyway. Peter Alfke, Xilinx Applications ============================ John Larkin wrote: > On Mon, 06 May 2002 00:15:42 GMT, Peter Alfke <palfke@earthlink.net> > wrote: > > >That is a reliable albeit slow interface, sensitive to capacitive loading when > >the pull-up resistor is a few hundred ohms. If you are interested in higher > >speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask > >me for it. > > OK, Peter, what is the trick circuit? > > John
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