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Messages from 46200

Article: 46200
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: "Barry Brown" <barry_brown@agilent.com>
Date: Wed, 21 Aug 2002 13:52:41 -0700
Links: << >>  << T >>  << A >>
Ray -
Really?  Perhaps I'm missing something then.  When the two lines are
commented out, Synplify gives me a warning:

@W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box

I thought that sounded bad, but do you mean I can just ignore it?
I tried it, and the Xilinx P&R works fine, so I guess all is right with the
world.  So then what does Synplify include that Virtex library for?

Thanks,
Barry

"Ray Andraka" <ray@andraka.com> wrote in message
news:3D62B4D4.6739AA63@andraka.com...
> you don't need those two lines for synplify either. Just leave them out.
>
> Barry Brown wrote:
>
> > I need to use some Xilinx primitives in my VHDL, and they seem to be in
> > different libraries for use with ModelSim and Synplify.  Here's what I
have
> > so far...
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_unsigned.all;
> > -- synthesis translate_off
> > library unisim;
> > use unisim.all;
> > -- synthesis translate_on
> > library virtex;
> > use virtex.components.all;
> > ...
> >
> > This works fine in Synplify, but for ModelSim I have to comment out the
two
> > lines...
> >
> > --library virtex;
> > --use virtex.components.all;
> >
> > Does anyone know a better way to "hide" these from ModelSim?
> >
> > Thanks,
> > Barry Brown
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 46201
Subject: Re: Logic Analyzers with an Altera Board
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 21 Aug 2002 14:04:45 -0700
Links: << >>  << T >>  << A >>
> I have a prototyping board from Altera for testing my design. I'm new
> to using a prototype board and hence had some questions. The device in
> the prototype board is a EP20K1500E.
> Does anyone have views on whether I would need a logic analyzer with
> this board ? 


If you keep your design synchronous and do a good job with simulation
you might not need a logic analyzer. You will need a scope to
check activity on clock, reset etc.

> Do people who use prototype boards always use analyzers ?


Some love them and use them all the time.
Some hate them and only roll them out only when completely stumped.

If the board has all the interfaces you need to prove that
your design works, just do it.


> Is there an alternate way out without using analyzers ? Any
> recommendation on which logic analyzer should I use ?


I think your money is better spent on good simulation
and synthesis tools.

    -- Mike Treseler


Article: 46202
Subject: Re: Huge discrepanzcy between gate-array and standard cell synthesis
From: johne@vcd.hp.com (John Eaton)
Date: 21 Aug 2002 21:29:25 GMT
Links: << >>  << T >>  << A >>
HenningB (HenningBahr@web.de) wrote:
: Hi all,

: I have designed a simple frequency divider, existing mainly of 15
: flip-flops. Ambit BuildGates is my synthesis tool. I am getting the
: following results when my target technology is a 300k gate-array
: technology from LSI:

: Worst path delay: 1.73 ns
: Cell Area:    279

: And these are the results when using a standard-cell 0.35 um
: technology:

: Worst path delay: 1.92 ns
: Cell Area:	13,304

: Why is there such a huge discrepancy between the cell areas?
: I expected the standard-cell to be faster. 
: My explanation for the faster gate-array implementation: it takes only
: the gate delay into account not any wiring. Am I right?
: Does the worst path delay only exist of the combinational part? (the
: tool only highlights the combinational logic)

: Cheers,
: Henning


Not sure about BG but in synopsys the area is in whatever units the lib builder
felt like using. Area comparisons between two different technologies is meaningless.

John Eaton
 

Article: 46203
Subject: Re: Academics vs 'real' FPGA use
From: Buddy Smith <nullset@dookie.net>
Date: Wed, 21 Aug 2002 21:33:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kevin Brace <killspam4kevinbraceusenet@killspam4hotmail.com> wrote:
> 
> 

>        Austin, have you even seen any 3D graphics chip vendors using
> FPGA for production?

First, let me say thanks to those of you who have replied to this post.  
I'm enjoying it :)

Now, to respond to this....

A friend of mine interned at NVIDIA for the summer, and told me that they 
use ~$5 million FPGAs for simulation of designs before they send them to 
the fab.  The FPGAs they use even have AGP ports....

I thought this was very interesting.

> No wonder I see almost no one using FPGA for PC related applications
> (i.e., CPU, graphics chip, chipset, etc.) other than for prototyping.
> 

Yup...I can definitely see FPGAs being used for prototyping, even in cases 
where I couldn't imagine it.

Thanks again for the responses all.  If you're looking for a soon-to-be 
graduating computer engineer, feel free to contact me via email for a 
resume.

--buddy

-- 
-----BEGIN GEEK CODE BLOCK-----
Version: 3.12 GE d- s:- a-- C+++ UL P++++ L+++ E- W+ N++ o-- K- w-- O---- 
M- V- PS-- PE Y+ PGP t+ 5 X R tv+ b DI++++ D G e h r++ y- 
------END GEEK CODE BLOCK------

Article: 46204
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: Ken McElvain <ken@synplicity.com>
Date: Wed, 21 Aug 2002 21:48:32 GMT
Links: << >>  << T >>  << A >>
Some components are simple and a component declaration is enough.  Some
require a bit more information to interpret, which is stored as 
attributes in the package.  This might include information used in
DRC checking such as which pins are tristate.  If you want to
instantiate a LUT4 then you will need the package.  The package
file lives at .../synplify/lib/xilinx/virtex.vhd

In your case nothing more is needed and your component declaration
is all you need.

- Ken

Barry Brown wrote:

> Ray -
> Really?  Perhaps I'm missing something then.  When the two lines are
> commented out, Synplify gives me a warning:
> 
> @W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box
> 
> I thought that sounded bad, but do you mean I can just ignore it?
> I tried it, and the Xilinx P&R works fine, so I guess all is right with the
> world.  So then what does Synplify include that Virtex library for?
> 
> Thanks,
> Barry
> 
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D62B4D4.6739AA63@andraka.com...
> 
>>you don't need those two lines for synplify either. Just leave them out.
>>
>>Barry Brown wrote:
>>
>>
>>>I need to use some Xilinx primitives in my VHDL, and they seem to be in
>>>different libraries for use with ModelSim and Synplify.  Here's what I
>>>
> have
> 
>>>so far...
>>>
>>>library ieee;
>>>use ieee.std_logic_1164.all;
>>>use ieee.std_logic_unsigned.all;
>>>-- synthesis translate_off
>>>library unisim;
>>>use unisim.all;
>>>-- synthesis translate_on
>>>library virtex;
>>>use virtex.components.all;
>>>...
>>>
>>>This works fine in Synplify, but for ModelSim I have to comment out the
>>>
> two
> 
>>>lines...
>>>
>>>--library virtex;
>>>--use virtex.components.all;
>>>
>>>Does anyone know a better way to "hide" these from ModelSim?
>>>
>>>Thanks,
>>>Barry Brown
>>>
>>--
>>--Ray Andraka, P.E.
>>President, the Andraka Consulting Group, Inc.
>>401/884-7930     Fax 401/884-7950
>>email ray@andraka.com
>>http://www.andraka.com
>>
>> "They that give up essential liberty to obtain a little
>>  temporary safety deserve neither liberty nor safety."
>>                                          -Benjamin Franklin, 1759
>>
>>
>>
> 
> 


Article: 46205
Subject: Re: Academics vs 'real' FPGA use
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 21 Aug 2002 15:03:34 -0700
Links: << >>  << T >>  << A >>
Paul,

If you can find a standard off the shelf chip that does everything you need, more
power to you!

But beware the competion if it is that easy.

Austin

Paul wrote:

> In article <3D63AC3F.DA644BC1@xilinx.com>, Austin Lesea
> <austin.lesea@xilinx.com> wrote:
>
> > Paul,
> >
> > What FPGA you learned on has nothing to do with where the opportunities
> will be.
> >
> > There are people working for me who have used Altera FPGAs before they came
> > here.  Nothing wrong with that.  When you sell a part that wakes up everytime,
> > and asks "what will I be today?" it is hard to say how the chips get
> used unless
> > someone goes out and researches all of the applications (see below).
> >
> > To say that a front runner part like Virtex II has won XX,000 sockets implies
> > XX,000 different applications among a lot of different customers.
> >
> > If you ask an ASIC designer today about what they are doing, you will
> find that
> > they are a bit jealous of what we are doing: .13u, nine metal layers, power pc
> > from IBM, multi-gigbit transceivers, all copper process, low K
> dielectrics, etc.
> > etc. etc.  Most ASIC designers are working with two year old technology,
> > grinding out the standard stuff (graphics controllers, memory
> controllers, disc
> > controllers) yet again, and again.
> >
> > And, by the way, we are now working on the next generation(s) beyond .13u...
> >
> > So the FPGA user engineer at our customers is in a bit of an interesting
> > situation:  they get to use technologies that are two or even three
> years ahead
> > of the ASIC designer....so who is playing with the coolest toys now?
> >
> > I am sure the FPGA you had in school was a few years old, and hence
> regarded as
> > something good to learn on, but not seriously to be thought of as something
> > "hi-tech."  But FPGAs today have become more than just "glue" and are now
> > finding themselves at the heart of a system due to their capabilites.
> >
> >  http://www.xilinx.com/xcell/xl30/xl30_10.pdf
> >
> > I wrote it over four years ago, but it has come true far sooner than I would
> > have ever believed.
> >
> >  http://www.xilinx.com/company/success/index.htm
> >
> > We go find people who use the chips, and are happy and successful.
> >
> > Austin
> >
>
> Austin:
>
> I was attempting to provide some perspective as a board designer, as to what
> people in the "real" world do with FPGAs. Certainly, the original poster can
> tell from reading the posts in this group, as to what people are doing with
> FPGAs. In my case, I've worked in an environment where they are used as glue,
> and I've also worked in a startup, where an entire card was based on
> nothing but FPGAs and DDR / QDR memories.
>
> I don't think the original poster was attempting to dump on X or A. A lot of
> people choose Xilinx or Altera, based on their familiarity with a particular
> design flow, so the choice wasn't based on nanoseconds, it was based on a
> GUI.
>
> As a new graduate, the original poster (Buddy) will have to choose what kind
> of career path to take. At one time, a board designer did designs with discrete
> logic ("jelly beans"), so the board designer had to spec and design all the
> logic, frequently without the aid of nifty synthesis tools. Board design now,
> is all about glueing the right large ASICs together, to achieve an objective.
> There isn't enough time to understand all of the operation of the devices, as
> the spec sheets for a large board can total a couple thousand pages of paper.
> If you are lucky, you get enough time to do the interface timing and that's it.
> That is why I referred to throwing the devices on the board, and leaving it
> to the software team to make it work.
>
> If Buddy enjoys designing blocks of logic, then working first as an end user
> of FPGAs gives an opportunity to become familiar with specing and designing
> logic. FPGA design makes a good lead-in to ASIC design, as the learning curve
> will be easier with FPGAs as a first step. No ASIC design team is going to
> take a new grad with no experience, and give him or her a significant portion
> of a chip to design, with all the schedule pressures inherent. A small FPGA
> design, on the other hand, allows someone new to logic design to get their
> feet wet, while minimizing the risk to the overall project.
>
> As to the original question...
>
>   Can someone point me to a text, or website that contains information about
>   real world applications of FPGAs?
>
> I don't think a single web site is going to do that for you. If you visited
> opencores.org, for example, you would see examples of intellectual property
> donated by designers, but 99% of all design is jealously guarded by
> the companies that paid for it. Going to the X or A website isn't going to
> help, because the IP they are selling is going to be popular, commodity stuff.
> A site like fpgacpu.org gives some ideas, but would those ideas appear in
> commercial products ?
>
> The best source of ideas is probably reading this newsgroup!
>
> As to this comment...
>
> > I am sure the FPGA you had in school was a few years old, and hence
> regarded as
> > something good to learn on, but not seriously to be thought of as something
> > "hi-tech."  But FPGAs today have become more than just "glue" and are now
> > finding themselves at the heart of a system due to their capabilites.
>
> They may be the heart of a system to you, but if I can find an off-the-shelf
> device that solves my problem, why would I mess with an FPGA ? It can take
> an army of people to design systems on a chip. In my example above, where a
> board was constructed of nothing but FPGAs and DDR / QDR memory, there were
> two board designers and around fifteen FPGA designers. Does that sound like
> a cheap way to design things ? Imagine how many units I would have to sell
> to pay for the engineering!
>
>          Paul


Article: 46206
Subject: Re: Xilinx tools: which one? Esp. schematic
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Aug 2002 22:03:49 GMT
Links: << >>  << T >>  << A >>
I wonder if models for all the primitives are there, or is it missing working
models for SRL16s and Dual port BRAMs?  As I recall they had reached an impasse
with Viewlogic around 1999 or so where viewlogic had to change something to
allow those peices to simulate and viewlogic didn't want to do it.  At the time,
Xilinx pretty much said, use HDL for virtex if you are going to use the
features.  Try running a simulation on something that twiddles the address bits
of an SRL16.  If that works, then someone woke up and fixed it.  If, as I
suspect it doesn't, then you have a very crippled simulation if you are going to
take advantage of the architecture.

Austin Franklin wrote:

> Hi,
>
> I tried a small V2P design today in Viewdraw, and it went all the way
> through the tools, and I pushed down to the simulation models, and they were
> there (though I didn't run a simulation yet)...so I believe, at least to
> some level, this works.  There was even a symbol for the PowerPC...but I
> didn't explore that too much, though I think I might.  I wonder if there's a
> simulation model for that...there was both a VHDL and a Verilog selection
> for the PPC...
>
> Regards,
>
> Austin
>
>

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46207
Subject: Re: Logic Analyzers with an Altera Board
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Aug 2002 22:08:35 GMT
Links: << >>  << T >>  << A >>
I agree with Mike here.   A good simulation and sound design analysis will
get you a bunch further than any logic analyzer could, especially
considering that the only signals available to the analyzer are those
outside the chip (yes you can use ILA, but that comes at a price too, and
the reroute can change the performance enough to make a problem that wan't
appear or a real problem go away).   I've always taken the attitude that
extra time spent verifying the design before going to chip saves about 10x
that amount of time spent in the lab, often in an uncomfortable he-said
she-said situation.

Mike Treseler wrote:

> > I have a prototyping board from Altera for testing my design. I'm new
> > to using a prototype board and hence had some questions. The device in
> > the prototype board is a EP20K1500E.
> > Does anyone have views on whether I would need a logic analyzer with
> > this board ?
>
> If you keep your design synchronous and do a good job with simulation
> you might not need a logic analyzer. You will need a scope to
> check activity on clock, reset etc.
>
> > Do people who use prototype boards always use analyzers ?
>
> Some love them and use them all the time.
> Some hate them and only roll them out only when completely stumped.
>
> If the board has all the interfaces you need to prove that
> your design works, just do it.
>
> > Is there an alternate way out without using analyzers ? Any
> > recommendation on which logic analyzer should I use ?
>
> I think your money is better spent on good simulation
> and synthesis tools.
>
>     -- Mike Treseler

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46208
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Aug 2002 22:12:03 GMT
Links: << >>  << T >>  << A >>
The xilinx software looks for the edifs for any black boxes in the netlist.
Any that are primitives are already known by xilinx, so they go through the
tools jsut fine.  You can avoid the Synplicity nastygrams by putting the
syn_black_box attribute on any primitive components.  I never figured out why
synplicity has their own virtex library.  It conflicts with unisim, and
requires a special compile in order to simulate it.  FWIW, I was stumped by the
same problem when I started out with synplify many maintenance payments ago.

Barry Brown wrote:

> Ray -
> Really?  Perhaps I'm missing something then.  When the two lines are
> commented out, Synplify gives me a warning:
>
> @W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box
>
> I thought that sounded bad, but do you mean I can just ignore it?
> I tried it, and the Xilinx P&R works fine, so I guess all is right with the
> world.  So then what does Synplify include that Virtex library for?
>
> Thanks,
> Barry
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D62B4D4.6739AA63@andraka.com...
> > you don't need those two lines for synplify either. Just leave them out.
> >
> > Barry Brown wrote:
> >
> > > I need to use some Xilinx primitives in my VHDL, and they seem to be in
> > > different libraries for use with ModelSim and Synplify.  Here's what I
> have
> > > so far...
> > >
> > > library ieee;
> > > use ieee.std_logic_1164.all;
> > > use ieee.std_logic_unsigned.all;
> > > -- synthesis translate_off
> > > library unisim;
> > > use unisim.all;
> > > -- synthesis translate_on
> > > library virtex;
> > > use virtex.components.all;
> > > ...
> > >
> > > This works fine in Synplify, but for ModelSim I have to comment out the
> two
> > > lines...
> > >
> > > --library virtex;
> > > --use virtex.components.all;
> > >
> > > Does anyone know a better way to "hide" these from ModelSim?
> > >
> > > Thanks,
> > > Barry Brown
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46209
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Aug 2002 22:14:03 GMT
Links: << >>  << T >>  << A >>
Ken,

You can also instantiate LUT4's the same way, provided you put a user attribute
(INIT=) on it and add a pragma'd out generic for the init for simulation.



Ken McElvain wrote:

> Some components are simple and a component declaration is enough.  Some
> require a bit more information to interpret, which is stored as
> attributes in the package.  This might include information used in
> DRC checking such as which pins are tristate.  If you want to
> instantiate a LUT4 then you will need the package.  The package
> file lives at .../synplify/lib/xilinx/virtex.vhd
>
> In your case nothing more is needed and your component declaration
> is all you need.
>
> - Ken
>
> Barry Brown wrote:
>
> > Ray -
> > Really?  Perhaps I'm missing something then.  When the two lines are
> > commented out, Synplify gives me a warning:
> >
> > @W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box
> >
> > I thought that sounded bad, but do you mean I can just ignore it?
> > I tried it, and the Xilinx P&R works fine, so I guess all is right with the
> > world.  So then what does Synplify include that Virtex library for?
> >
> > Thanks,
> > Barry
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:3D62B4D4.6739AA63@andraka.com...
> >
> >>you don't need those two lines for synplify either. Just leave them out.
> >>
> >>Barry Brown wrote:
> >>
> >>
> >>>I need to use some Xilinx primitives in my VHDL, and they seem to be in
> >>>different libraries for use with ModelSim and Synplify.  Here's what I
> >>>
> > have
> >
> >>>so far...
> >>>
> >>>library ieee;
> >>>use ieee.std_logic_1164.all;
> >>>use ieee.std_logic_unsigned.all;
> >>>-- synthesis translate_off
> >>>library unisim;
> >>>use unisim.all;
> >>>-- synthesis translate_on
> >>>library virtex;
> >>>use virtex.components.all;
> >>>...
> >>>
> >>>This works fine in Synplify, but for ModelSim I have to comment out the
> >>>
> > two
> >
> >>>lines...
> >>>
> >>>--library virtex;
> >>>--use virtex.components.all;
> >>>
> >>>Does anyone know a better way to "hide" these from ModelSim?
> >>>
> >>>Thanks,
> >>>Barry Brown
> >>>
> >>--
> >>--Ray Andraka, P.E.
> >>President, the Andraka Consulting Group, Inc.
> >>401/884-7930     Fax 401/884-7950
> >>email ray@andraka.com
> >>http://www.andraka.com
> >>
> >> "They that give up essential liberty to obtain a little
> >>  temporary safety deserve neither liberty nor safety."
> >>                                          -Benjamin Franklin, 1759
> >>
> >>
> >>
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46210
Subject: Is this asynchronous design safe ?
From: TED <ted_jmt@zapta.com>
Date: Wed, 21 Aug 2002 22:14:46 GMT
Links: << >>  << T >>  << A >>

Our VHDL model contains a small synchronous portion which I am not
sure if is glitch safe so any comment or suggestion will be greatly
appreciated. 

The chip does not have a continuous clock and therefore it will be
costly to convert this portion of the chip  to an asynchronous design
(the rest of the chip receives an external clock pulse when it need to
change state).

We are currently using this design with Altera FPGA and plan to switch
in a month or two to a more hardwired solution such as Atmel ULC or
ChipExpress.

The file below shows the principle operation of the asynchronous
portion. The flip flop q has two 'set' inputs which are qualified by
two 'enable' inputs respectively. The set operation should happen only
when set1 (set2) is high while en1 (en2) is high.

Is it possible that the synthesizer will generate a circuit that will
have glitches while let's say en1 is low and set1 changes state ?  If
so, is there a safer way to do that ?

Any comment will be greatly appreciated.

Thanks,

Tal



========================



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;


library work;



entity temp is

    Port (set1, set2        : in      std_logic;
          en1,  en2         : in      std_logic;
          reset             : in      std_logic;
		  clk               : in      std_logic;
		  data              : in      std_logic;
          q                 : out     std_logic);

end temp;



architecture temp_arc of temp is

begin

  process (set1, set2, en1, en2, reset)

  begin

    if (set1 = '1' and en1 = '1') then
       q <= '1';

    elsif (set2 = '1' and en2 = '1') then
       q <= '1';

    elsif (reset = '1') then
       q <= '0';

    elsif (clk'event and clk='1') then
       q <= data;

	end if;

   end process;

end temp_arc;



Article: 46211
Subject: Re: What's wrong with clearLogic?
From: "Pete Ormsby" <faepeteDELETETHIS@attbi.com>
Date: Wed, 21 Aug 2002 22:15:35 GMT
Links: << >>  << T >>  << A >>
http://www.altera.com/corporate/news_room/releases/corporate/nr-clearlogic.h
tml


Leon Qin <lyqin@cti.com.cn> wrote in message
news:23c59085.0208210006.3cb6905a@posting.google.com...
> http://www.clear-logic.com/



Article: 46212
Subject: Re: Is this asynchronous design safe ?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Aug 2002 22:22:50 GMT
Links: << >>  << T >>  << A >>
I wouldn't leave this up to the synthesis at all.  At a very minimum code
to each LUT and put a keep buffer on the LUT output.  Be extremely careful
of both static and dynamic hazards, as the path timing is waiting to bite
you there.  Bottom line is yes, it can be done....if you are very very
careful.  You'll also have to do the timing analysis by hand because the
static timing analyzer will throw any combinatorial loops away before it
starts.  I would also suggest floorplanning it to at least have a fighting
chance of getting something more or less the same on every run of the
tools (the routing may still vary), and it would be wise to keep it
somewhat isolated so that you get inconsistency due to different routing
solutions caused by local congestion.

TED wrote:

> Our VHDL model contains a small synchronous portion which I am not
> sure if is glitch safe so any comment or suggestion will be greatly
> appreciated.
>
> The chip does not have a continuous clock and therefore it will be
> costly to convert this portion of the chip  to an asynchronous design
> (the rest of the chip receives an external clock pulse when it need to
> change state).
>
> We are currently using this design with Altera FPGA and plan to switch
> in a month or two to a more hardwired solution such as Atmel ULC or
> ChipExpress.
>
> The file below shows the principle operation of the asynchronous
> portion. The flip flop q has two 'set' inputs which are qualified by
> two 'enable' inputs respectively. The set operation should happen only
> when set1 (set2) is high while en1 (en2) is high.
>
> Is it possible that the synthesizer will generate a circuit that will
> have glitches while let's say en1 is low and set1 changes state ?  If
> so, is there a safer way to do that ?
>
> Any comment will be greatly appreciated.
>
> Thanks,
>
> Tal
>
> ========================
>
> library IEEE;
>
> use IEEE.STD_LOGIC_1164.ALL;
>
> library work;
>
> entity temp is
>
>     Port (set1, set2        : in      std_logic;
>           en1,  en2         : in      std_logic;
>           reset             : in      std_logic;
>                   clk               : in      std_logic;
>                   data              : in      std_logic;
>           q                 : out     std_logic);
>
> end temp;
>
> architecture temp_arc of temp is
>
> begin
>
>   process (set1, set2, en1, en2, reset)
>
>   begin
>
>     if (set1 = '1' and en1 = '1') then
>        q <= '1';
>
>     elsif (set2 = '1' and en2 = '1') then
>        q <= '1';
>
>     elsif (reset = '1') then
>        q <= '0';
>
>     elsif (clk'event and clk='1') then
>        q <= data;
>
>         end if;
>
>    end process;
>
> end temp_arc;

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46213
Subject: Re: Logic Analyzers not required with Xilinx Boards....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 21 Aug 2002 15:32:39 -0700
Links: << >>  << T >>  << A >>

--------------0B5A2FEAB929320AA6A262E7
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

and....

Some people use Xilinx ChipScope ILA with their Xilinx FPGAs and never have
this problem.

 http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?iLanguageID=1&iCountryID=1&title=chipscope_ila

Austin

Mike Treseler wrote:

> > I have a prototyping board from Altera for testing my design. I'm new
> > to using a prototype board and hence had some questions. The device in
> > the prototype board is a EP20K1500E.
> > Does anyone have views on whether I would need a logic analyzer with
> > this board ?
>
> If you keep your design synchronous and do a good job with simulation
> you might not need a logic analyzer. You will need a scope to
> check activity on clock, reset etc.
>
> > Do people who use prototype boards always use analyzers ?
>
> Some love them and use them all the time.
> Some hate them and only roll them out only when completely stumped.
>
> If the board has all the interfaces you need to prove that
> your design works, just do it.
>
> > Is there an alternate way out without using analyzers ? Any
> > recommendation on which logic analyzer should I use ?
>
> I think your money is better spent on good simulation
> and synthesis tools.
>
>     -- Mike Treseler



Article: 46214
Subject: Re: I2C License
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 22 Aug 2002 10:43:43 +1200
Links: << >>  << T >>  << A >>
Davis Moore wrote:
> 
> Kolja Sulimma wrote:
> 
> [snip]
> 
> >
> > The above only applies to techniques that are required to use the
> > chip. So you can assume that you licensed the memory bus, but if there
> > is an MP3 application not for the processor you do not own an MP3
> > license.
> >
> > Kolja Sulimma
> 
> This is the only area where I have personal experience with this
> issue. I made an MP3 player in school a few years back and I used
> the MP3 decoder chip from MAS Electronics (I think). I looked into
> the licensing issues since at that time the body that owned the
> MP3 encoding/decoding technology was getting sensitive about
> the use of their technology. Anyways, to the point, MAS Electronics
> (or whatever the company was) paid the royalties for the MP3 decoding
> technology. Anyone who bought the chips were free to integrate
> the chips into whatever product. Now, interestingly enough, the
> particular MP3 decoder chip I used was controlled via I2C
> interface. My controller was implemented in a CPLD so I looked for
> but did not find any information covering legal issues of integrating
> master or slave I2C devices in a product.

 i2c masters are, and have been, implemented in Software, in 
generic Microcontrollers, by the truckload around the world 
for decades.
 i2c Software Slaves are not as common, but still finite.

 Given that SW compiled for a CPLD, and SW compiled for a uC have to 
be on an identical legal footing ( comments anyone ? )
that gives a vast sea of (pre) existing use cases to quote.

- jg

Article: 46215
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 22 Aug 2002 00:11:08 GMT
Links: << >>  << T >>  << A >>
That is partially true.  If you do it the way I suggested, then Synplify
will have a proper timing model for the LUT instead of treating it like
an unknown black box.  In both cases, Synplify will not modify the
LUT, but the correct timing model will lead to improved timing of paths
through the LUT.

Ray Andraka wrote:

> Ken,
> 
> You can also instantiate LUT4's the same way, provided you put a user attribute
> (INIT=) on it and add a pragma'd out generic for the init for simulation.
> 
> 
> 
> Ken McElvain wrote:
> 
> 
>>Some components are simple and a component declaration is enough.  Some
>>require a bit more information to interpret, which is stored as
>>attributes in the package.  This might include information used in
>>DRC checking such as which pins are tristate.  If you want to
>>instantiate a LUT4 then you will need the package.  The package
>>file lives at .../synplify/lib/xilinx/virtex.vhd
>>
>>In your case nothing more is needed and your component declaration
>>is all you need.
>>
>>- Ken
>>
>>Barry Brown wrote:
>>
>>
>>>Ray -
>>>Really?  Perhaps I'm missing something then.  When the two lines are
>>>commented out, Synplify gives me a warning:
>>>
>>>@W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box
>>>
>>>I thought that sounded bad, but do you mean I can just ignore it?
>>>I tried it, and the Xilinx P&R works fine, so I guess all is right with the
>>>world.  So then what does Synplify include that Virtex library for?
>>>
>>>Thanks,
>>>Barry
>>>
>>>"Ray Andraka" <ray@andraka.com> wrote in message
>>>news:3D62B4D4.6739AA63@andraka.com...
>>>
>>>
>>>>you don't need those two lines for synplify either. Just leave them out.
>>>>
>>>>Barry Brown wrote:
>>>>
>>>>
>>>>
>>>>>I need to use some Xilinx primitives in my VHDL, and they seem to be in
>>>>>different libraries for use with ModelSim and Synplify.  Here's what I
>>>>>
>>>>>
>>>have
>>>
>>>
>>>>>so far...
>>>>>
>>>>>library ieee;
>>>>>use ieee.std_logic_1164.all;
>>>>>use ieee.std_logic_unsigned.all;
>>>>>-- synthesis translate_off
>>>>>library unisim;
>>>>>use unisim.all;
>>>>>-- synthesis translate_on
>>>>>library virtex;
>>>>>use virtex.components.all;
>>>>>...
>>>>>
>>>>>This works fine in Synplify, but for ModelSim I have to comment out the
>>>>>
>>>>>
>>>two
>>>
>>>
>>>>>lines...
>>>>>
>>>>>--library virtex;
>>>>>--use virtex.components.all;
>>>>>
>>>>>Does anyone know a better way to "hide" these from ModelSim?
>>>>>
>>>>>Thanks,
>>>>>Barry Brown
>>>>>
>>>>>
>>>>--
>>>>--Ray Andraka, P.E.
>>>>President, the Andraka Consulting Group, Inc.
>>>>401/884-7930     Fax 401/884-7950
>>>>email ray@andraka.com
>>>>http://www.andraka.com
>>>>
>>>>"They that give up essential liberty to obtain a little
>>>> temporary safety deserve neither liberty nor safety."
>>>>                                         -Benjamin Franklin, 1759
>>>>
>>>>
>>>>
>>>>
>>>
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 
> 


Article: 46216
Subject: Re: INOUT port
From: "Reala" <->
Date: Thu, 22 Aug 2002 09:14:02 +0800
Links: << >>  << T >>  << A >>
Dear Mark,

It is what I want to know. Your reply is use for me. Thank you.
My method is "change" the inout port to IN port for 1st simulation.
Then, "change" the inout port to OUT port for 2nd simulation.
However, it is a stupid method and not work very well.
I read some docuements about Verilog in internet, but not too much
information about INOUT port. So, I post the problem in newsgroups.

Reala


"Mark Momcilovich" <momcilma@yahoo.com> wrote in message
news:2f6f0882.0208210640.56a09805@posting.google.com...
> "Reala" <-> wrote in message news:<ajsgss$57k1@imsp212.netvigator.com>...
> > Hi,
> >
> > For the design with input and output only, I collect input of design to
> > output of test generater and vice versa. However, when the design have
INOUT
> > port, How can i collect this to test generate mode?
> >
> > Thanks you.
> > Reala
>
> ----------------------------------------------------------
> Reala,
>   I'm not sure what you're trying to do here but it sounds like you're
> writing
> at testbench in Verilog.  Verilog simulators have trouble driving
> "inout" pins from a "reg" in a testbench.  Instead drive the "inout"
> pin from your testbench with a net "wire", "tri", "wor" or a "trior"
> then "assign" this net with a "reg" registered value.
>   Try this code out below.  I've shown a "wire" net "bidir_data"
> attached to the "inout" pin of the UUT module that is a 16-bit
> bidirectional register.
>   I force tri-stated "zzzz" into the register "bidir_data_reg" which
> in turn drives the "net" "bidir_data", when I expect the UUT's data
> bus to be an output.  I force example data "aa55" into
> "bidir_data_reg", when I expect the UUT's data bus to be an input.
>   This approach solves multiple headaches and allows me to accurately
> simulate verilog "inout" module pins.
>   Hope this helps,
> Mark
>
> ----------------------------------------------------------
> module testbench();
> parameter CLK_PERIOD = 80;
> // Inputs
>     reg mclk;
>
> // Outputs
>
> // Bidirs
>
> // Nets
>     wire [15:0] bidir_data;
>
> // Registers
>     reg  [15:0] bidir_data_reg;
>
> // Instantiate the UUT
>     bidir_16bit_reg UUTreg (mclk, bidir_data);
>
> // Initialize Inputs
>     initial begin
>        mclk = 0;
>        bidir_data_reg = 16'hzzzz;
>    #20 bidir_data_reg = 16'haa55;
>    #80 bidir_data_reg = 16'hzzzz;
>     end
>
> // Assignments
> assign bidir_data = bidir_data_reg ;
>
> // mclk Clock generator
>     always
>        begin
>        #(CLK_PERIOD/2) mclk = ~mclk;
>        end
> endmodule



Article: 46217
Subject: Re: INOUT port
From: "Reala" <->
Date: Thu, 22 Aug 2002 09:17:51 +0800
Links: << >>  << T >>  << A >>
Hi ae,

I read some docuement about verilog in internet, but it is not too much
information about INOUT port. I have difficulty to write a testbench for
INOUT port.

Actually, for thedesign involving INOUT port, I also do not know how to do.
Any docuement about INOUT port recommand for me?
Thanks.

Reala
<ae> wrote in message news:ee787ad.0@WebX.sUN8CHnE...
> Not completely sure what you are asking but it sounds like you are asking
how to control your INOUT port between reading/writing in which case a
tri-state network with whatever enables you want should work...



Article: 46218
Subject: Re: Xilinx tools: which one? Esp. schematic
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Wed, 21 Aug 2002 21:32:22 -0400
Links: << >>  << T >>  << A >>
Hi Ray,

SRL16 sim model seems to be there, and it seems like it's pretty simple,
buf's on each input/output and a single SRL sim prim...dual port BRAM...I'll
have to look...RAMB16...in both Verilog and VHDL it appears!

Austin

"Ray Andraka" <ray@andraka.com> wrote in message
news:3D640F3E.7EE10D02@andraka.com...
> I wonder if models for all the primitives are there, or is it missing
working
> models for SRL16s and Dual port BRAMs?  As I recall they had reached an
impasse
> with Viewlogic around 1999 or so where viewlogic had to change something
to
> allow those peices to simulate and viewlogic didn't want to do it.  At the
time,
> Xilinx pretty much said, use HDL for virtex if you are going to use the
> features.  Try running a simulation on something that twiddles the address
bits
> of an SRL16.  If that works, then someone woke up and fixed it.  If, as I
> suspect it doesn't, then you have a very crippled simulation if you are
going to
> take advantage of the architecture.
>
> Austin Franklin wrote:
>
> > Hi,
> >
> > I tried a small V2P design today in Viewdraw, and it went all the way
> > through the tools, and I pushed down to the simulation models, and they
were
> > there (though I didn't run a simulation yet)...so I believe, at least to
> > some level, this works.  There was even a symbol for the PowerPC...but I
> > didn't explore that too much, though I think I might.  I wonder if
there's a
> > simulation model for that...there was both a VHDL and a Verilog
selection
> > for the PPC...
> >
> > Regards,
> >
> > Austin
> >
> >
>
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 46219
Subject: Re: Logic Analyzers with an Altera Board
From: nospam@needed.com (Paul)
Date: Wed, 21 Aug 2002 22:40:06 -0400
Links: << >>  << T >>  << A >>
In article <ea62e09.0208211211.1334e12a@posting.google.com>,
prashantj@usa.net (Prashant) wrote:

> Hi,
> 
> I have a prototyping board from Altera for testing my design. I'm new
> to using a prototype board and hence had some questions. The device in
> the prototype board is a EP20K1500E.
> 
> Does anyone have views on whether I would need a logic analyzer with
> this board ? Do people who use prototype boards always use analyzers ?
> Is there an alternate way out without using analyzers ? Any
> recommendation on which logic analyzer should I use ?
> 
> Thanks,
> Prashant

Really, it depends on your budget and how much time you have to complete
a design, as to how much equipment you buy for development purposes.

As others have pointed out, it can be difficult to see what is going
on inside an FPGA. (In another post, Austin mentions ChipScope, which 
is a macro inside the device you can use to sample internal signals.)
One option is to dedicate a number of outputs on your design, where
each output is driven by a multiplexer tree which is connected to 
the important nodes in your design. You then use jumpers to control
which internal multiplexer input is used to drive these spare outputs.
The multiplexer tree is P&R with the rest of the design, so it doesn't
have to be added later. 

Once any signals are available outside the chip (either test outputs
or real outputs), you can place a connector on the board which is only
populated on your lab prototype. For example, some analyzers have
probe inputs which connect to a small Amp Mictor connector. The Mictor
allows a 50 ohm environment to be maintained from the board to the
analyzer. If the signal traces flow "through" the connector on the 
board, there is minimal signal integrity degradation when the connector
is removed in production.

If you have zero budget for test equipment, I would still plan on
some kind of approach to test. Later, if you get desperate, you can
always lease test equipment for a month or two if the need arises.

Simulation testbenches have really improved the bringup process for
designs in the lab. If you have a mainly datapath design, you can
frequently see positive results within a couple of days of delivery
of your populated board, if the design was simulated thoroughly 
before design close.

Where simulation sometimes breaks down, is at the board level. 
Depending on the size of the design, it can sometimes be difficult
to load an entire board in simulation, so a piecewise approach 
might be required. Also, encrypted behavioral models are not 
always available for all the devices on your board.

In a big company, I have seen a 4 channel digital scope on each
designers lab bench, while there are 2 logic analysers shared
for every 15 lab benches. This should give you some idea as to
which equipment has the highest utility.

A digital scope with 1Ghz bandwidth can deal with making timing
measurements and checking signal integrity on "run of the mill"
CMOS interfaces. For a home project, even a digital scope can
be more than you can afford.

If you ever plan on selling what you design, you should still do
some signal verification before releasing the design to production.
Leasing a bit of test equipment is much cheaper than a field 
recall of your design.

        Paul

Article: 46220
Subject: Re: How to include Xilinx library for both ModelSim and Synplify?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 22 Aug 2002 02:48:17 GMT
Links: << >>  << T >>  << A >>
OK, that makes sense.  Since, in most of our stuff we are very aware of how it is
being constructed (and design the logic for single level as much as possible), it is
not an issue.  As I recall, the unisim and the synplicity virtex libraries cannot
co-exist in the same architecture-entity without configuration statements, so if you
use components out of one, you need to use that for all.

Ken McElvain wrote:

> That is partially true.  If you do it the way I suggested, then Synplify
> will have a proper timing model for the LUT instead of treating it like
> an unknown black box.  In both cases, Synplify will not modify the
> LUT, but the correct timing model will lead to improved timing of paths
> through the LUT.
>
> Ray Andraka wrote:
>
> > Ken,
> >
> > You can also instantiate LUT4's the same way, provided you put a user attribute
> > (INIT=) on it and add a pragma'd out generic for the init for simulation.
> >
> >
> >
> > Ken McElvain wrote:
> >
> >
> >>Some components are simple and a component declaration is enough.  Some
> >>require a bit more information to interpret, which is stored as
> >>attributes in the package.  This might include information used in
> >>DRC checking such as which pins are tristate.  If you want to
> >>instantiate a LUT4 then you will need the package.  The package
> >>file lives at .../synplify/lib/xilinx/virtex.vhd
> >>
> >>In your case nothing more is needed and your component declaration
> >>is all you need.
> >>
> >>- Ken
> >>
> >>Barry Brown wrote:
> >>
> >>
> >>>Ray -
> >>>Really?  Perhaps I'm missing something then.  When the two lines are
> >>>commented out, Synplify gives me a warning:
> >>>
> >>>@W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box
> >>>
> >>>I thought that sounded bad, but do you mean I can just ignore it?
> >>>I tried it, and the Xilinx P&R works fine, so I guess all is right with the
> >>>world.  So then what does Synplify include that Virtex library for?
> >>>
> >>>Thanks,
> >>>Barry
> >>>
> >>>"Ray Andraka" <ray@andraka.com> wrote in message
> >>>news:3D62B4D4.6739AA63@andraka.com...
> >>>
> >>>
> >>>>you don't need those two lines for synplify either. Just leave them out.
> >>>>
> >>>>Barry Brown wrote:
> >>>>
> >>>>
> >>>>
> >>>>>I need to use some Xilinx primitives in my VHDL, and they seem to be in
> >>>>>different libraries for use with ModelSim and Synplify.  Here's what I
> >>>>>
> >>>>>
> >>>have
> >>>
> >>>
> >>>>>so far...
> >>>>>
> >>>>>library ieee;
> >>>>>use ieee.std_logic_1164.all;
> >>>>>use ieee.std_logic_unsigned.all;
> >>>>>-- synthesis translate_off
> >>>>>library unisim;
> >>>>>use unisim.all;
> >>>>>-- synthesis translate_on
> >>>>>library virtex;
> >>>>>use virtex.components.all;
> >>>>>...
> >>>>>
> >>>>>This works fine in Synplify, but for ModelSim I have to comment out the
> >>>>>
> >>>>>
> >>>two
> >>>
> >>>
> >>>>>lines...
> >>>>>
> >>>>>--library virtex;
> >>>>>--use virtex.components.all;
> >>>>>
> >>>>>Does anyone know a better way to "hide" these from ModelSim?
> >>>>>
> >>>>>Thanks,
> >>>>>Barry Brown
> >>>>>
> >>>>>
> >>>>--
> >>>>--Ray Andraka, P.E.
> >>>>President, the Andraka Consulting Group, Inc.
> >>>>401/884-7930     Fax 401/884-7950
> >>>>email ray@andraka.com
> >>>>http://www.andraka.com
> >>>>
> >>>>"They that give up essential liberty to obtain a little
> >>>> temporary safety deserve neither liberty nor safety."
> >>>>                                         -Benjamin Franklin, 1759
> >>>>
> >>>>
> >>>>
> >>>>
> >>>
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46221
Subject: Re: Xilinx tools: which one? Esp. schematic
From: Ray Andraka <ray@andraka.com>
Date: Thu, 22 Aug 2002 02:53:18 GMT
Links: << >>  << T >>  << A >>
It is there, but does it function correctly for a dynamic address?  IIRC, the
issue wasn't whether or not it was there but that it only did a static delay.
The BRAMs, again IIRC,  had models but they did not function as dual port.
Hopefully that has since been addressed, but frankly I'd be surprised if it has
been.  Thinkng back, I think  another block that was not supported was the
DLLs.  I don't recall the behavior of their model if there was one at all.

Austin Franklin wrote:

> Hi Ray,
>
> SRL16 sim model seems to be there, and it seems like it's pretty simple,
> buf's on each input/output and a single SRL sim prim...dual port BRAM...I'll
> have to look...RAMB16...in both Verilog and VHDL it appears!
>
> Austin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D640F3E.7EE10D02@andraka.com...
> > I wonder if models for all the primitives are there, or is it missing
> working
> > models for SRL16s and Dual port BRAMs?  As I recall they had reached an
> impasse
> > with Viewlogic around 1999 or so where viewlogic had to change something
> to
> > allow those peices to simulate and viewlogic didn't want to do it.  At the
> time,
> > Xilinx pretty much said, use HDL for virtex if you are going to use the
> > features.  Try running a simulation on something that twiddles the address
> bits
> > of an SRL16.  If that works, then someone woke up and fixed it.  If, as I
> > suspect it doesn't, then you have a very crippled simulation if you are
> going to
> > take advantage of the architecture.
> >
> > Austin Franklin wrote:
> >
> > > Hi,
> > >
> > > I tried a small V2P design today in Viewdraw, and it went all the way
> > > through the tools, and I pushed down to the simulation models, and they
> were
> > > there (though I didn't run a simulation yet)...so I believe, at least to
> > > some level, this works.  There was even a symbol for the PowerPC...but I
> > > didn't explore that too much, though I think I might.  I wonder if
> there's a
> > > simulation model for that...there was both a VHDL and a Verilog
> selection
> > > for the PPC...
> > >
> > > Regards,
> > >
> > > Austin
> > >
> > >
> >
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46222
Subject: Re: to reduce the circuit design
From: maimuna_a@nrsa.gov.in (maimuna)
Date: 21 Aug 2002 22:22:10 -0700
Links: << >>  << T >>  << A >>
thanx for the reply. but the case statment will not work since this
also will be lenthier. i want is there any option like table or
anything else which will reduce the design statements. if there is no
other option then i have to write code with if..else statement which
will be too longer.
plese help me out
maimuna

"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1029759710.27834@turtle.ru.ac.za>...
> Isn't there a case for a CASE statement here? If not to reduce the design,
> at least to make it a bit more readable!
> 
> Adrian
> 
> 
> maimuna <maimuna_a@nrsa.gov.in> wrote in message
> news:13bf39b3.0208190350.447bd4bf@posting.google.com...
> > please go thro this circuit and tell me is there any why to reduce the
> > design
> >
> > the various variables are pixclk_reg[], lc_msb_inv[]  & lc_byt_cnt[].
> > depending on the values of these variables the design changes.
> > i have given u only two different conditions like pixclk_reg[] == 6 &
> > lc_byt_cnt[] == 0 and pixclk_reg[] == 6 & lc_byt_cnt[] == 1. but still
> > there are more conditions like
> > pixclk_reg[] == 6 & lc_byt_cnt[] == 2
> > pixclk_reg[] == 6 & lc_byt_cnt[] == 3
> > pixclk_reg[] == 5 & lc_byt_cnt[] == 0
> > pixclk_reg[] == 5 & lc_byt_cnt[] == 1
> > pixclk_reg[] == 5 & lc_byt_cnt[] == 2
> > ----
> > ---
> > ---
> > ---
> > pixclk_reg[] == 3 & lc_byt_cnt[] == 3
> > end_of_line is just A CONDITION
> > CAN U PLEASE HELP ME OUT
> > MAIMUNA
> >
> > the design is as below
> >
> >
> > if pixclk_reg[] == 6 & lc_byt_cnt[] == 0 then
> > if lc_msb_inv[] == 0 then
> > if end_of_line == TRUE then
> > line_cntr_one[6..0] = line_cntr_one[6..0] +1;
> > if line_cntr_one[6..0] == TRUE then
> > line_cntr_one[6..0] =1;
> > else line_cntr_one[6..0] = line_cntr_one[6..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > elsif lc_msb_inv[] == 1 then
> > if end_of_line == TRUE then
> > line_cntr_one[5..0] = line_cntr_one[5..0] +1;
> > if line_cntr_one[5..0] == TRUE then
> > line_cntr_one[5..0] =1;
> > else line_cntr_one[5..0] = line_cntr_one[5..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > elsif lc_msb_inv[] == 2 then
> > if end_of_line == TRUE then
> > line_cntr_one[4..0] = line_cntr_one[4..0] +1;
> > if line_cntr_one[4..0] == TRUE then
> > line_cntr_one[4..0] =1;
> > else line_cntr_one[4..0] = line_cntr_one[4..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > elsif lc_msb_inv[] == 3 then
> > if end_of_line == TRUE then
> > line_cntr_one[3..0] = line_cntr_one[3..0] +1;
> > if line_cntr_one[3..0] == TRUE then
> > line_cntr_one[3..0] =1;
> > else line_cntr_one[3..0] = line_cntr_one[3..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > elsif lc_msb_inv[] == 4 then
> > if end_of_line == TRUE then
> > line_cntr_one[2..0] = line_cntr_one[2..0] +1;
> > if line_cntr_one[2..0] == TRUE then
> > line_cntr_one[2..0] =1;
> > else line_cntr_one[2..0] = line_cntr_one[2..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > elsif lc_msb_inv[] == 5 then
> > if end_of_line == TRUE then
> > line_cntr_one[1..0] = line_cntr_one[1..0] +1;
> > if line_cntr_one[1..0] == TRUE then
> > line_cntr_one[1..0] = 1;
> > else line_cntr_one[1..0] = line_cntr_one[1..0];
> > end if;
> > else line_cntr_one[] = line_cntr_one[];
> > end if;
> > end if;
> > elsif  pixclk_reg[] == 6 & lc_byt_cnt[] == 1 then
> > if end_of_line == TRUE then
> > line_cntr_one[6..0] = line_cntr_one[6..0]+1;
> > if line_cntr_one[6..0] == TRUE then
> > line_cntr_one[6..0] = 0;
> > else line_cntr_one[6..0] = line_cntr_one[6..0];
> > end if;
> > else line_cntr_one[6..0] = line_cntr_one[6..0];
> > end if;
> > if end_of_line == TRUE & line_cntr_one[] == TRUE then
> > if lc_msb_inv[] == 0 then
> > if end_of_line == TRUE then
> > line_cntr_two[6..0] = line_cntr_two[6..0] +1;
> > if line_cntr_two[6..0] == TRUE then
> > line_cntr_two[6..0] = 0;
> > else line_cntr_two[6..0] = line_cntr_two[6..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > elsif lc_msb_inv[] == 1 then
> > if end_of_line == TRUE then
> > line_cntr_two[5..0] = line_cntr_two[5..0] +1;
> > if line_cntr_two[5..0] == TRUE then
> > line_cntr_two[5..0] = 0;
> > else line_cntr_two[5..0] = line_cntr_two[5..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > elsif lc_msb_inv[] == 2 then
> > if end_of_line == TRUE then
> > line_cntr_two[4..0] = line_cntr_two[4..0] +1;
> > if line_cntr_two[4..0] == TRUE then
> > line_cntr_two[4..0] = 0;
> > else line_cntr_two[4..0] = line_cntr_two[4..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > elsif lc_msb_inv[] == 3 then
> > if end_of_line == TRUE then
> > line_cntr_two[3..0] = line_cntr_two[3..0] +1;
> > if line_cntr_two[3..0] == TRUE then
> > line_cntr_two[3..0] = 0;
> > else line_cntr_two[3..0] = line_cntr_two[3..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > elsif lc_msb_inv[] == 4 then
> > if end_of_line == TRUE then
> > line_cntr_two[2..0] = line_cntr_two[2..0] +1;
> > if line_cntr_two[2..0] == TRUE then
> > line_cntr_two[2..0] = 0;
> > else line_cntr_two[2..0] = line_cntr_two[2..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > elsif lc_msb_inv[] == 5 then
> > if end_of_line == TRUE then
> > line_cntr_two[1..0] = line_cntr_two[1..0] +1;
> > if line_cntr_two[1..0] == TRUE then
> > line_cntr_two[1..0] = 0;
> > else line_cntr_two[1..0] = line_cntr_two[1..0];
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > end if;
> > else line_cntr_two[] = line_cntr_two[];
> > end if;
> > if line_cntr_one[6..0] == TRUE then
> > line_cntr_one[6..0] =1;
> > else line_cntr_one[6..0] = line_cntr_one[6..0];
> > end if;
> > ---
> > ---
> > ---
> >
> > ----
> > END;

Article: 46223
Subject: combinatorial clocks
From: mike@sysoc.de (Michael Schmidl)
Date: 21 Aug 2002 23:25:42 -0700
Links: << >>  << T >>  << A >>
I have a customer using a XCV2000 and XCV800 where I have to integrate
an IP core.

The PCB is already fixed so I can not change the pinning. This PCB has
only one GCK connected and all other pins available are normal IOs -
the other 3 GCKs are not connected and not accessible due to the ball
grid housing.

The IP I try to integrate has three "clock inputs". One - connected to
the GCK2 - is used to clock the host interface to the controlling
processor. The other two "clock inputs" - connected to normal IOs -
are used to clock data streams in and out of the XILINX and are both
generated by an external component (it is a Ethernet IP core I am
talking about and the two clocks are the MII interface clocks
generated by an external PHY chip).

The next odd thing is that the CORE I have to integrate uses a logic
to multiplex the two PHY clock inputs and brings this multiplexed
clocks to an OUTPUT wire of the core (they call this the
PRE-CLOCK-TREE signals). The actual clock driving all logic inside the
core is an INPUT wire of the core (called the POST-CLOCK-TREE
signals). So they are producing something like a CLOCKTREE (the core
is originally intended for ASIC or GATEARRAY designs).

I tried to connect the pre- and post-clock-tree signal at my top level
just with a wire and use the same signal for driving my logic which
must run on the same clocks as the core.

If I use ISE 4.2.03i/XST to produce a gatelevel model, it does not
work! I get strange misbehaviours that look like HOLD violations
between flip flops driven by the same clock.

Before I generated the gatelevel model I used the CONSTRAINT EDITOR to
define the different clocks for the nodes detected as clocks. The
place and route tells me that these constraints have been meet and the
STA shows the some. But the gatelevel does not work.

Next try was to connect the "clock-tree" signals to pads of the XILINX
and to connect the in- and outputs within the testbench. VOILA, it
works! Now the ISE places the clock inputs as exspected to GCK pins
and uses BUFGPs to drive the "clock tree" clocking the logic connected
to it!

But unfortunatly I can not do this in reality. The GCKs are not
availabel so I have to find a solution for the "combinatorial clock"
to get a working design.

ANY IDEA???

Any help is appreciated.

With kind regards
_______________________________________
Dipl.-Ing.(FH) Michael Schmidl
Prochintalstr. 5
D-80993 München
Germany
Tel   089  / 143 20658
Mobil 0179 / 673 0851
Fax   089  / 2443 73489
PGP-Key: www.mschmidl.de/mschmidl.asc
Info:    www.mschmidl.de

Article: 46224
Subject: Re: Huge discrepanzcy between gate-array and standard cell synthesis
From: Muzaffer Kal <kal@dspia.com>
Date: Thu, 22 Aug 2002 07:15:59 GMT
Links: << >>  << T >>  << A >>
On 20 Aug 2002 04:07:50 -0700, HenningBahr@web.de (HenningB) wrote:

>Hi all,
>
>I have designed a simple frequency divider, existing mainly of 15
>flip-flops. Ambit BuildGates is my synthesis tool. I am getting the
>following results when my target technology is a 300k gate-array
>technology from LSI:
>
>Worst path delay: 1.73 ns
>Cell Area:    279
>
>And these are the results when using a standard-cell 0.35 um
>technology:
>
>Worst path delay: 1.92 ns
>Cell Area:	13,304
>
>Why is there such a huge discrepancy between the cell areas?
>I expected the standard-cell to be faster. 
>My explanation for the faster gate-array implementation: it takes only
>the gate delay into account not any wiring. Am I right?
>Does the worst path delay only exist of the combinational part? (the
>tool only highlights the combinational logic)
>
>Cheers,
>Henning

Do a report_lib on your libraries and figure out what the unit is for
each number. You can check the area of the NAND2 as someone else
suggested. 47 square micron is not that unreasonable for a .35u NAND2
cell.
As to timing, are you setting the same constraints and using wire load
models ? It depends on how accurate the wire load models are (for a
block this size they can be overly pessimistic).

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations



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