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Messages from 48975

Article: 48975
Subject: filters on fpgas
From: stenasc@yahoo.com (Bob)
Date: 28 Oct 2002 07:51:01 -0800
Links: << >>  << T >>  << A >>
Hi.

I want to create a filter on an FPGA. The filter is a 25 tap FIR. It
is to be used  for an audio application. What kind of chip resources
ie no. of flops
would this use. Is it possible to use existing C code for a DSP to
implement this?

Thanks for your help

Bob

Article: 48976
Subject: Re: assigning TIG to a net in VHDL source (Xilinx)
From: "Simon" <null@null.null>
Date: Mon, 28 Oct 2002 16:12:15 -0000
Links: << >>  << T >>  << A >>
> It would seem that "" matches the first of these.  However, that
> doesn't mean that it will work with the particular synthesiser that
> you are using.  I guess you need to try giving it a valid TSid next.

The empty string does pass through the synthesiser (leonardo) ok, and
appears as expected in the edif.

I have had a reply from Xilinx, and it would appear that the problem is a
'known issue' with TIGs in the current version of MAP.

The workaround is to push on with PAR anyway - apparently this has to be
done via the command line as the GUI will not continue if there's an error,
but that's fine for me as I never use the gui anyway.
... seems to be working so far, but it'll be a while before the chip is
cooked ;)

Thanks,
Simon



Article: 48977
Subject: Re: Pin locking Virtex 2 FPGA
From: Kate Kelley <kate.kelley@xilinx.com>
Date: Mon, 28 Oct 2002 09:29:58 -0700
Links: << >>  << T >>  << A >>
Mike,

The 5.1i tools have a new tool called PACE - (Pinout and Area Constraints
Editor).  One of the major functions is to help out with pin assignments.
Check out http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=pace
for more information.

If you don't have 5.1i you can use the Floorplanner in 4.2i to help you
out.   This will show you how par placed your signals.  It is a good idea
to group the busses together and any other pins that should logically be
grouped together.

In the older 4K devices it was important to put data busses on the sides
and control logic on the top or bottom but that isn't true for the Virtex
devices.  It is more important to group signals together that go to the
same logic.

Do be careful of clocking if you have more than 8 clocks (only 8 clock are
allowed in a clock region), multiple I/O standards, DDR,  I/O that are
connected to carry logic, and clock pins.  It is important to run your
pinout through the tools to make sure you are not violating any pinout
rules.

Kate



M Schreiber wrote:

> Hello,
> I am in the process of a new design.  The design is probably about 50%
> complete.  All of the interfaces are defined to and from the chip but
> the internal fpga logic is not completely defined.  Now I need to
> start the PCB design effort, and lock down some pins.  I ran my design
> in its current state through the Xilinx tool set and had it choose the
> pins for me.  Then I went back and glanced over the .ucf file and a
> few things stood out as less than optimal (at least seems that way to
> me).  There are many buses throughout the design and I would have
> expected them to be grouped in a similar area of the chip, but they
> were not.  The tools did manage to put all of my input clocks on
> global clock buffers and even a good portion of output clocks to other
> devices.  I guess the question I am asking is what are some good rules
> of thumb (I know that these rules can't always be applied) for
> choosing pin configurations before a design is complete?  Should I let
> the tools choose most of my pins and modify that list or should I
> group buses together with timing constraints, etc?  I glanced through
> comp.arch.fpga for similar topics, but most of them were old and I was
> wondering if anyone had any new thoughts on the subject.  This is my
> first major design that I am doing on my own (Xilinx Virtex 2
> xc2v1000fg456, vhdl based, fpga express, xilinx 4.2i tools) and I want
> to make sure I do all I can to optimize my design.
> Thanks,
>         Mike Schreiber
>         Hardware Engineer
>         Mschreiber75@yahoo.com


Article: 48978
Subject: programming flex10k
From: "naluzzi filippo" <naluzzi@cclinf.polito.it>
Date: Mon, 28 Oct 2002 17:45:54 +0100
Links: << >>  << T >>  << A >>
I`ve a problem in programming an Altera FPGA (flex 10k30), in JTAG mode and
even by a configuration device (EPC2).
The FPGA never release the pin CONF_DONE so a configuration (and an user
mode) can`t start. In JATG mode (ByteBlaster cable on parallel port) the
software (Maxplus2) is not able to load succesfully the project to the
target device, and using  EPC, this configuration device reload infinitely
the data to FPGA (exactly, the FPGA doesn`t release the CONF_DONE pin, so
the pull-up resistor can not pull it, and the configuration device is not
able to hear that the programming has been done so it entries in a infinite
programming-loop).

Can you help me?





Article: 48979
Subject: Leonardo and lpm (Altera)
From: "Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>
Date: Mon, 28 Oct 2002 17:55:56 +0100
Links: << >>  << T >>  << A >>
Hi all,
I'm in trouble with leonardo : I have a design
in vhdl which instanciates lpm functions such as lpm_ram_dp
and I would like to synthesize it with leonardo for the APEX20Ke
technology.
The problem is that it seems that leonardo doesn't recognize those 
primitives : it generates black boxes with name such as :  
lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED

wich can't be read by the P&R quartus.
So, my question is :
Do I have to :
1) configure leonardo to directly synthesize lpm megafunctions (how ?)
2) tell leonardo not to change the name (ie keep lpm_ram_dp) by not adding
generic parameters (how ?)
3) Not synthesize entities containing lpm (but somes are in an ugly generated code)
4) other ?

thanks very much for your help . I'm on it for a long time now
and I'm getting mad.

Thanks a lot.

Stephane

Article: 48980
Subject: Re: filters on fpgas
From: Ray Andraka <ray@andraka.com>
Date: Mon, 28 Oct 2002 17:04:46 GMT
Links: << >>  << T >>  << A >>
Depends on the implementation.  At 25 taps and audio rates, you can make
a FIR filter using a block ram for the delay queue, either a BRAM or a
CLB RAM for the coefficients a scaling accumulator multiplier and an
accumulator for a very compact design (the only CLBs are a pair of
accumulators a simple state machine and addressing logic for the
memories.

Bob wrote:

> Hi.
>
> I want to create a filter on an FPGA. The filter is a 25 tap FIR. It
> is to be used  for an audio application. What kind of chip resources
> ie no. of flops
> would this use. Is it possible to use existing C code for a DSP to
> implement this?
>
> Thanks for your help
>
> Bob

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 48981
Subject: Re: Phased clocks...
From: Ray Andraka <ray@andraka.com>
Date: Mon, 28 Oct 2002 17:08:04 GMT
Links: << >>  << T >>  << A >>
No need to use a negative edge.  The phase decode changes as a result of the
clock rising edge.  By the time it propagates to the flip-flop clock enables the
clock rising edge is long past, and as long as your clock frequency is not too
high, it is long before the next rising edge occurs.

Noddy wrote:

> > Use phased clock enables instead.  Ie, the 32 MHz clock goes to
> everything, then
> > the divided clock enable controls the flip-flops on each phase.  You can
> > substantially reduced the size of your filter bank by going to a
> digit-serial
> > architecture using distributed arithmetic since you have 8 clocks per
> sample to
> > work with.
>
> Thanks for the advice... I do have one question though regarding the clock
> enables (I may be mixing up something, though). Consider a sub-filter in the
> polyphase filterbank. What you are saying, I think, is that I should send
> the 32MHz clock signal to the sub-filter clock input, and then use a phased
> clock at the enable? How do I make sure that the filter is enabled before
> the clock edge arrives since the 32 MHz clock will be driving both the
> sub-filter, and the 3bit decoder (which forms the phased signal)? Unless I
> use a negative edge triggered clock input on the sub-filter?
>
> Thanks
>
> adrian

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 48982
Subject: Re: DCM and CLK on Virtex2 PCIX controller
From: "Brannon King" <bking@starbridgesystems.com>
Date: Mon, 28 Oct 2002 10:10:13 -0700
Links: << >>  << T >>  << A >>
> Sorry I dont get your point at all. Could you explain in general your
setup?
> I assume you have a PCI-X IP core and want to glue you logic to it,
right?
> So whats the point there?

Sorry if I have been unclear. The problem is this: I have 320 pads to plug
into tri-state DDR buffers in the userapp of the PCI-X IP core. When I do
that, my clock speed goes way down. I don't know how to explain it any
simpler than that, and I'm not at liberty to post the full source code. The
full setup basically consists of two 64bit registers where one is the
control codes (with one pin plugged into the T) and the other is the data.
The data pins are plugged strait to the ODDRs and the return from the IDDRs
are ran through a 'with' statement for multiplexing before getting tied to
the S_DATA_IN.

Don't feel like you have to email -- feel free to post to the newsgroup.
Thanks.




Article: 48983
Subject: Re: Leonardo and lpm (Altera)
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 28 Oct 2002 09:51:18 -0800
Links: << >>  << T >>  << A >>


Mancini Stéphane wrote:

> Hi all,
> I'm in trouble with leonardo : I have a design
> in vhdl which instanciates lpm functions such as lpm_ram_dp
> and I would like to synthesize it with leonardo for the APEX20Ke
> technology.
> The problem is that it seems that leonardo doesn't recognize those 
> primitives : it generates black boxes with name such as :  
> lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED


I find it easier to let leo infer the lpm function from
the source code. Start with the lpm source code for the
object you're after, replace the parameters
with constants and run leo.


For more information do a
google groups search on:
  vhdl lpm open source leo



    -- Mike Treseler


Article: 48984
Subject: Re: Leonardo and lpm (Altera)
From: Prager Roman <rprager@frequentis.com>
Date: Mon, 28 Oct 2002 18:00:25 GMT
Links: << >>  << T >>  << A >>
 wrote:
> Hi all,
> I'm in trouble with leonardo : I have a design
> in vhdl which instanciates lpm functions such as lpm_ram_dp
> and I would like to synthesize it with leonardo for the APEX20Ke
> technology.
> The problem is that it seems that leonardo doesn't recognize those 
> primitives : it generates black boxes with name such as :  
> lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED

> wich can't be read by the P&R quartus.
> So, my question is :
> Do I have to :
> 1) configure leonardo to directly synthesize lpm megafunctions (how ?)
no
> 2) tell leonardo not to change the name (ie keep lpm_ram_dp) by not adding
> generic parameters (how ?)
> 3) Not synthesize entities containing lpm (but somes are in an ugly generated code)
> 4) other ?
Altera Support told us to leave the lpm- functions as blackboxes and do not
try to synthesize them with Leonardo. (which seems to be the same as you
are doing).

Indeed, I get such instance names as you mentioned above, but in my case, Quartus
has no problem reading the edf- file.
But it depends on Leonardo settings. What does the exact error message look
like?. E.g. I once had problems, when I also allowed Leonardo to put in the
logic cells for the pins.

Roman

> thanks very much for your help . I'm on it for a long time now
> and I'm getting mad.

> Thanks a lot.

> Stephane

Article: 48985
Subject: From NCD to Bitstream (Xilinx FPGA)
From: Weifeng Xu <wxu@ecs.umass.edu>
Date: Mon, 28 Oct 2002 13:28:27 -0500
Links: << >>  << T >>  << A >>
Hi, guys
   I wanna know whether I can write a script file to generate a final
bitstream from NCD file,
can "bitgen" take NCD file directly?
  Thanks!

Weifeng


Article: 48986
Subject: Re: 3.3V Device Programmer Suggestions ?
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: Mon, 28 Oct 2002 20:00:04 GMT
Links: << >>  << T >>  << A >>
rrr@ieee.org (Rajeev) writes:

> One question, Petter, I use the parallel cable all the time for JTAG
> download to my test FPGA, and also for ChipScope... but I don't know how

If the SPROM is in the same scan chain as your FPGA you will only need
to generate MCS files and change your impact configuration. 

> to go about using it to program the SPROM.  Is there an AppNote or something
> that explains how to do this... or where should I start my learning ?  Will
> I also need to write some software ?

See article:

http://groups.google.com/groups?safe=images&ie=UTF-8&oe=UTF-8&as_umsgid=87smyva5qd.fsf%40filestore.home.gustad.com&lr=&hl=en


Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 48987
Subject: Re: Porting from Xilinx to Altera?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Mon, 28 Oct 2002 21:17:46 +0100
Links: << >>  << T >>  << A >>
Not all families are supported by the web edition.
For some the MaxPlus2 is required.

Rene

Fredrik wrote:
> Hi,
> There is a learning curve but it is no big think to get used to
> Alteras software. There is indeed a free version of QuartusII avalible
> called QuartusII Web Edition, this software supports all familys but
> not all densities. Full information is avalible on Alteras Web.
> Cheers
> Fredrik 
> "Soul in Seoul" <Far@East.Design> wrote in message news:<3dbcedf0$1@news.starhub.net.sg>...


Article: 48988
Subject: Re: From NCD to Bitstream (Xilinx FPGA)
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: Mon, 28 Oct 2002 21:00:04 GMT
Links: << >>  << T >>  << A >>
Weifeng Xu <wxu@ecs.umass.edu> writes:

> Hi, guys
>    I wanna know whether I can write a script file to generate a final
> bitstream from NCD file,
> can "bitgen" take NCD file directly?

Yes, e.g. bitgen -w -g ConfigRate:8 dut.ncd dut.bit

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 48989
Subject: Re: Porting from Xilinx to Altera?
From: "Karl de Boois" <karlIGNORETHISPART@chello.nl>
Date: Tue, 29 Oct 2002 05:00:45 GMT
Links: << >>  << T >>  << A >>
You don't wanna use the families that are not supported by QuartusII ! The
main reason for using MAXPlus2 would be the relaxed system requirements for
your workstation.

Karl.
"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message
news:3DBD9B6A.5030508@dplanet.ch...
> Not all families are supported by the web edition.
> For some the MaxPlus2 is required.
>
> Rene
>
> Fredrik wrote:
> > Hi,
> > There is a learning curve but it is no big think to get used to
> > Alteras software. There is indeed a free version of QuartusII avalible
> > called QuartusII Web Edition, this software supports all familys but
> > not all densities. Full information is avalible on Alteras Web.
> > Cheers
> > Fredrik
> > "Soul in Seoul" <Far@East.Design> wrote in message
news:<3dbcedf0$1@news.starhub.net.sg>...
>



Article: 48990
Subject: Re: High Performance FPGA's - Xilinx and ??????
From: zhouchang2001cn@yahoo.com.cn (Zhou Chang)
Date: 28 Oct 2002 21:04:15 -0800
Links: << >>  << T >>  << A >>
Yes,what I define the "normal design" is a design many be implemented
in no more than four logic level ,( that is mean the combine logic may
be implemented from  input to output not cover more than four logic cell
(or logic element )). The normal design does not point to a certain design.
and in our some design is faster than what I said.
    
    We just compare the lowest speed grade is for economic reason.

best regards

zhou chang






fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0210280642.7922cca1@posting.google.com>...
> Hi,
> Please take into consideration the latest speed grades for Stratix the
> -5 and you will see some blazing fast preformance. (Just to compare
> Xilinx and Altera on there respectivly fastes FPGA's to be fair).
> Fredrik
> zhouchang2001cn@yahoo.com.cn (Zhou Chang) wrote in message news:<2ccc49b.0210272152.4a6e4206@posting.google.com>...

Article: 48991
Subject: Re: Leonardo and lpm (Altera)
From: avanish.bharati@altium.com.au (Avanish)
Date: 28 Oct 2002 22:01:26 -0800
Links: << >>  << T >>  << A >>
Hi

Try actually adding couple of attributes in your code and then
synthesise.
In you component declaration section of your code add.

component LPM_RAM_DP
        generic (  
          
          LPM_TYPE : string := LPM_RAM_DP;
        
         etc...
         );
   
           port (RDCLOCK : in std_logic := '0'
            etc..
            );
end component;

  -- important attribute that link with LPM_RAM_DP
  attribute macrocell : boolean;
  attribute macrocell of LPM_RAM_DP : component is true;
  attribute LPM_TYPE of LPM_RAM_DP  : component is "LPM_RAM_DP";
  
Here I am using "macrocell" but I am sure Leonardo should have one
built in or even recognise something like this too.
attribute BOX_TYPE : string;
attribute BOX_TYPE of LPM_RAM_DP : component is "BLACK_BOX";

This brings me to a question for everyone. What is the standard
BLACK_BOX attribute in VHDL for synthesis tools? Is there one!

Hope this helps

Avanish Bharati
Altium



Prager Roman <rprager@frequentis.com> wrote in message news:<apjskp$c6o$1@frqvie15ux.frequentis.frq>...
> wrote:
> > Hi all,
> > I'm in trouble with leonardo : I have a design
> > in vhdl which instanciates lpm functions such as lpm_ram_dp
> > and I would like to synthesize it with leonardo for the APEX20Ke
> > technology.
> > The problem is that it seems that leonardo doesn't recognize those 
> > primitives : it generates black boxes with name such as :  
> > lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED
>  
> > wich can't be read by the P&R quartus.
> > So, my question is :
> > Do I have to :
> > 1) configure leonardo to directly synthesize lpm megafunctions (how ?)
>  no
> > 2) tell leonardo not to change the name (ie keep lpm_ram_dp) by not adding
> > generic parameters (how ?)
> > 3) Not synthesize entities containing lpm (but somes are in an ugly generated code)
> > 4) other ?
> Altera Support told us to leave the lpm- functions as blackboxes and do not
> try to synthesize them with Leonardo. (which seems to be the same as you
> are doing).
> 
> Indeed, I get such instance names as you mentioned above, but in my case, Quartus
> has no problem reading the edf- file.
> But it depends on Leonardo settings. What does the exact error message look
> like?. E.g. I once had problems, when I also allowed Leonardo to put in the
> logic cells for the pins.
> 
> Roman
> 
> > thanks very much for your help . I'm on it for a long time now
> > and I'm getting mad.
>  
> > Thanks a lot.
>  
> > Stephane

Article: 48992
Subject: Re: Phased clocks...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 29 Oct 2002 10:41:33 +0200
Links: << >>  << T >>  << A >>
Ok.. thanks. One last question: I am using a 4 bit input. I was planning on
using the CoreGen distributed arithmetic FIR filter, using a digit serial
approach. This reduces the output sample rate to 1 sample every 4. Since
N=8, I would need a two phase clock on the clock enable. Unfortunately, for
some strange reason, the CoreGen does not provide a clock enable pin!!! So,
any other ideas other than using the phased clock enable?

adrian


> No need to use a negative edge.  The phase decode changes as a result of
the
> clock rising edge.  By the time it propagates to the flip-flop clock
enables the
> clock rising edge is long past, and as long as your clock frequency is not
too
> high, it is long before the next rising edge occurs.
>
> Noddy wrote:
>
> > > Use phased clock enables instead.  Ie, the 32 MHz clock goes to
> > everything, then
> > > the divided clock enable controls the flip-flops on each phase.  You
can
> > > substantially reduced the size of your filter bank by going to a
> > digit-serial
> > > architecture using distributed arithmetic since you have 8 clocks per
> > sample to
> > > work with.
> >
> > Thanks for the advice... I do have one question though regarding the
clock
> > enables (I may be mixing up something, though). Consider a sub-filter in
the
> > polyphase filterbank. What you are saying, I think, is that I should
send
> > the 32MHz clock signal to the sub-filter clock input, and then use a
phased
> > clock at the enable? How do I make sure that the filter is enabled
before
> > the clock edge arrives since the 32 MHz clock will be driving both the
> > sub-filter, and the 3bit decoder (which forms the phased signal)? Unless
I
> > use a negative edge triggered clock input on the sub-filter?
> >
> > Thanks
> >
> > adrian
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 48993
Subject: Modelsim help
From: "Peng Cong" <pc_dragon@sohu.com>
Date: Tue, 29 Oct 2002 17:10:01 +0800
Links: << >>  << T >>  << A >>
Xilinx ISE 5.1 + Modelsim 5.5e

When I use modelsim for simulation, it always propmt
"Evaluation memory limit reached".
How can I solve this problem?

Thanks for any advance



Article: 48994
Subject: Re: Phased clocks...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 29 Oct 2002 11:37:49 +0200
Links: << >>  << T >>  << A >>
I think I may have solved my own problem... I can use the ND pin, I think!

adrian


> Ok.. thanks. One last question: I am using a 4 bit input. I was planning
on
> using the CoreGen distributed arithmetic FIR filter, using a digit serial
> approach. This reduces the output sample rate to 1 sample every 4. Since
> N=8, I would need a two phase clock on the clock enable. Unfortunately,
for
> some strange reason, the CoreGen does not provide a clock enable pin!!!
So,
> any other ideas other than using the phased clock enable?
>
> adrian
>
>
> > No need to use a negative edge.  The phase decode changes as a result of
> the
> > clock rising edge.  By the time it propagates to the flip-flop clock
> enables the
> > clock rising edge is long past, and as long as your clock frequency is
not
> too
> > high, it is long before the next rising edge occurs.
> >
> > Noddy wrote:
> >
> > > > Use phased clock enables instead.  Ie, the 32 MHz clock goes to
> > > everything, then
> > > > the divided clock enable controls the flip-flops on each phase.  You
> can
> > > > substantially reduced the size of your filter bank by going to a
> > > digit-serial
> > > > architecture using distributed arithmetic since you have 8 clocks
per
> > > sample to
> > > > work with.
> > >
> > > Thanks for the advice... I do have one question though regarding the
> clock
> > > enables (I may be mixing up something, though). Consider a sub-filter
in
> the
> > > polyphase filterbank. What you are saying, I think, is that I should
> send
> > > the 32MHz clock signal to the sub-filter clock input, and then use a
> phased
> > > clock at the enable? How do I make sure that the filter is enabled
> before
> > > the clock edge arrives since the 32 MHz clock will be driving both the
> > > sub-filter, and the 3bit decoder (which forms the phased signal)?
Unless
> I
> > > use a negative edge triggered clock input on the sub-filter?
> > >
> > > Thanks
> > >
> > > adrian
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >
>
>



Article: 48995
Subject: Can we retaining EAB Data using BACK UP power SUPPLY for Vccint
From: satishkmys@yahoo.com (Satish K)
Date: 29 Oct 2002 01:55:37 -0800
Links: << >>  << T >>  << A >>
Dears,
 I am implementing  RAM   in   ACEX device ALTERA. We  wants  to know 
whether   written data into  EAB  is  retained when vccio supply 
fails, Can we avoid the data loss by having Supply backup for only
vccint . (nINIT_CONG pulled to  vccint.).

Explained below

After  writing  memory initialize data into  EAB during  power on
configuration,  later  I have loaded application  data   into  EAB. 
This application data has to be retained , when ever  there is power
failure.

  Now the  question is , whether  vccint supply  voltage is sufficient
 as  backup power supply  to retain memory data   or   both  Vccint  &
 Vccio are required  to hold memory  data .

please help me in deciding ,for adverse conditions.

-Satish K

Article: 48996
Subject: Re: Xilinx ISE 4.2i Student edition on Windows XP
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 29 Oct 2002 10:24:43 +0000
Links: << >>  << T >>  << A >>
Sorry, I was not using version 5.1i (I have not downloaded it yet): I am
using version 4.2 or thereabouts on Windows XP.

Article: 48997
Subject: Information--conference paper
From: "Stelios Zontos" <zontos@telecom.ntua.gr>
Date: Tue, 29 Oct 2002 12:28:09 +0200
Links: << >>  << T >>  << A >>
Dear all,

me and my partners have designed and successfully implemented the electronic
part of a WDM ring node (Burst Mode Rx/Tx, data storage, MAC protocol). The
electronic part consists of two boards and many FPGAs. We tested our
equipment and we are now interested to present our work to a
conference/journal. Can somebody give me information on some conferences and
on the content of the paper? It is the first time we like to edit a paper on
hardware implementation :)

Thanks in advance
H.




Article: 48998
Subject: Re: Modelsim help
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 29 Oct 2002 10:31:32 +0000
Links: << >>  << T >>  << A >>
Peng Cong wrote:
"Xilinx ISE 5.1 + Modelsim 5.5e

When I use modelsim for simulation, it always propmt
"Evaluation memory limit reached".
How can I solve this problem?"

Unfortunately this is a problem with the restricted
version of Modelsim which Xilinx gives away for free.
You can choose to:
* not run your simulation in Modelsim;
* make a smaller system to simulate, small enough to fit in the memory
restrictions of Modelsim XE;
or
* buy a full copy of Modelsim.

Article: 48999
Subject: Re: Xilinx ISE 4.2i Student edition on Windows XP
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 29 Oct 2002 10:38:27 +0000
Links: << >>  << T >>  << A >>
Someone other than the topic starter said:

"i download Xilinx ISE WebPACK version about 5.1i from the web,but it
can not run on my computer,the operate system is windows 98.i don't know
why?"

Version 4.2 runs on Windows 98, but maybe version 5.1i does not. Try
getting an old version from
http://www.xilinx.com/webpack/classics/wpclassic/



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