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Messages from 51075

Article: 51075
Subject: Re: BP programmer questions, prices, alternatives
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Mon, 30 Dec 2002 10:48:23 -0500
Links: << >>  << T >>  << A >>
Dave,

I can't answer your specific questions, but I have a BP-1200, and I
absolutely love it.  The software is great (they finally got a Windows
application...) and software upgrades are free, or at least have been for
the 8 years I've had mine!  Their device support is unparalled, and their
support in general has been stupendous as well.

I got mine with the universal 84 pin PLCC adapter (optional) and DIP48
adapter, and also have some adapters from ET to use with the 48 pin DIP
adapter to program SOL packages.

You can download the application software and run it in demo mode, and see
what it does.

Regards,

Austin


"Dave" <dfnr2@yahoo.com> wrote in message news:m34r8yao2s.fsf@yahoo.com...
> Hello,
>
> I'm thinking of letting my Data I/O coast on without further software
> updates, and put the money into a new BP programmer.  I'm frustrated
> by the lack of pricing information on the BP website, or any
> distributors' sites.  Would anyone who recently bought a BP-1200 care
> to post some prices for the 1200, any of the extra modules, any
> upgrades, and the software upgrade to generate serial numbers.
>
> Also, is it possible to write your own little program to generate
> serial numbers, and have the free BP software call it, or do you still
> have to pay for an "advanced features" package?
>
> It would be great if some kind soul posted some info here;
> alternatively, I'd be grateful for a scanned pricelist by email.  I've
> contacted the local rep, but since there's no reply, I assume he's on
> vacation.
>
> Thanks for any info,
>
> David.
> --
> dave - dfnr2@yahoo.com
>



Article: 51076
Subject: Re: what is bus keeper / bus gate.
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Mon, 30 Dec 2002 15:53:28 GMT
Links: << >>  << T >>  << A >>
On 29 Dec 2002 23:50:59 -0800, sri_valli_design@hotmail.com (Valli)
wrote:

>Hai all,
>
>Can someone pass some functional info., and vhdl/verilog model for bus
>keeper, and bus gate logic!

A bus keeper is a device that maintains the last level driven on a
tri-state bus.
It has one connection (not including power supply) that acts as both
an input and an output.  If the signal is high, then it drives a weak
high out.  If the signal is low, then it drives a weak low out.

You can find keeper source (VHDL and Verilog) in the Xilinx unisim
library.

"Bus gates" (if I understand your terminology) are devices that can
act like bidirectional switches or transmission gates and are used to
connect two tri-state signals together.
These can be modeled directly using a Verilog gate primitive.
VHDL is a little harder, but it can be done.  Ben Cohen's zero ohm
resistor model shows how.  I found a copy of the model in the file
"synplify.vhd" in an installation of Synplify.

Regards,
Allan.

Article: 51077
Subject: Re: BP programmer questions, prices, alternatives
From: "Mathew Orman" <orman@nospam.com>
Date: Mon, 30 Dec 2002 18:48:09 +0100
Links: << >>  << T >>  << A >>
Correct...
I you are going to be in the business of programming various devices than
spending $5000 is well justify,
but if you are developing based on the "state of the art" programmable logic
than... ones again
try LATTICE ispLSI it comes with one simple cable to program all of them in
circuit and you don't even need to switch of the power while you are
programming.

"Austin Franklin" <austin@da98rkroom.com> wrote in message
news:v10qejg3laog26@corp.supernews.com...
> I didn't know the Lattice ispLSI could program over 3000 different
> programmable devices.  Silly me.  Heck, I didn't even know they made a
> device programmer!
>
> ;-)
>
> "Mathew Orman" <orman@nospam.com> wrote in message
> news:aupgb7$157$1@news.tpi.pl...
> > Do not waist money and time,  switch to LATTICE ispLSI !
> >
> > "Dave" <dfnr2@yahoo.com> wrote in message
news:m34r8yao2s.fsf@yahoo.com...
> > > Hello,
> > >
> > > I'm thinking of letting my Data I/O coast on without further software
> > > updates, and put the money into a new BP programmer.  I'm frustrated
> > > by the lack of pricing information on the BP website, or any
> > > distributors' sites.  Would anyone who recently bought a BP-1200 care
> > > to post some prices for the 1200, any of the extra modules, any
> > > upgrades, and the software upgrade to generate serial numbers.
> > >
> > > Also, is it possible to write your own little program to generate
> > > serial numbers, and have the free BP software call it, or do you still
> > > have to pay for an "advanced features" package?
> > >
> > > It would be great if some kind soul posted some info here;
> > > alternatively, I'd be grateful for a scanned pricelist by email.  I've
> > > contacted the local rep, but since there's no reply, I assume he's on
> > > vacation.
> > >
> > > Thanks for any info,
> > >
> > > David.
> > > --
> > > dave - dfnr2@yahoo.com
> > >
> >
> >
>
>



Article: 51078
(removed)


Article: 51079
Subject: Re: interface DRAM to FPGA
From: "Eric Pearson" <ecp@mgl.ca>
Date: Mon, 30 Dec 2002 18:37:24 GMT
Links: << >>  << T >>  << A >>

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3E1057E4.77E3799C@yahoo.com...
> Rob Finch wrote:
> >
> > Hi,
> >
> > Just wondering if anyone has interfaced ordinary DRAM (72 pin simms) to
an
> > FPGA and are series damping resistors required ?
>
> I have not used standard DRAM with an FPGA, only SDRAM.  But the
> electrical issues are the same.  The series damping resistors are used
> for impedance matching to minimize reflections.  If your traces are only
> 3 inches or so you won't need to worry with this.  If your traces are 6
> inches or more you definitely need to consider the issue.  In between it
> depends on the details of your driver speed.  So try to keep all your
> traces as short as possible.  The RAS and CAS lines are of special
> concern since reflections can cause double clocking of the DRAM.

I have sucessfully used 72 pin DRAM simm's with a number of FPGA designs.
Trick is too meet all the dram timing specs, and keep the
high fanout ras / cas edges fast and monotonic (as stated above)

Controlled impedance drive is usually required. individual series damped
drivers
for each address and control pin is usually sufficient for a single SIMM.

A pll multiplied clock or other methods can be used to carefully place
ras and cas edges, while keeping address and data synchonous
at the fpga boundary edge.

Sdram's are much nicer.

Regards...

Eric Pearson



Article: 51080
Subject: Xilinx Gate Counts
From: Adam Elbirt <aelbirt@nac.net>
Date: Mon, 30 Dec 2002 14:15:49 -0500
Links: << >>  << T >>  << A >>
Anyone know of an application note or on-line documentation where Xilinx 
specifies how they calculate their estimated gate counts for Virtex (or 
other families) implementations?

Adam


Article: 51081
Subject: Re: thermal issues on FPGA
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Mon, 30 Dec 2002 14:25:34 -0500
Links: << >>  << T >>  << A >>
Good News!!! (at least for me)

    Relocating the fans to the opposite side of the cabinet elimanated the
problem (or at least put it below the noise floor of the remainder of the
system).

Thanks to all for the advice given.

Theron


"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:3E0FCAA4.5F10@designtools.co.nz...
> Theron Hicks wrote:
> >
> > Jim Granville wrote:
> >
> > > Theron Hicks (Terry) wrote:
> > > >
> > > > Actually Glen, the device I am building _is_ a hot wire anemometer.
The control
> > > > system is Pulse Width Modulated as opposed to the conventional
Whetstone Bridge
> > > > based constant temperature anemometer.  By using PWM we can get a
better
> > > > transfer function and use a simple counter instead of an A/D
converter.  Also,
> > > > the system has a few other advantages.  (See United States Patent
#03603147.)
> > > > The real problem is that the fan ENI shows up in the Spectral Plot
for the
> > > > recovered data from the anemometer.
> > >
> > > I would have expected the two to have different frequency bands - the
> > > FAN will be 100's of Hz, and the airflow sub-Hz ?
> > >
> >
> > Jim,
> >     As it turns out the frequency of interest for the flow is up to on
the order of
> > several KHz.  The frequency of interest is defined by the size of the
feature to be
> > resolved and the velocity of the flow.  We look at features on the order
of 1mm in a
> > 10m/S flow.  Thus maximum frequency of interest is about 10KHz  The fan
has spectral
> > content from as low as about 150Hz to as high as 2.5KHz.  The
competetive full analog
> > product has a frequency response of about 30KHz at 10m/s flow velocity.
>
>    Hmm, there goes that idea...
>  More thermal mass -> Fins seems the best approach, & maybe experiment
> with a small compressed air cylinder - that will have no EMC :)
>  It will have a finite life, but should tell you where the noise-floor
> is, for comparitive testing / demonstrations.
>
> -jg



Article: 51082
Subject: Re: BP programmer questions, prices, alternatives
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Mon, 30 Dec 2002 16:00:08 -0500
Links: << >>  << T >>  << A >>
They are very nice parts, but the don't fill every need...hence the need for
being able to program other devices.

You don't have to be in the business of programming various devices to
require the use of a device programmer...any decent engineering/R&D facility
should have one IMO.  It's sometimes penny wise and pound foolish to use $5
devices, when $2 could just as easily have been used, just to save
$5000...obviously, there is a break-even point, and obviously, the field
upgradeability of ISP devices is nice...but again, they don't fill
everyone's needs (cost, performance, size...)...so other devices exist that
require a programmer.

Austin

"Mathew Orman" <orman@nospam.com> wrote in message
news:auq0r9$9v6$1@news.tpi.pl...
> Correct...
> I you are going to be in the business of programming various devices than
> spending $5000 is well justify,
> but if you are developing based on the "state of the art" programmable
logic
> than... ones again
> try LATTICE ispLSI it comes with one simple cable to program all of them
in
> circuit and you don't even need to switch of the power while you are
> programming.
>
> "Austin Franklin" <austin@da98rkroom.com> wrote in message
> news:v10qejg3laog26@corp.supernews.com...
> > I didn't know the Lattice ispLSI could program over 3000 different
> > programmable devices.  Silly me.  Heck, I didn't even know they made a
> > device programmer!
> >
> > ;-)
> >
> > "Mathew Orman" <orman@nospam.com> wrote in message
> > news:aupgb7$157$1@news.tpi.pl...
> > > Do not waist money and time,  switch to LATTICE ispLSI !
> > >
> > > "Dave" <dfnr2@yahoo.com> wrote in message
> news:m34r8yao2s.fsf@yahoo.com...
> > > > Hello,
> > > >
> > > > I'm thinking of letting my Data I/O coast on without further
software
> > > > updates, and put the money into a new BP programmer.  I'm frustrated
> > > > by the lack of pricing information on the BP website, or any
> > > > distributors' sites.  Would anyone who recently bought a BP-1200
care
> > > > to post some prices for the 1200, any of the extra modules, any
> > > > upgrades, and the software upgrade to generate serial numbers.
> > > >
> > > > Also, is it possible to write your own little program to generate
> > > > serial numbers, and have the free BP software call it, or do you
still
> > > > have to pay for an "advanced features" package?
> > > >
> > > > It would be great if some kind soul posted some info here;
> > > > alternatively, I'd be grateful for a scanned pricelist by email.
I've
> > > > contacted the local rep, but since there's no reply, I assume he's
on
> > > > vacation.
> > > >
> > > > Thanks for any info,
> > > >
> > > > David.
> > > > --
> > > > dave - dfnr2@yahoo.com
> > > >
> > >
> > >
> >
> >
>
>



Article: 51083
Subject: xilinx virtex "done" pin problem with jtag
From: naveengupta2003@yahoo.com (Naveen Gupta)
Date: 30 Dec 2002 14:12:21 -0800
Links: << >>  << T >>  << A >>
Hi!,
  I am employing the jtag mode for configuring the virtex-2 part.
  I am using impact with cables for that.
  The problem is that the done pin does not go high even though impact
  confirms that the configuration went fine[thru' scanning out the
  status register "init" and "done" bits from the status register].

  Could someone help me with this.
  Obviously the mode bits are set to jtag mode, the startup clock
  is jtag, and apparently the configuration went smmoth[as the status
  register readout is satisfactory to impact]: the "done" pin is 
  not updated however.

Thanks and regards,
Naveen Gupta

Article: 51084
Subject: VLSI training and prospects?
From: anglomont@yahoo.com (TI)
Date: 30 Dec 2002 15:10:23 -0800
Links: << >>  << T >>  << A >>
Hi group,
-is a course like the one at www.naics.ca
enough to qualify an engineer to find work with vlsi, or masters is needed?
-how risky is a ASIC design career anyway ie
what is the chance Berkeley's 'chip in a day' Simulink to silicon aproach
succeeds completely?
(www.mathworks.com/mason/tag/ proxy.html?dataid=1248&fileid=4207)
- Do you think Asian vlsi engineers are going to be dumped completely or
just partly as soon as they become too expensive compared to people in
some other underdeveloped country? (http://www.eetimes.com/story/OEG20020627S0032)

thanx

Article: 51085
Subject: Re: xilinx virtex "done" pin problem with jtag
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Tue, 31 Dec 2002 04:00:52 GMT
Links: << >>  << T >>  << A >>
Naveen,

We had a similar problem with the Virtex-II. In fact, we knew that the
configuration had completed properly because the part started to get warm,
but no DONE going high!.

The problem was, in bitgen (as I recall) there is an option to enable the
PWRDWN or HSWAP_EN stuff (I can't remember exactly what it was) and its
relationship to the DONE pin. Once we disabled that feature the done pin
went high. I remember yelling loudly when we finally got it working, after
several hours of trying different things. The option talks about the DONE
pin showing some status other than just indicating the "done" condition.
Select the option that makes the DONE pin only its normal function.

Your local Xilinx FAE should know about this bitgen option (and how to turn
it off).

Good luck,
Bob

"Naveen Gupta" <naveengupta2003@yahoo.com> wrote in message
news:e68da158.0212301412.313675a8@posting.google.com...
> Hi!,
>   I am employing the jtag mode for configuring the virtex-2 part.
>   I am using impact with cables for that.
>   The problem is that the done pin does not go high even though impact
>   confirms that the configuration went fine[thru' scanning out the
>   status register "init" and "done" bits from the status register].
>
>   Could someone help me with this.
>   Obviously the mode bits are set to jtag mode, the startup clock
>   is jtag, and apparently the configuration went smmoth[as the status
>   register readout is satisfactory to impact]: the "done" pin is
>   not updated however.
>
> Thanks and regards,
> Naveen Gupta
>



Article: 51086
Subject: Re: dualport ram instantiation in Spartan IIE
From: Igor Orlovich <igoro@hotmail.com>
Date: Tue, 31 Dec 2002 04:13:19 GMT
Links: << >>  << T >>  << A >>
Have you tried simply following Xilinx's examples of inferring Dual Port Ram 
instead? 
sean da wrote:

> I used Xilinx Core Generator to build simulation model for dualport
> Ram, and it went through the synthesis phase by XTS, but during
> implementation phase, I got the error message said "dualport_ram is
> unexpected, ....", dualport_ram is my dualport RAM name. What is the
> black box name should I put in my code to pass this implementation
> phase as well as Place/Route phase? Thanks!


Article: 51087
Subject: VLSI training in Germany, the Balcans or Russia?
From: anglomont@yahoo.com (TI)
Date: 30 Dec 2002 22:53:53 -0800
Links: << >>  << T >>  << A >>
Hi,

 I would like to specialize in the area of VLSI so I wonder if there
is an institution/company near Stuttgart or Munnich in Germany or
Budapest in Hungary or elsewhere in Romania, Bulgaria, or Moscow in
Russia, that offers such training course that  during 2-4 months
covers perhaps:
 -Techniques for digital system design
 -Hardware description languages 	
 -Design methodology for VLSI circuits and systems: ASIC, FPGA, PLD  
 -Employing EDA tools like:  ModelSim, Leonardo, Xilinx, Altera, etc. 
 please let me know of any details 

 thank you very much 
 and have a Happy New Year

TI

Article: 51088
Subject: Re: distributed computing with Modesim
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 31 Dec 2002 11:13:29 +0100
Links: << >>  << T >>  << A >>
nachikap@yahoo.com (Nachiket Kapre) writes:

> > One big problem is that the license cost is linear, while the
> > performance increase is usually not. Personally I would think it would
> > be great if could throw 16 $3,000 PC's at the problem and get an 8x
> > increase in performance. However, a simulation license usually costs
> > 10-15 times as much as a PC. If a vendor was selling a distributed
> > simulator for less than linear cost this could be worthwhile.
> 
> do you have figures or studies that substantiate this assertion? I
> plan to run a small proto run of this kind on a small simple design
> and try to provide figures. If they are already avaiable then it will
> save me this time.

The speedup factor I quoted was a guess. It's of course design
dependent. I've been working on a design where I got a close to linear
speedup (for only 2-4 nodes). The design was partitioned manually and
the interface between the design was a specified bus. The glue was a
socket library which was implemented as a PLI library in the verilog
case. In some of the cases the modules were written in C++ in others
they were written in verilog.

> Well, if you go up this thread, David Casselman did point out
> SimCluster by avery design www.avery-design.com . You might want to
> see their simulators.

Thanks for the link. Their product description says: "SimCluster also
supports distributed simulation using other vendors Verilog
simulators, hardware accelerators, and emulators." It appears that
this is a PLI library similar to the one described above. Does anybody
have any details? They also use Ethernet as an interconnect. I would
assume they would benefit from using a low latency interconnect like
SCI.

> If I am not mistaken Leospec does have a thing known as incrememntal
> synthesis, wherein we synthesise smaller blocks of the design withotu
> flattening them and stitch them all up in the end. This seems ideal
> and fertile for parallel concurrent synthesis, with no communication
> penalties as in simulations. THe EDA vendors should have jumped at
> parallel synthesis much before the notion of concurrent simulations
> took wing. I am not entirely clear about how to manage a concurrent
> PAR.

Synthesis and PAR algorithms are usually exploring alternatives,
typically using an A* search or similar. Each node in a cluster will
explore its own part of the search three. The amount of communication
between the nodes is fairly low. Any module(s) which is not flattened
could be synthesized separately on a node without any communication
with any other modules (assuming that the port list has been checked
by the parser node).

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 51089
Subject: Re: BP programmer questions, prices, alternatives
From: Aurash Lazarut <aurash@xilinx.com>
Date: Tue, 31 Dec 2002 10:51:50 +0000
Links: << >>  << T >>  << A >>

--------------5FD43E0A3544ACAC99657C28
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dave

Try www.elnec.com
they have some nice hw programers universal and dedicated, stable
software, free upgrades, and yhey can implement an algorithm by request
if you have a strange part (not in the list with the supported ones)

Cheers,
Aurash

Dave wrote:

> Hello,
>
> I'm thinking of letting my Data I/O coast on without further software
> updates, and put the money into a new BP programmer.  I'm frustrated
> by the lack of pricing information on the BP website, or any
> distributors' sites.  Would anyone who recently bought a BP-1200 care
> to post some prices for the 1200, any of the extra modules, any
> upgrades, and the software upgrade to generate serial numbers.
>
> Also, is it possible to write your own little program to generate
> serial numbers, and have the free BP software call it, or do you still
> have to pay for an "advanced features" package?
>
> It would be great if some kind soul posted some info here;
> alternatively, I'd be grateful for a scanned pricelist by email.  I've
> contacted the local rep, but since there's no reply, I assume he's on
> vacation.
>
> Thanks for any info,
>
> David.
> --
> dave - dfnr2@yahoo.com

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/

phone:  353 01 4032639
fax:    353 01 4640324





Article: 51090
Subject: Unused FPGA I/O Pins?
From: Andreas Schweizer <aschweiz@iiic.ethz.ch>
Date: 31 Dec 2002 14:06:56 +0100
Links: << >>  << T >>  << A >>
Hi everyone,

in the design I'm working at, we're using a Virtex-II
FPGA in the FG 676 package. Many of the I/O pins are
however unused. Is it a good idea to connect these
to GND? or leave them unconnected or connect some to
GND and some to Vcco?

Thank you for reading and a happy 2003 to all!
Andy


Article: 51091
Subject: Re: BP programmer questions, prices, alternatives
From: "Mathew Orman" <orman@nospam.com>
Date: Tue, 31 Dec 2002 14:36:44 +0100
Links: << >>  << T >>  << A >>
Well, in my case the device programmers where sitting on the shelf governing
the dust and finally I've sold them to used equipment shop.
Also I had the same thoughts when decided to purchase them.
But every case is different so anyway to all of you....

Have a happy new year!



"Austin Franklin" <austin@da98rkroom.com> wrote in message
news:v11cupquavmj69@corp.supernews.com...
> They are very nice parts, but the don't fill every need...hence the need
for
> being able to program other devices.
>
> You don't have to be in the business of programming various devices to
> require the use of a device programmer...any decent engineering/R&D
facility
> should have one IMO.  It's sometimes penny wise and pound foolish to use
$5
> devices, when $2 could just as easily have been used, just to save
> $5000...obviously, there is a break-even point, and obviously, the field
> upgradeability of ISP devices is nice...but again, they don't fill
> everyone's needs (cost, performance, size...)...so other devices exist
that
> require a programmer.
>
> Austin
>
> "Mathew Orman" <orman@nospam.com> wrote in message
> news:auq0r9$9v6$1@news.tpi.pl...
> > Correct...
> > I you are going to be in the business of programming various devices
than
> > spending $5000 is well justify,
> > but if you are developing based on the "state of the art" programmable
> logic
> > than... ones again
> > try LATTICE ispLSI it comes with one simple cable to program all of them
> in
> > circuit and you don't even need to switch of the power while you are
> > programming.
> >
> > "Austin Franklin" <austin@da98rkroom.com> wrote in message
> > news:v10qejg3laog26@corp.supernews.com...
> > > I didn't know the Lattice ispLSI could program over 3000 different
> > > programmable devices.  Silly me.  Heck, I didn't even know they made a
> > > device programmer!
> > >
> > > ;-)
> > >
> > > "Mathew Orman" <orman@nospam.com> wrote in message
> > > news:aupgb7$157$1@news.tpi.pl...
> > > > Do not waist money and time,  switch to LATTICE ispLSI !
> > > >
> > > > "Dave" <dfnr2@yahoo.com> wrote in message
> > news:m34r8yao2s.fsf@yahoo.com...
> > > > > Hello,
> > > > >
> > > > > I'm thinking of letting my Data I/O coast on without further
> software
> > > > > updates, and put the money into a new BP programmer.  I'm
frustrated
> > > > > by the lack of pricing information on the BP website, or any
> > > > > distributors' sites.  Would anyone who recently bought a BP-1200
> care
> > > > > to post some prices for the 1200, any of the extra modules, any
> > > > > upgrades, and the software upgrade to generate serial numbers.
> > > > >
> > > > > Also, is it possible to write your own little program to generate
> > > > > serial numbers, and have the free BP software call it, or do you
> still
> > > > > have to pay for an "advanced features" package?
> > > > >
> > > > > It would be great if some kind soul posted some info here;
> > > > > alternatively, I'd be grateful for a scanned pricelist by email.
> I've
> > > > > contacted the local rep, but since there's no reply, I assume he's
> on
> > > > > vacation.
> > > > >
> > > > > Thanks for any info,
> > > > >
> > > > > David.
> > > > > --
> > > > > dave - dfnr2@yahoo.com
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>



Article: 51092
Subject: Re: Unused FPGA I/O Pins?
From: Kumaran Selvaratnam <selvars@yahoo.com>
Date: Tue, 31 Dec 2002 10:59:00 -0500
Links: << >>  << T >>  << A >>
Hi Andreas,

I am not familiar with FG 676 but in general, you have to drive the 
inputs and leave the outputs unconnected. However, for specific 
information consult the datasheets of the particular FPGA you are 
planning to use. This is what chip companies suggest.
Some of the chips provide I/O Configuration setup that can be done 
internally through software means.

Good Luck
Kumaran

Andreas Schweizer wrote:

> Hi everyone,
> 
> in the design I'm working at, we're using a Virtex-II
> FPGA in the FG 676 package. Many of the I/O pins are
> however unused. Is it a good idea to connect these
> to GND? or leave them unconnected or connect some to
> GND and some to Vcco?
> 
> Thank you for reading and a happy 2003 to all!
> Andy
> 
> 


Article: 51093
Subject: Re: Unused FPGA I/O Pins?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 31 Dec 2002 10:48:10 -0800
Links: << >>  << T >>  << A >>
If they are unused, just leave them unconnected.
But, if you want to be nice and reduce potential ground bounce, then you
can configure these pins as permanently active Low outputs ( strongest
option) and connect them on the pc-board to ground.
That way you have additional ground connections from the inside to the
ground plane, and although the resistive part may be not perfect, all
the lead inductances are in parallel, and thus reduce the inductive
kick.

Happy New Year und ein Gutes Neues Jahr, hoffentlich besser als 2002.
Peter Alfke, Xilinx Applications
=============================
Andreas Schweizer wrote:

> Hi everyone,
>
> in the design I'm working at, we're using a Virtex-II
> FPGA in the FG 676 package. Many of the I/O pins are
> however unused. Is it a good idea to connect these
> to GND? or leave them unconnected or connect some to
> GND and some to Vcco?
>
> Thank you for reading and a happy 2003 to all!
> Andy


Article: 51094
Subject: Re: what is bus keeper / bus gate.
From: vhdlcohen@aol.com (ben cohen)
Date: 31 Dec 2002 12:08:45 -0800
Links: << >>  << T >>  << A >>
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3e1066be.16045482@netnews.agilent.com>...
....
> "Bus gates" (if I understand your terminology) are devices that can
> act like bidirectional switches or transmission gates and are used to
> connect two tri-state signals together.
> These can be modeled directly using a Verilog gate primitive.
> VHDL is a little harder, but it can be done.  Ben Cohen's zero ohm
> resistor model shows how.  I found a copy of the model in the file
> "synplify.vhd" in an installation of Synplify.
> 
> Regards,
> Allan.

The gate switch model is also at my site
http://www.vhdlcohen.com/ 

Ben

Article: 51095
Subject: Re: free fpga soft core
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 31 Dec 2002 19:33:56 -0800
Links: << >>  << T >>  << A >>
dasariware@yahoo.com (dasari) wrote in message news:<e1df9052.0212262205.65e4e8e6@posting.google.com>...
> Hi Rudi,
> 
> I tried in:
> http://www.opencores.org/projects/fpga/ -- only specs are there for
> FPGA core!
> {FPGA Core Specification Author: Marko Mlinar
> marko.mlinar@campus.fri.uni-lj.si
> Damjan Lampret damjan.lampret@yahoo.com Rev. 0.6}
> 
> http://www.asics.ws/fip_sub.html -- No soft core for FPGA model
> available.
> 
> I am looking for a FPGA model/core[embedded array like Varicore!](any
> LUT based architecture!), not the cores targeted to FPGAs.
> 
> Thanks,
> Dasari.

Sorry slight miscommunication here ! I though you where looking
for IP cores to implement in an FPGA, not for an FPGA IP Core.

Cheers,
rudi
------------------------------------------------
www.asics.ws   - Solutions for your ASIC needs -
NEW ! 4 New Free IP Cores this months (so far :*)
FREE IP Cores  -->   http://www.asics.ws/  <---
-----  ALL SPAM forwarded to: UCE@FTC.GOV  -----

Article: 51096
Subject: shift register implementation
From: lm_chan@hotmail.com (Lana)
Date: 31 Dec 2002 20:10:14 -0800
Links: << >>  << T >>  << A >>
I would like to design a module which will enable me to input 12-bit
samples and output 16-bit samples.  One implementation that I've
though of entails the design of shift register using 6 8-bit
registers.  However, this would entail that 4 cycles to load the
registers and 3 cycles to output the contents along with a bit of
logic to switch between the two modes.  Is there a more efficient
manner of doing this that will result in better bandwidth and resouce
usuage?

Thanks

Article: 51097
Subject: Re: BP programmer questions, prices, alternatives
From: John Eaton <johne@hpvcljte.vcd.hp.com>
Date: 1 Jan 2003 04:59:43 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga Dave <dfnr2@yahoo.com> wrote:
: Hello,

: I'm thinking of letting my Data I/O coast on without further software
: updates, and put the money into a new BP programmer.  I'm frustrated
: by the lack of pricing information on the BP website, or any
: distributors' sites.  Would anyone who recently bought a BP-1200 care
: to post some prices for the 1200, any of the extra modules, any
: upgrades, and the software upgrade to generate serial numbers.

We did that about 7 years ago and are glad we did. My only complaint
is that I once looked inside and the mechanical packaging seemed a bit
shabby for an instrument in that price range. 

It would be nice if they could dump the parallel port interface and go
with either ethernet or USB.

I for one am sick and tired of all these programmers with all their 
plug in adapter modules that all seem to cost $495 each. Do you know
how many differnet adapter modules I have for a 84 pin plcc package?
It would really be nice if there were a standard to allow plug in adapters
to work over various vendors programmers.


John Eaton

reply address is a spam sink. use first.last@hp.com

Article: 51098
Subject: bitfile back to ncd?
From: "Steve Hurlock" <steven.hurlock@unisys.com>
Date: Wed, 1 Jan 2003 01:34:44 -0500
Links: << >>  << T >>  << A >>
Hello All,
Does any one have any way to get an ncd file from bit file?

Thanks,
Steve H



Article: 51099
Subject: Any Xilinx Design Language(.xdl) document?
From: Liao Jirong <iscp1097@nus.edu.sg>
Date: Wed, 1 Jan 2003 16:58:59 +0800
Links: << >>  << T >>  << A >>
To understand how the mapping affects the delay, I try to look into the
.xdl output, which is converted from .ncd output from Xilinx tools. Is
there any document on this?

Btw: anybody know how to count the delay from the Xilinx mapping output?

Thanks.
 




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