Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 57025

Article: 57025
Subject: Re: How to trace the FPGA signals without a logical analyzer?
From: Steve Lass <lass@xilinx.com>
Date: Fri, 20 Jun 2003 17:41:59 -0600
Links: << >>  << T >>  << A >>
Check out Chipscope Pro:
http://www.xilinx.com/ise/verification/chipscope_pro.htm

It builds a logic analyzer inside the FPGA using available logic and 
memory resources.

Steve

ouadid abdelkarim wrote:

>Hi fellows,
>I want to ask about any way to use an FPGA (xilinx) board without a logical analyzer and still can see all the waves. Is there any software that can be used with a board that is connected to a simple PC?
>thanks
>
>  
>


Article: 57026
Subject: Re: Quartus bug or wrong VHDL?
From: Ken McElvain <ken@synplicity.com>
Date: Sat, 21 Jun 2003 00:33:20 GMT
Links: << >>  << T >>  << A >>
Synplify and all the 3rd party tools will handle this style
of VHDL just fine.  There is nothing wrong with the code.
"Z" can be stored in a vhdl signal and the synthesis tool
should make the necessary hardware.  Apparently Quartus didn't.


Martin Schoeberl wrote:

> Since Leonardo is not longer available from Altera I'm trying to use Quartus
> for synthesis. But I get a different output with Quartus. I tracked the
> problem down and now my qustion is: Is it a bug or sloopy written VHDL?
> 
> The problem is setting output to tristate. See following VHDL code: I asumed
> that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> will not change when changing state to 'rd1'. This was ok with Leonardo. But
> with Quartus I have to set d to 'Z' again in every state. What is the
> correct VHDL code?
> 
> Martin
> 
> process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
> begin
>     if (reset='1') then
>         state <= idl;
>         a <= "ZZZZZZZZZZZZZZZZZZZ";
>         d <= "ZZZZZZZZ";
>         ....
>     elsif rising_edge(clk) then
>         case state is
>             when idl =>
>                 a <= "ZZZZZZZZZZZZZZZZZZZ";
>                 d <= "ZZZZZZZZ";
> 
>                 if (mem_rd='1') then
>                     a <= din(16 downto 0) & "00";
>                     nram_cs <= '0';
>                     ram_access <= '1';
>                     i := ram_cnt;
>                     nrd <= '0';
>                     state <= rd1;
>                 elsif (mem_wr='1') then
>                     ...
>             when rd1 =>
>                 d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but
> NOT in Leonardo
>                 i := i-1;
>                 if (i=0) then
>                     state <= rd2;
>                     mem_din(7 downto 0) <= d;
>                     a(1 downto 0) <= "01";
>                     i := ram_cnt;
>                 end if;
> 
>             when rd2 =>
>                 d <= "ZZZZZZZZ"; -- same as in rd1
>                 i := i-1;
>                 if (i=0) then
>                     ...
> 
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone: http://www.jopdesign.com/cyclone/
> 
> 
> 


Article: 57027
Subject: Re: No longer talking about power consumption....
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 20 Jun 2003 20:45:32 -0400
Links: << >>  << T >>  << A >>
"Nicholas C. Weaver" wrote:
> 
> In article <3EF39237.ACC68E6D@yahoo.com>,
> rickman  <spamgoeshere4@yahoo.com> wrote:
> >> While there's little hope to squeeze more out of the Spartan-3 or the
> >> Cyclone family beyond what's announced, I'm looking forward to the NextGen
> >> products producing a more "optimum" available I/O to Logic ratio.
> >
> >That won't happen unless they start changing the way they do IO.  I have
> >read about a few companies that have a method of putting the IO pad on
> >top of the logic.  This will pretty much eliminate the perimeter length
> >issue in determining how many IOs a chip can have.  So far none of the
> >PLD makers have adopted this method.  I hope they catch on to this newer
> >technology.
> 
> Area pads (C4 solder ball style) flip-chips have been fairly common in
> the microprocessor world for a while.
> 
> However I think they are still a lot more costly than lead frame or
> FC-lead frame packaging, which is a big BIG deal on the cost-sensitive
> parts.
> 
> What I'd like to see is two versions, one which uses C4 solderballs to
> mount to a very high pincount frame, and the other (which only
> populates 1/4 of the pads) as a chip-scale BGA which uses wafer-level
> packaging to lower the package cost and provide for a decent amount of
> I/Os in a small footprint.  But that may be a fair bit away  in the future.

I am referring to a new technology that a couple of companies are
starting to use that is still low cost and accommodates wire bonding. 
Seems the pressure of wire bonding is not normally compatible with the
other processes of making transistors.  I belive it was VLSI that
developed this (or bought it from someone else).  But it was a few
months ago that I read about it and I don't remember the details other
than that they were going to be making chips with it about now.  I seem
to recall that it would support three rows of pads without using any
more chip area.  I think the wire bonding gets tricky with more than
three rows.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57028
Subject: Re: Quartus bug or wrong VHDL?
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 20 Jun 2003 20:52:38 -0400
Links: << >>  << T >>  << A >>
That may be true.  But I would still recommend a coding style change.  I
prefer to picture the hardware I want and then write the code to
describe it.  This style mixes the code for the logic, FFs and tristate
buffers into one process which makes it hard to picture exactly what
will be generated.  Unlike some designers, I *do* care since many
designs need to optimize the density.  If you can't anticipate the logic
produced, it is hard to tell if it is anything like optimal.  

Also, I once did a project which ended up use three different synthesis
packages during the course of about 6 months.  I learned a very valuable
lesson in writing code that *every* package will accept!  


Ken McElvain wrote:
> 
> Synplify and all the 3rd party tools will handle this style
> of VHDL just fine.  There is nothing wrong with the code.
> "Z" can be stored in a vhdl signal and the synthesis tool
> should make the necessary hardware.  Apparently Quartus didn't.
> 
> Martin Schoeberl wrote:
> 
> > Since Leonardo is not longer available from Altera I'm trying to use Quartus
> > for synthesis. But I get a different output with Quartus. I tracked the
> > problem down and now my qustion is: Is it a bug or sloopy written VHDL?
> >
> > The problem is setting output to tristate. See following VHDL code: I asumed
> > that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> > will not change when changing state to 'rd1'. This was ok with Leonardo. But
> > with Quartus I have to set d to 'Z' again in every state. What is the
> > correct VHDL code?
> >
> > Martin
> >
> > process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
> > begin
> >     if (reset='1') then
> >         state <= idl;
> >         a <= "ZZZZZZZZZZZZZZZZZZZ";
> >         d <= "ZZZZZZZZ";
> >         ....
> >     elsif rising_edge(clk) then
> >         case state is
> >             when idl =>
> >                 a <= "ZZZZZZZZZZZZZZZZZZZ";
> >                 d <= "ZZZZZZZZ";
> >
> >                 if (mem_rd='1') then
> >                     a <= din(16 downto 0) & "00";
> >                     nram_cs <= '0';
> >                     ram_access <= '1';
> >                     i := ram_cnt;
> >                     nrd <= '0';
> >                     state <= rd1;
> >                 elsif (mem_wr='1') then
> >                     ...
> >             when rd1 =>
> >                 d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but
> > NOT in Leonardo
> >                 i := i-1;
> >                 if (i=0) then
> >                     state <= rd2;
> >                     mem_din(7 downto 0) <= d;
> >                     a(1 downto 0) <= "01";
> >                     i := ram_cnt;
> >                 end if;
> >
> >             when rd2 =>
> >                 d <= "ZZZZZZZZ"; -- same as in rd1
> >                 i := i-1;
> >                 if (i=0) then
> >                     ...


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57029
Subject: Re: Quartus bug or wrong VHDL?
From: "Rob Dekker" <rob@verific.com>
Date: Fri, 20 Jun 2003 18:44:52 -0700
Links: << >>  << T >>  << A >>

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:6GGIa.34485$RM6.474195@news.chello.at...
> Since Leonardo is not longer available from Altera I'm trying to use
Quartus
> for synthesis. But I get a different output with Quartus. I tracked the
> problem down and now my qustion is: Is it a bug or sloopy written VHDL?
>
> The problem is setting output to tristate. See following VHDL code: I
asumed
> that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> will not change when changing state to 'rd1'. This was ok with Leonardo.
But
> with Quartus I have to set d to 'Z' again in every state. What is the
> correct VHDL code?
>
> Martin
>
> process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
> begin
>     if (reset='1') then
>         state <= idl;
>         a <= "ZZZZZZZZZZZZZZZZZZZ";
>         d <= "ZZZZZZZZ";
>         ....
>     elsif rising_edge(clk) then
>         case state is
>             when idl =>
>                 a <= "ZZZZZZZZZZZZZZZZZZZ";
>                 d <= "ZZZZZZZZ";
>
>                 if (mem_rd='1') then
>                     a <= din(16 downto 0) & "00";
>                     nram_cs <= '0';
>                     ram_access <= '1';
>                     i := ram_cnt;
>                     nrd <= '0';
>                     state <= rd1;
>                 elsif (mem_wr='1') then
>                     ...
>             when rd1 =>
>                 d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but
> NOT in Leonardo
>                 i := i-1;
>                 if (i=0) then
>                     state <= rd2;
>                     mem_din(7 downto 0) <= d;
>                     a(1 downto 0) <= "01";
>                     i := ram_cnt;
>                 end if;
>
>             when rd2 =>
>                 d <= "ZZZZZZZZ"; -- same as in rd1
>                 i := i-1;
>                 if (i=0) then
>                     ...
>
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone: http://www.jopdesign.com/cyclone/
>
>

The crucial question is :
Do you ever assign 'd' to anything else but 'Z' ?

If you do, then you would need to specify the 'Z' assignment explicitly in
rd1 and rd2
(if you want to always set it to 'Z' in these states).

If you dont, 'd' will always be 'Z', and an optimizer can remove the logic
that
would otherwize be created to maintain the last value.

Depending on your answer, we could track down which tool is wrong
or if both are right.

Rob



Article: 57030
Subject: Re: Please help with clock signal
From: "Ed Stevens" <ed@stevens8436.fslife.co.uk>
Date: Fri, 20 Jun 2003 22:34:13 -0700
Links: << >>  << T >>  << A >>
Thanks for your reply.

I've added the following to my code just after the architecture line:

    attribute clock_buffer: string;
    attribute clock_buffer of R_CLK: signal is "ibufg";
    attribute clock_buffer of W_CLK: signal is "ibufg";

The code Synthersises correctly and im able to map R_CLK and W_CLK to
general purpose pins.  The trouble is the FPGA no longer recognises any
signals that goto the general purpose pins of R_CLK and W_CLK.  I have two
push buttons that I want to act as R_CLK and W_CLK, when they are connected
to the FPGA's dedicated clock pins everything works fine, when they are
connected to the I/O pins using the above code nothing works.

Any ideas on what im doing wrong?

Thanks for any further help,

"Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message
news:bcv1hu$3qd$1@newsg4.svr.pol.co.uk...
> Hi,
>
> Im getting the following error in the XILINX Project Navigator:
>
>
> ERROR:MapLib:93 - Illegal LOC on symbol "w_clk" (pad signal=w_clk) or
BUFGP
> symbol "w_clk_BUFGP" (output signal=w_clk_BUFGP), IPAD-IBUFG should only
be
> LOCed to GCLKIOB site.
>
>
> How can I assign w_clk to a general purpose I/O pin, rather than one of
the
> clock inputs?
>
> Thanks for any help,
>
>



Article: 57031
Subject: Quartus II VHDL 2 modules
From: blackpack3000@yahoo.com (Christopher)
Date: 20 Jun 2003 23:20:04 -0700
Links: << >>  << T >>  << A >>
Hi!

Does anyone have a simple example using 2 VHDL files that work with
Quartus II?  I am looking for a file that describes one function
(special gate) and the other file that uses the first file.  Say one
file describes some simple gate.  The second file uses that
description without having to rewrite all the code.

I have an application where I want to reuse the same gate but don't
want to rewrite it every time.  If no other solution exist, I will
rewrite it.

I figured someone had a simple 2 file example.  I have seen some
samples with flip-flops but they didn't seem to work at least as my
little understanding of the docs.

I'd appreciate it greatly if someone had 2 files where one arch uses
(port map) to another file such that it will work with Quartus II.

Any thoughts suggestions or links are greatly appreciated.
Thanks!

Article: 57032
Subject: Re: FPGA GPU (Spartan IIe 300K)
From: "Matt" <bielstein2002@attbi.com>
Date: Sat, 21 Jun 2003 07:43:58 GMT
Links: << >>  << T >>  << A >>
Try www.insight-electronics.com They make a S-IIE board with 300 and 600k
parts for a reasonable price.


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:bcs3k7$mca33$1@ID-84877.news.dfncis.de...
> "Bazaillion" <nospam@nospam.org> schrieb im Newsbeitrag
> news:3tr1fvoht0mhnbfaer4c2o39dij8v57rr0@4ax.com...
>
> > So could a Spartan IIe 300K be used to create a graphics processor
> > (GPU Only) for a homebrew console on
> > par with like a 16 Bit SuperNintendo (SNES) ?
>
> A a rough guess I would say this is possible. Most of the ressources in
the
> pacman from fpgaarcade.com is used for the Z80 implementation.
>
> > Or for that matter could any FPGA board under $1000 give this kind of
> > performance or could they even do better?
>
> The Spartan-IIE series is the way to go. Maybe there is a board available
> with a 400 or even 600k gate part.
> I dont know aboput Altera parts.
>
> --
> Regards
> Falk
>
>
>
>
>



Article: 57033
Subject: Re: FPGA configure through a PC parallel port.
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 21 Jun 2003 09:04:34 GMT
Links: << >>  << T >>  << A >>
On 20 Jun 2003 14:58:20 -0700, dgleeson@utvinternet.com (Denis Gleeson) wrote:
>Hello all
>
>I am in the process of configuring an FPGA using the Parallel port of
>a PC.
>My board also has a socket for a xilinx parallel programming
>cable(Parallel cable IV). This works fine and configures the device
>for me. What I am trying to do now is get my own software to configure
>the FPGA through a standard parallel cable.
>
>The device is a spartan XL XCS05XL.
>
>SO far I've used details from xilinx app note  on "Configuring FPGAs
>over a processor bus."
>
>Well my software is not configuring the device. One thing that seems
>odd is that I don't seem to be able to drive the DIN pin low. I can
>get it down to about 1V but no lower. I thought it might be the pin I
>was using from the control port of the parallel port but I started
>using a pin from the data port with no benefit.
>On this device the DIN and DOUT pins are the same.
>
>I suppose if I got a schematic of the Parallel IV cable I would see
>what I was doing wrong.
>
>Any suggestions?
>
>Thanks in advance for all assistance.
>
>Denis

Looking at this code may help:

   http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm


and the cable schematics are at:

   http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html
   http://toolbox.xilinx.com/docsan/3_1i/data/common/jtg/dppb/appb.htm


   An earlier version is at

   http://www.xilinx.com/support/programr/files/0380507.pdf

 

   



Philip Freidin
Fliptronics

Article: 57034
Subject: Re: Bidirectional bus (tristate issue) // with ABV comments
From: Thomas <tom3@protectedfromreality.com>
Date: Sat, 21 Jun 2003 09:06:27 GMT
Links: << >>  << T >>  << A >>
this is what seems to happen with HDL bencher. I think I'll have to start 
writing my own testbenches...


On 20 Jun 2003 16:10:20 -0700, ben cohen <vhdlcohen@aol.com> wrote:

> Thomas <tom3@protectedfromreality.com> wrote in message 
> news:<oprq2qzaummo2d8p@news3.news.adelphia.net>...
>> I have also a similar thread in comp.arch.fpga;
>>
>> apparently my code works well when the inout signal is used in the fpga; 
>> only when I assign the signal to a pin the simulation starts to fail.
>> I am using HDL bencher to generate the testscript and I wonder if it 
>> could be the reason: I set some values to be read with hdl bencher, and 
>> then it verifies every clock cycle the values are still there, but in 
>> the meantime, I might have switched the signal to output
>>
>> what do you think?
> I never used HDL bencher. Not clear as to exactly what you are saying.
> If I understand you correctly, the testbench checks for an expected
> value at every clock, and drives the inout signal with a hard value
> ('1' or '0') even when that port is in the "out" mode, rather than the
> "in" mode.  Thus, the TB is not driving Zs.    If that is the case,
> the TB is definitely in error.
>
> For the record, In TB design I generally use my own client/slave model
> instead of a commercial product.  That is described in my books.
> I am now moving toward assertion-based verification (ABV), and really
> liking PSL, property specification language, along with dynamic
> simulation verification.  I'll be exploring static, or formal
> verification soon.  ABV with PSL and simulation helps define design
> intent, expected operation, and alerts of errors.  PSL eases the
> design of the TB because it puts more of the "verifier" design onto
> PSL, instead of a user defined model.
> Ben
>
>>
>> On 19 Jun 2003 18:38:16 GMT, VhdlCohen <vhdlcohen@aol.com> wrote:
>>
>> >> modelsim shows my BUS_Data signal as conflicts all through the >> 
>> simulation;
>> > You  seem to have an error in a driving value from one of your 
>> drivers.  > The best way to debug this is to run the simulation until 
>> you get a > conflict,
>> > and then type: drivers bus_data  That will show you the source of each 
>> of > the drivers, and you can then get to
>> > the root of it.  What you have looks OK, but without a full 
>> understanding > of the design, it is
>> > difficult for me to find the error.  The "drivers" command would be 
>> the > first
>> > thing I would try.  --------------------------------------------------- 
>>
>>
>> --- >
>> >
>> > ----------------------
>> > Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 > 
>> http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following > 
>> textbooks: * Using PSL/SUGAR with Verilog and VHDL
>> > Guide to Property Specification Language for ABV, 2003 isbn 0-9705394- 
>> 4-4
>> > * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
>> > 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1
>> > * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923- 
>> > 8474-1
>> > * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0- 
>> 7923-> 8115
>> > ----------------------------------------------------------------------- 
>>
>>
>> --- >
>> >
>> > ----
>> >
>> >
>



Article: 57035
Subject: Re: Quartus bug or wrong VHDL?
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sat, 21 Jun 2003 10:17:03 GMT
Links: << >>  << T >>  << A >>
"Rob Dekker" <rob@verific.com> schrieb im Newsbeitrag
news:bd0deq$j07$1@slb5.atl.mindspring.net...
>
> "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
> news:6GGIa.34485$RM6.474195@news.chello.at...
> > Since Leonardo is not longer available from Altera I'm trying to use
> Quartus
> > for synthesis. But I get a different output with Quartus. I tracked the
> > problem down and now my qustion is: Is it a bug or sloopy written VHDL?
> >
> > The problem is setting output to tristate. See following VHDL code: I
> asumed
> > that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> > will not change when changing state to 'rd1'. This was ok with Leonardo.
> But
> > with Quartus I have to set d to 'Z' again in every state. What is the
> > correct VHDL code?
> >
> > Martin
> >
> > process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
> > begin
> >     if (reset='1') then
> >         state <= idl;
> >         a <= "ZZZZZZZZZZZZZZZZZZZ";
> >         d <= "ZZZZZZZZ";
> >         ....
> >     elsif rising_edge(clk) then
> >         case state is
> >             when idl =>
> >                 a <= "ZZZZZZZZZZZZZZZZZZZ";
> >                 d <= "ZZZZZZZZ";
> >
> >                 if (mem_rd='1') then
> >                     a <= din(16 downto 0) & "00";
> >                     nram_cs <= '0';
> >                     ram_access <= '1';
> >                     i := ram_cnt;
> >                     nrd <= '0';
> >                     state <= rd1;
> >                 elsif (mem_wr='1') then
> >                     ...
> >             when rd1 =>
> >                 d <= "ZZZZZZZZ"; -- this line is necessary in Quartus
but
> > NOT in Leonardo
> >                 i := i-1;
> >                 if (i=0) then
> >                     state <= rd2;
> >                     mem_din(7 downto 0) <= d;
> >                     a(1 downto 0) <= "01";
> >                     i := ram_cnt;
> >                 end if;
> >
> >             when rd2 =>
> >                 d <= "ZZZZZZZZ"; -- same as in rd1
> >                 i := i-1;
> >                 if (i=0) then
> >                     ...
> >
> > --------------------------------------------------------
> > JOP - a Java Processor core for FPGAs now
> > on Cyclone: http://www.jopdesign.com/cyclone/
> >
> >
>
> The crucial question is :
> Do you ever assign 'd' to anything else but 'Z' ?

Shure in the write states.

>
> If you do, then you would need to specify the 'Z' assignment explicitly in
> rd1 and rd2
> (if you want to always set it to 'Z' in these states).

Not really. The 'idl' state will always come befor the rdx states. So the
assignement in 'idl' should be enough.

The design is a 32 bit memory acces to 'slow' 8 bit sram (with 3 cycle read
and 4 cycle write). Without access the state machine sits in 'idle', on read
the transitions are idl -> rd1 -> rd2 -> rd3 -> rd4 -> idl, on write: idl ->
wr1 -> wr2 -> wr3 -> wr4 -> idl.

wr1 looks like:

   when wr1 =>
    i := i-1;
    d <= mem_dout(7 downto 0); -- write first byte
    if (i=1) then
     nwr_int <= '1';
    end if;
    if (i=0) then
      nwr_int <= '0';
      state <= wr2; -- goto state to write second byte
      a(1 downto 0) <= "01";
      i := ram_cnt+1;
    end if;

>
> If you dont, 'd' will always be 'Z', and an optimizer can remove the logic
> that
> would otherwize be created to maintain the last value.
>
> Depending on your answer, we could track down which tool is wrong
> or if both are right.
>
> Rob
>
shall I post the complete VHD source?

Martin



Article: 57036
Subject: Re: Please help with clock signal
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 21 Jun 2003 14:20:16 +0200
Links: << >>  << T >>  << A >>

"Ed Stevens" <ed@stevens8436.fslife.co.uk> schrieb im Newsbeitrag
news:bcvuko$pal$1@newsg4.svr.pol.co.uk...
> Thanks for your reply.
>
> I've added the following to my code just after the architecture line:
>
>     attribute clock_buffer: string;
>     attribute clock_buffer of R_CLK: signal is "ibufg";
>     attribute clock_buffer of W_CLK: signal is "ibufg";
>
> The code Synthersises correctly and im able to map R_CLK and W_CLK to
> general purpose pins.  The trouble is the FPGA no longer recognises any
> signals that goto the general purpose pins of R_CLK and W_CLK.  I have two
> push buttons that I want to act as R_CLK and W_CLK, when they are
connected
> to the FPGA's dedicated clock pins everything works fine, when they are
> connected to the I/O pins using the above code nothing works.

You are SOOOOO close, missed the bullseye just by a hairwidth ;-))
You need to specify a "ibuf" !!!!, which is a normal input buffer.
A "ibufg" is a dedicaded clock input.
An beware of the lower case, those F**** attributes are case sensitive.
Looks like a bad property from Verilog which made its way into the VHDL
section of XST. :-((

--
Regards
Falk

P.S. But FORGET about using those push buttons directly as a clock. The will
bounce like hell. So use a (digital) debouncing circuit.




Article: 57037
Subject: Quartus / Leonardo frustration
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sat, 21 Jun 2003 15:48:54 GMT
Links: << >>  << T >>  << A >>
I really don't know how to continue. After solving the difference between
Leonard and Quartus about tri state assignements I continued on my design. A
few added lines and the fitter of Quartus crashes! The same design is
synthesizable with Leonard and P&R with Max+Plus or Quartus is ok.

Ok, I see this is a dilemma with free SW, but I would pay (some) money for
good SW. One option I got told from Mentor is to buy a one-year support
contract of  Leonardo for EUR 1.155,- (only till 06/30!). Not so cheap, but
they told me that Leonardo is a dead product, only bugs will be fixed, no
further development!
Mentors solution: A very special deal: Precision for EUR 6.875,- PLUS EUR
4.095,- for a one year support! And I was told I will save EUR 13.000,- with
this deal.
Sorry, but my projects will not pay for this SW cost.
Is there no solution between EUR 0,- and EUR 11.000,- for FPGA designs?

a little bit frustrated
Martin
--
--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/



Article: 57038
Subject: Interfaces in Handelc
From: "P. Prasad" <pprasad@chandra.cse.iitb.ac.in>
Date: Sat, 21 Jun 2003 21:31:00 +0530
Links: << >>  << T >>  << A >>
Hi,
  I am working on a HANDELC project on Xilinx FPGA(RC1000 board) and using Celoxica's DK1 environment. I have some doubts regarding HANDELC. I am new to HANDELC and FPGA.


The Problem
-----------

As the project is getting bigger and bigger, the compilation(synthesis into EDIF) time  is taking many hours. So the goal is to reduce the compilation time.

The approach which I tried to use was to break up the program into smaller parts, compile these into separate EDIFs and hook them into the main HANDELC program using interfaces(ports). So the parts of the program which have already been synthesized into EDIF do not take any time at all thus saving lot of time.

But I am doing some mistake in my code and I am clueless to what is wrong. Actually I feel that I need to synchronise the EDIF component with the main HANDELC program but don't know how ( maybe use interfaces properly???). I have given below the detailed description of the things I tried.


Here is the code for the main HANDELC program:(compiles to test.edf)
---------------------------------------------


#define PP1000_32BIT_RAMS
#define PP1000_DIVIDE4

#define PP1000_CLOCK	PP1000_MCLK

#include "C:\rc1000pp\fpga\virtex\pp1000.h"

set part = "V1000BG560-4";
set family = XilinxVirtex;

unsigned 8 value;

/* here interface to the component is defined */
interface test2
		(unsigned 8 ret_val)
	test2_instance
		(unsigned int 8 x = value);
void main (void)
{
	/****
	Interaction with the board is done .
	just reading some data from Memory banks which is written
	by a VC++ host program using RC1000 board API.
	Actually this data needs to be processed.
	To simplify the issue it's not given here.
	This is gauranteed to be correct, I tested it.
	****/

	value = 10; /* input to component EDIF */

	/* trying to use the EDIF component */
	while(test2_instance.ret_val == 0){delay;};
	value = test2_instance.ret_val;

	/****
	Interaction with board.
	just writing some processed data into memory bank.
	This part is gauranteed to be correct, I tested it. */
	****/
}

HANDELC code for the EDIF component (it compiles to test2.edf)
-----------------------------------

unsigned 8 value1;

interface port_in
		(unsigned int 8 x)
	comp_inp
		();

interface port_out
		()
	comp_outp
		(unsigned 8 ret_val = value1);


set clock = external; /* I am clueless here what clock to use */
void main(void)
{
	value1 = comp_inp.x * 10;
}


First I compile the above code to get test2.edf and then use the Xilinx place and route tool to merge both the edifs to get test.bit file.

But the above program does not work at all. Always I get value 0 when i read from the memory bank but the value is supposed to be 100. Also another suspicious thing is that the check for (ret_val==0) in the main HANDELC code surprisingly takes a long time (around 8 secs).

One more observation is that even if I explicitly write a value after the two statements as given below:

	/* trying to use the EDIF component */
	while(test2_instance.ret_val == 0){delay;};
	value = test2_instance.ret_val;

	value = 100; /* introduced now just to debug*/

	/****
	Interaction with board.
	just writing some processed data into memory bank.
	****/


still it gives 0. But if I remove the two statements trying to access the component, without removing the newly introduced statement,then the read value is 100 as required .


I don't know where I am going wrong. Any suggestions or help will greatly help me.

regards,

P.Prasad


Article: 57039
Subject: Re: PALs, GALs and ABEL
From: "Rick Haver" <rhaver@tampabay.rr.com>
Date: Sat, 21 Jun 2003 17:28:43 GMT
Links: << >>  << T >>  << A >>
I just did such a task. I converted an existing .JED from 22L10 into the
.JED required for a 22V10 by the pal2gal method. Also, I used the lattice
software which allowed me to make updates and create the new corresponding
.JED for the 22v10. Also, don't forget the capaility of retrieving the
source from just the old .JED file by the jed2abl utility.

Good Luck

"Paul Urbanus" <urbpublic@hotmail.com> wrote in message
news:3EF31484.8060904@hotmail.com...
> I have two old designs - from 1987 - that I wrote in ABEL (by Data I/O)
> that fit into a PAL20L8 and a PAL20L10. I want to program some new parts
> with these designs, but only have GAL20V8 and GAL22V10 parts available.
>
> According to a Lattice Semi data sheet, there parts are supposed to be
> fuse compatible with all of the parts they replace. So, in theory I
> should be able (pardon the pun) to use the PAL20L10 JEDEC file to
> program the GAL22V10 and the PAL20L8 JEDEC file to program the GAL20L8.
>
> Anyone have any experience in this matter who can say, "Yes, it will
> work, or, no way in Hades this will work?"
>
> On a related note, does anyone know if the old DOS version of ABEL is in
> the public domain? And if so, where I can download a new version.
>
> Of course, I could always recode the PALS in VHDL using the Cypress Warp
> software, which used to support the 22V10, at least.
>
> Thanx
>
>
> ______________________________________________________________________
> Posted Via Uncensored-News.Com - Still Only $9.95 -
http://www.uncensored-news.com
>       <><><><><><><>   The Worlds Uncensored News Source
<><><><><><><><>
>
>



Article: 57040
Subject: Re: Reducing synthesize time for state machines
From: atsai@signalogic.com (Albert Tsai)
Date: 21 Jun 2003 10:47:14 -0700
Links: << >>  << T >>  << A >>
The reason we had the smaller state machines advance state on the
opposite edge of the clock from the main machines is to prevent race
conditions.  For example, the smaller state machine could set the done
variable right when the main machine checks the done variable. The
main machine could stay forever in the checking state depending on
whether the main machine checks the done variable before or after it
is set.

Thanks,
-Albert

Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3EF36ECA.7080309@flukenetworks.com>...
> Albert Tsai wrote:
> 
> > I am currently using Xilinx's Webpack ISE 5.2.3 to work on a
> > dma_controller portion of a project.  When I synthesize the project,
> > the tool seems to take a long time synthesizing and optimizing the
> > dma_controller code.  The end result, is that the project takes 11
> > minutes to compile.  I am trying to look for ways to reduce this
> > compile time.
> > 
> > This dma contoller involves two main state machines that perform
> > handshakes with several smaller state machines in order to minimize
> > repetitive states.  The main state machines advance state on the
> > positive edge of the clock, while the smaller state machines advance
> > state on the clock's negative edge. 
> 
> Webpack probably wouldn't have to think
> so hard, if everything happened on
> the rising edge of the clock.
> 
>          -- Mike Treseler

Article: 57041
Subject: Re: Reducing synthesize time for state machines
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sat, 21 Jun 2003 19:32:10 GMT
Links: << >>  << T >>  << A >>
Hi - 

On 21 Jun 2003 10:47:14 -0700, atsai@signalogic.com (Albert Tsai)
wrote:

>The reason we had the smaller state machines advance state on the
>opposite edge of the clock from the main machines is to prevent race
>conditions.  For example, the smaller state machine could set the done
>variable right when the main machine checks the done variable. The
>main machine could stay forever in the checking state depending on
>whether the main machine checks the done variable before or after it
>is set.

If I correctly understand what you're doing--running a number of FSMs
from the same clock in the same FPGA-- using the falling edge to
change outputs  is unnecessary.  If an FSM asserts an output at the
start of cycle N, another FSM run from the same clock will not act on
that output until cycle N+1.  

Or are you doing something other than what I've described?

Bob Perlman 
Cambrian Design Works


Article: 57042
Subject: Re: Quartus / Leonardo frustration
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: Sat, 21 Jun 2003 19:57:08 GMT
Links: << >>  << T >>  << A >>
Hi Martin,

I would suggest filing a case with mysupport.altera.com detailing the
conditions under which your design crashes; without knowing the cause of
your crash, it is difficult to help you out.

As for your tristate issue, I've fired an email off to a colleague about it.
My past experiences with the new HDL compiler in Quartus is that every
"problem" I've found with it usually comes down to Quartus being correct
(according to the HDL spec). However, we sometimes need to loosen the tool's
interpretation in order to match that of 3rd party tools or when there are
ambiguities in the specs, and we don't find these cases out until a user
stumbles across them.

I wouldn’t call Quartus free software -- it is a heavily subsidized product
(free for some devices, nominal fee for others). We have 100's of software
engineers who work on Quartus to improve its stability, feature set, and
quality of results. High-quality HDL support is a relatively new feature in
Quartus, so it's conceivable that there are still bugs. Our goal is that
Quartus will provide you good-quality synthesis, but 3rd party tools still
offer value from a feature set, quality of results, and user interface
perspective.

Regards,
Paul Leventis
Altera Corp.

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:G7%Ia.48515$RM6.650504@news.chello.at...
> I really don't know how to continue. After solving the difference between
> Leonard and Quartus about tri state assignements I continued on my design.
A
> few added lines and the fitter of Quartus crashes! The same design is
> synthesizable with Leonard and P&R with Max+Plus or Quartus is ok.
>
> Ok, I see this is a dilemma with free SW, but I would pay (some) money for
> good SW. One option I got told from Mentor is to buy a one-year support
> contract of  Leonardo for EUR 1.155,- (only till 06/30!). Not so cheap,
but
> they told me that Leonardo is a dead product, only bugs will be fixed, no
> further development!
> Mentors solution: A very special deal: Precision for EUR 6.875,- PLUS EUR
> 4.095,- for a one year support! And I was told I will save EUR 13.000,-
with
> this deal.
> Sorry, but my projects will not pay for this SW cost.
> Is there no solution between EUR 0,- and EUR 11.000,- for FPGA designs?
>
> a little bit frustrated
> Martin
> --
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone: http://www.jopdesign.com/cyclone/
>
>



Article: 57043
Subject: Re: Please help with clock signal
From: "Ed Stevens" <ed@stevens8436.fslife.co.uk>
Date: Sat, 21 Jun 2003 14:41:47 -0700
Links: << >>  << T >>  << A >>
Great that works.  Thanks.

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:bd1ika$obfdg$1@ID-84877.news.dfncis.de...
>
> "Ed Stevens" <ed@stevens8436.fslife.co.uk> schrieb im Newsbeitrag
> news:bcvuko$pal$1@newsg4.svr.pol.co.uk...
> > Thanks for your reply.
> >
> > I've added the following to my code just after the architecture line:
> >
> >     attribute clock_buffer: string;
> >     attribute clock_buffer of R_CLK: signal is "ibufg";
> >     attribute clock_buffer of W_CLK: signal is "ibufg";
> >
> > The code Synthersises correctly and im able to map R_CLK and W_CLK to
> > general purpose pins.  The trouble is the FPGA no longer recognises any
> > signals that goto the general purpose pins of R_CLK and W_CLK.  I have
two
> > push buttons that I want to act as R_CLK and W_CLK, when they are
> connected
> > to the FPGA's dedicated clock pins everything works fine, when they are
> > connected to the I/O pins using the above code nothing works.
>
> You are SOOOOO close, missed the bullseye just by a hairwidth ;-))
> You need to specify a "ibuf" !!!!, which is a normal input buffer.
> A "ibufg" is a dedicaded clock input.
> An beware of the lower case, those F**** attributes are case sensitive.
> Looks like a bad property from Verilog which made its way into the VHDL
> section of XST. :-((
>
> --
> Regards
> Falk
>
> P.S. But FORGET about using those push buttons directly as a clock. The
will
> bounce like hell. So use a (digital) debouncing circuit.
>
>
>



Article: 57044
Subject: Convert rbt to bit
From: panjuhwa_fpga@yahoo.com (PanJuHwa)
Date: 21 Jun 2003 16:55:04 -0700
Links: << >>  << T >>  << A >>
Hi,

  how do we do that? Is it possible to code using Java?

  Thanks

Article: 57045
Subject: Re: Reducing synthesize time for state machines
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Sun, 22 Jun 2003 02:18:46 +0200
Links: << >>  << T >>  << A >>
Albert Tsai wrote:
> The reason we had the smaller state machines advance state on the
> opposite edge of the clock from the main machines is to prevent race
> conditions.  For example, the smaller state machine could set the done
> variable right when the main machine checks the done variable. The
> main machine could stay forever in the checking state depending on
> whether the main machine checks the done variable before or after it
> is set.
> 
> Thanks,
> -Albert

I think you should rethink how it works when the clock skew is less
than the delay of the logic as it is in an fpga when everything is on
the same global clock.

signals are evaluated on the edge, signals change after the edge, when 
everything sees the edge at the same time, and the max delay is less
than the clock period, theres no race.
using both rising and falling edge just give the signals half as much 
time to settle.

try drawing clock and signals on a piece of paper with the signals 
delayed a bit compared to the clock edge ....

-Lasse


Article: 57046
Subject: Re: Convert rbt to bit
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 22 Jun 2003 01:41:41 GMT
Links: << >>  << T >>  << A >>
On 21 Jun 2003 16:55:04 -0700, panjuhwa_fpga@yahoo.com (PanJuHwa) wrote:
>Hi,
>
>  how do we do that? Is it possible to code using Java?
>
>  Thanks

Why would you want to do this? The same program (bitgen) generates
both files. If you can get one, you can get the other.

Philip

Philip Freidin
Fliptronics

Article: 57047
Subject: What's the difference between ASIC and FPGA?
From: John K. <jonnykwtb@aol.com>
Date: Sun, 22 Jun 2003 12:23:02 +0100
Links: << >>  << T >>  << A >>

Hi,
sorry if this question has already been asked millions times. :P

What's the difference between ASIC and FPGA?

Thanks,
John

Article: 57048
Subject: "Ethernet only" network
From: visualfor@yahoo.com (Naveed)
Date: 22 Jun 2003 05:10:17 -0700
Links: << >>  << T >>  << A >>
Hello guys,

I have a multiple card system (56 cards), where I download a huge
amount of data (~500MB)  to each card from PC.  I have been using
parallel NI "DIO" bus to do that,  But it's slow and need very careful
termination to work.

I have been thinking about using cheap gigabit Ethernet solution.  I
have Altera's cyclone 1C6 on cards.  I can buy gigabit Ethernet
MAC+PHY for less than $15, then I can do rest of the processing inside
the FPGA.  The problem is that 1C6 is not big enough to implement the
TCP/IP stack inside (no external memory to store instruction).

So I thought, why use TCP/IP?  You can talk to just Ethernet to
Ethernet.  Has anybody ever implemented "Ethernet only" solution using
Windows?  How do sniffer guys do it by talking directly to NIC?

Just looking for big picture here.  Any help is appreciated.

Article: 57049
Subject: Difference between ASIC and FPGA
From: visualfor@yahoo.com (Naveed)
Date: 22 Jun 2003 05:14:06 -0700
Links: << >>  << T >>  << A >>
ASIC is not reprogrammable, while FPGA is.  ASIC cost a lot more to
build, but is cheaper in large quantity, and much more faster and
consume less power than FPGA.

Deep down, if you really think about it, FPGA is also an ASIC, but the
one that you can program!



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search