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Hi Ken Ok when i plug in the cable, windows reports a usb device is found, but because win doesn' know what it is, it fails. I have attached a screenshot (Sample.jpg, sorry about the attachment but I don't have web space to upload on a site). Now someone also mentioned to use Jongo WinDriver which I'm trying to use it. Firstly have u used this program your self. If you haven't used it then reject the next line. Secondly, this program allows you to generate a custom inf file (with product and vendor id), which I do but when it comes to installing the new custom driver, win2k doesn't like it and instead uses the c:\winnt\inf\usb.inf file. This sucks. Do you know what 'multi-interface device' means? Cheers Ken Regards "Kenneth Land" <kland1@neuralog1.com> wrote in message news:vnk7hr7qu9hgba@news.supernews.com... > >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61251
Hey, Sorry, my cheapy supernews account doesn't support attachments or .jpgs. (text only) The Jongo stuff sounds cool if it would work. I'm not going to be able to rebuild our driver for awhile. I'll have to find the machine at work that has the DDK installed. (My machine doesn't) Interestingly our vendor/device id's don't exist in the driver source, only the driver name. Is Jongo free? Sounds interesting. I was wondering why there isn't a generice bulk interface driver in Windows that you could use to talk to any USB device. I'm wondering if its not possible. If our vendor/device id's are only in our .inf file then that would mean anyone could map their device to use an existing driver just by editting the .inf file. As you may guess, I wasn't the guy who originally built our sample Netchip driver many years ago. (I was the guy who got the registered ID's in the first place) I know it was easy and it works great. I'll update you if I make any more progress. Ken "SneakerNet" <nospam@nospam.org> wrote in message news:gMpeb.164200$JA5.4050596@news.xtra.co.nz... > Hi Ken >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61252
Marketing is full of engineers who couldn't design their way out of a paper bag. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F79060D.1FF4C408@yahoo.com... > Here is a perfect example of what is wrong with Marketing in engineering > companies. I recently asked Xilinx for a "Spartan-3 Resource CD". It > has been a couple of weeks since I requested it, so I don't remember if > I expected it to contain something especially useful (like a copy of > Webpack) or if I thought it would contain only data sheets. In any > event, it came today. It does not contain Webpack. It only uses less > than 100 MB of the available 650 MB to provide a few data sheets, app > notes and the Acrobat reader. What's more, when it autostarted on > loading the CD, it opened a window for Flash player. But this Flash > player does not seem to work correctly and I can't use it to view > anything past the second level of menu. > > I can read any of the data sheets on the CD without the viewer. But > what is the point of spending a lot of time on this silly viewer only to > have it not work on an otherwise functional machine? Also, what is the > point of sending out this sort of marketing drivel for free and yet > charging to send out "free" software which is much harder to download > intact from the web site? I can download data sheets and app notes > easily even over my slow modem connection. IIRC, the Webpack is about > 180 MB for the newest release. Why does this necessitate a charge to > get a copy on CD when CDs are clearly considered a minor expense? In > volumes of 1000's CDs only cost around a dollar to make and mail > including US postage. > > In general, I find marketing at most companies to work against their > best interests. But then they do make for good copy in the Dilbert > column. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61253
Hi Ken The Jongo windriver is free for 30 days, but a quick hunt on www.astalavista.box.sk found the never ending patch. I can send you the program + patch if u'r interested. Let me Know.. The program does sound very cool, excpect I can't get it to work *sniff*. You are right about the ID's. I suspect the .sys and .dll files prob have the ID's as well in it. Then again I'm no guru at windows driver.. aaargghh .. why does this have to be so unfriendly.. any more help pls pls drop in a line Regards "Kenneth Land" <kland1@neuralog1.com> wrote in message news:vnkc07hhvlfu53@news.supernews.com... > Hey, >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61254
> Marketing is full of engineers who couldn't design their way out of a paper > bag. Ever seen three design engineers standing around, trying to figure out how to work a Xerox machine?Article: 61255
Paul - Thanks much. I followed your directions and turned off the Norton boxes. Robert "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:AJ5eb.161395$Lnr1.60086@news01.bloor.is.net.cable.rogers.com... > Robert, > > I just got back from a week long trip, and my computer is STILL crunching > away -- there is a good reason I don't use my Altera email address here. > Ever some kids in a class I TAed decided to post my email to a couple of > porn mailing lists, this email address has been "dirty" if you excuse the > pun :-) > > You can stop AntiVirus from notifying you for every email virus. Do the > following: > > (1) Double click your AntiVirus icon in the system tray > (2) Click "Options" > (3) Under the Internet tab, click on "EMail" > (4) Click the "Repair then silently delete if unsuccessful". Bye-bye > irritating message. > > I'd also suggest disabling "Display tray icon" and "Dispaly progress > indicator when sending email" as these two things are slow, and seem to chew > up system resources. > > As for filtering your spam, there are many options floating around, most of > which have been covered by previous posters. > > Good luck, > > Paul Leventis > Altera Corp. >Article: 61256
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:bl3jrf$g63$1$8302bc10@news.demon.co.uk... > Ekalavya Nishada wrote: > > Greetings, > > > > I am new to hardware design and hoping to get a reality check on > > building a lexical analyzer and parser using FPGAs. > > Jan Gray, begetter of the excellent but more or less defunct > fpgacpu.org site, has discussed this. Search in Google. Thanks Tim. Say not defunct -- think of it as on extended hiatus. (Hint: try googling jan gray msdn). Anyway, Ekalavya, if you visit fpgacpu.org and type 'parsing' into the Search box you'll find a few entries that may be of interest. Jan Gray, Gray Research LLC FPGA CPU "News": www.fpgacpu.orgArticle: 61257
Hi Ray - Yup, the "failed delivery" messages have been about 50% of this recent MS barrage. I hope the perps of these viruses are at least making money from their efforts (identity theft, etc.). That would redeem them on some level in my mind, but it's probably just a bunch of pimply 15-year-olds doing it for kicks. As for spam, I don't get the business concept at all. How many penis enlargement pills have actually been sold from email ads? The complete idiocy of the concept has kept me waiting for the volume to decrease, but it just keeps getting worse. California just passed an "anti-spam" law. We'll see what difference it makes. Robert "Ray Andraka" <ray@andraka.com> wrote in message news:3F788635.431A955@andraka.com... > 300-400/day isn't that bad. I've been getting that in under 2 hours. > My ISP has been next to useless on resolving it. I did change to the > latest paid version of Eudora, which has a spam filter built in. That > has done a pretty good job of culling out the junk. I also had to set > the virus sw to automatically delete virus files rather than prompt me > to do away with the annoying dialog boxes that were popping up every > couple of seconds. It is still not an ideal solution, as I can't go > off-line without having the mailbox at the ISP overflow within a few > hours, and I still have to cull the junk mail box to recover the > occasional false positive. It has cut down the time involved > however. In my case it has been two major sources this month: the > microsoft patch virus, and viruses embedded in "failed delivery" > "returned" emails. > > I too am a consultant, and I depend on having my email address in the > clear to get the traffic into me. This whole spam thing is an > irritant that was not at the debilitating level until this summer. >Article: 61258
James, I reinstalled the whole thing with the same result.... I am starting to suspect the installation file. When you installed it, did you use Xilinx web installer or did you first download the big file? I first tried to use their web installer but it failed 2 times, so I downloaded the big (188MB) file and ran it locally... Java thing aside I don't seem to have any pdf files installed whatsoever. Can you please confirm that you have %Xinlinx%\doc\usenglish\manuals.pdf ? My doc\usenglish has no files in it.... /Mikhail "James Williams" <james@williams-eng.com> wrote in message news:blc3ne$82b3$1@news3.infoave.net... > I got the VM from sun. My pdf's will open without a problem. > > Go to sun and look for the Virtual machine plugin for IE or Netscape. > > Regards, > > James > > > "MM" <mbmsv@yahoo.com> wrote in message > news:blc2q3$ajice$1@ID-204311.news.uni-berlin.de... > > "James Williams" <james@williams-eng.com> wrote in message > > news:blc1lo$81o9$1@news3.infoave.net... > > > You also need the Sun virtual machine plugin for your web browser. > > > > > > I had this exact problem when I installed 6.1 and I also had the Runtime > > > environment, however I had to also download and install the virtual > > machine > > > plugin for my web browser before the help would work. > > > > I believe I do have the plugin, but it still doesn't work... Maybe I have > a > > wrong plugin?.. Do you remember where you got it from? And what about the > > pdf part and the tutorials? Do you have them working? > > > > Thanks, > > /Mikhail > > > > > >Article: 61259
SneakerNet wrote: > Hi Ken > > Thanks for the important tip. I'll give that a shot. (so there is no way u > can send me driver? all i need is a driver with vendor id = 0c91 and > product id = 2001). > Anyway like u mentioned, very big pity that the guys didn't include > drivers and they gave their whole vhdl code free. Pity! > > Hope god has mercy on my soul while i'm doing usb driver.. LOL > Thanks Ken > Kind Regards [snip] You might look for a book by the title (I think) "UBS made easy" or something like that. My copy must be packed away. It had a lot of info on Windows drivers and included several VB examples on the CD. If I can find the book I'll post the ISBN but I remember I got it from Amazon. -- Joe Chisolm - ArizonaArticle: 61260
Hello, I'd like to know if anyone has interfaced a NS Channel Link TX to a Virtex-II FPGA and wouldn't mind sharing their experience. Or, if anyone has any thoughts on this problem. What follows are some details about this situation. There is much I could have added, but to prevent this from being too long, the details are not complete. I hope it's enough to convey the setup and observations. I'm trying to interface a Xilinx XC2V8000 to a National Semiconductor DS90CR483 using a 12" cable. The parallel data rate is about 68 MHz. The connector and cable are the same as those used on the National Semi's LVDS eval kit. I created an LVDS receiver design in the FPGA to receive the serialized data. I've studied the Xilinx appnotes and verified placement of the LVDS elements in the FPGA, e.g, the DDR registers in the IOBs are used. The phase shift is close, but not quite where I have predicted, following the NS datasheet and considering the small, if any, internal FPGA skew between the clock path and data paths to the DDR registers. The "error" is "measured" by observing the parallel data output from the LVDS receiver modules. The phase shift was empirically adjusted to center the clock in the middle of the "no error zone." The "no error zone" can actually have errors sometimes (more on this in the next paragraph). At 60 MHz, the errors are fewer. When the cable is longer, e.g. 3-4 ft, the errors are fewer. Also, some links seem to have more errors than others. (Changing cables does not appear to affect this much.) Resetting the FPGA DCM does not correlate well to the errors. Powering up/down the system does seem to affect the errors. The errors include times when no clock is output from the DCM. Thank you for any thoughts, MarkArticle: 61262
Marc Guardiani escribió: > > Javier, > > Do you use NT? Xilinx dropped NT support with ISE version 5.1i, but it Sorry I forgot to mention: we use Windows XP > still ran. With 6.1i Impact won't even start up. Neither will the Core > Generator. YMMV. > > Marc > Thanks for the info. Our iMPACT does start, and from the log messages, it seems it confuses LPT1=0378 with LPT1=0B78. I have tried to look for "edit options" to change that, but can't find anything either in the menus or in the PDF handbook. In any case... why does 6.1 uses 0B78 instead of the previous 0378? Confused... :-) -javierArticle: 61263
I'm trying to infer a 8x8 bit dual port distributed RAM in VirtexII
device, using XST.
My code looks similarly to the one from XST manual:
type RAM_TYPE is array(7 downto 0) of std_logic_vector(7 downto 0);
signal RAM : RAM_TYPE;
signal A: std_logic_vector(2 downto 0);
signal DPRA: std_logic_vector(2 downto 0);
.
.
.
RAM_INFER: process (clk)
begin
if (clk'event and clk = '1') then
if (RDBYTECNT_EN = '1') then
RAM(conv_integer(RDBYTE_CNT)) <= W1_DIN;
end if;
end if;
end process;
-- two 8-bit output ports are merged into 16-bit vector
RAM_OUT <= (RAM(conv_integer(DPRA))) & (RAM(conv_integer(A)));
Now I have two problems with above:
1) Every time (I think) modelsim executes function conv_integer()
it gives warnings like that:
There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result
will be 'X'(es).
CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, and it has been converted to 0.
conv_integer() function comes from ieee.std_logic_unsigned pakcage.
I tried also using different packege, i.e. ieee.numeric_std, then it
looks like that:
RAM(to_integer(unsigned(A)))
and Modelsim outputs
NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
Am I doing something wrong? Aside from the warnings, simulation results
seem to be OK.
2)The synthesis report says:
Found 8x8-bit dual-port distributed RAM for signal <ram>.
-----------------------------------------------------------------------
| aspect ratio | 8-word x 8-bit |
| clock | connected to signal <clk> | rise
| write enable | connected to signal <rdbytecnt_en> | high
| address | connected to signal <rdbyte_cnt> |
| dual address | connected to signal <dpra> |
| data in | connected to signal <w1_din> |
| data out | not connected |
| dual data out | connected to internal node |
| ram_style | Distributed |
-----------------------------------------------------------------------
INFO:Xst:1442 - The RAM contents appears to be read asynchronousely. A
synchronous read would allow you to take advantage of available block
RAM resources, for optimized device usage and improved timings. Please
refer to your documentation for coding guidelines.
Found 8x8-bit dual-port distributed RAM for signal <ram>.
-----------------------------------------------------------------------
| aspect ratio | 8-word x 8-bit |
| clock | connected to signal <clk> | rise
| write enable | connected to signal <rdbytecnt_en> | high
| address | connected to signal <rdbyte_cnt> |
| dual address | connected to signal <a> |
| data in | connected to signal <w1_din> |
| data out | not connected |
| dual data out | connected to internal node |
| ram_style | Distributed |
-----------------------------------------------------------------------
INFO:Xst:1442 - The RAM contents appears to be read asynchronousely. A
synchronous read would allow you to take advantage of available block
RAM resources, for optimized device usage and improved timings. Please
refer to your documentation for coding guidelines.
Does it mean that synthesizer infered two RAMs instead of one? Is this OK?
I'm using ISE5.2 with service pack 3.
--
Robert Pudlik
Article: 61264
Hi,
I've also got a little problem with implemeting a bidirectional port on =
a Spartan2.
When I use the following code:
process (ClkInt, ClkDir)
begin =20
if ClkDir =3D '0' then
SIGT <=3D 'Z';
ClkRxTX <=3D SIGT;
else
SIGT <=3D ClkInt;
ClkRxTX <=3D ClkInt;=20
end if;
end process ClkSwitch ;
My SIGT port becomes an output. only when I remove the lines SIGT <=3D =
ClkInt; and SIGT <=3D 'Z'; the SIGT port becomes an input. I just can't =
seem to get the port to become an inout (or Bidir).
My synthesis tool (leonardo spectrum) reports that the port is an inout. =
But after running the Xilinx map tool the port is already an ouput. I =
don't see anything in the reports about these ports.=20
One strange thing: When I make three testports on my toplevel, and =
create a process like the one above, there's no problem. The port is =
bidir as it should be. Anybody got any ideas on what this problem might =
be ??
Note: The sigt port is combined into a std_logic_vector with 7 other =
SIGT signales. The signals are declared as inout in the whole design.
Article: 61265
>Then why do DRAM memory systems include a CRC or parity bit?
>Certainly there is some non-zero probability that a latch will miss or
>a gate will experience a random noise spike?
>
>If what you say is true, the BER of a disk drive will be entirely the
>fault of a noisy head, and not the deserializer, cache or bus drivers?
Here is how I look at this area...
There are two types of electronics: logic and communications.
Logic includes computers. Everybody expects them to work correctly.
Communications includes things like Ethernet, fibers, and satellite
links. People (including engineers) expect a few errors.
The error rate you actually get on a communications link is determined
by the signal to noise ratio. That assumes classic gausian noise. See
any good communications text book. The key here is "gausian", which
is pretty good for fibers and satellite links.
On most communication links, there is an economic tradeoff. How
many miles can you go on a fiber before you get too many errors?
How many bits/second can you get on a satellite link before you get
too many errors?
Disks are similar to communications links. How many bits per square
inch can I get vs what is the error rate when reading them back?
On the other hand, people expect logic (and/or computers) to get the
right answer - zero errors. All that means is that they are running
with a signal/noise ratio that is very very very good relative to
communications links.
If you look at the classic errors vs signal/noise chart, you will see
that it's exponential. Make the signal stronger and the errors go
way down. Make it still stronger and you can't mesure them.
Classic logic (gates and FFs) operate in a signal/noise range that
is so far off scale that they don't make enough errors to worry about.
You need to worry about other sources of errors instead - things
like meteorites landing in your lab and smashing your FPGA but
missing your error testing gear.
If you look at errors on logic/computers, you can lump them into
several buckets.
Design/software errors
For example, Intel's divide bug
Fabrication errors from the factory.
broken chips, inadequate testing, assembly errors, ...
Systematic errors that are similar to noise. These are things
we can localize and analyse, but often overlook:
Clock jitter (see Austin's msg)
crosstalk
noise on power rails
Alpha particles, Cosmic rays...
Signal Ingegrety, reflections
(see the recent Spartan3 discussions)
...
These are the hardware versions of the software bugs above.
Thermal noise:
This is what's left after you correct for all of the above.
If something strange happens often enough, somebody will figure
out what's going on and put a name on it and it will get added
to the list above.
DRAMs are interesting. They are on the border between communications
and logic. We want them to work all the time, but we also want them
to be cheap. Cheap means small which means they are more likely to
drop bits if an alpha particle hits the right place.
(When people were first starting to get interested in alpha particles,
they were black magic or "thermal" noise. As soon as people understood
what was going on then they could measure and avoid the problem.)
If you want cheap DRAMs, you will get occasional errors. (You can't
buy any other kind, so get used to it.) With ECC and good software
(scrubbing) you can get close to error free DRAMs. Similarly, with
good FEC (Forward Error Correcting) you can get close to no errors
on satellite links.
Back to FPGAs. Roughly, they don't make any errors. What I mean
by that is that the gates and FFs work as expected. I expect there
is some thermal noise, but I doubt if you can measure it. There are
too many other things causing more intersting problems.
If your question was really how many errors to expect on a
simple input-FPGA/BRAM-output type design, my answer would be
"it depends". How solid is your design? Any metastability
involved? What sort of external noise/EMI? What are your input
output lines connected to? Is the clock solid? When you get done
with all those questions, then you get to ask about alpha particles
and cosmic rays.
It's really really hard to prove that your design is solid.
The software/systems guys have a neat phrase. Testing can't
prove the absence of bugs. It can only demonstrate their
existence.
The software guys have a set of tricks that make looking for bugs
more productive. Similarly, with hardware, it helps to look in
the places that are likely to cause errors. Put a scope on your
clocks. Check your power. Look at the places where signals cross
clock domains. ...
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 61266OK, I found answer to problem 1). At the start of simulation some signals were not initialized. Also in the test bench I was assigning 'Z' to adrress input (this RAM is part of a bigger design, and Address bus is bidirectional). The result was as I described - I could read/write proper values from/to the RAM. I still don't have answer to question 2). -- Robert PudlikArticle: 61267
Dear Mr Leventis,
thank you for your answer.
The problem of the QuartusII-Software-Compiler seems to be
the recognition of RAM-structures.
The following source code is synthesized using memory bits
when the signal writing is not used.
When the signal writing is used then QuartusII tries to synthesize
it without any memory bits.
Where could be the problem in the use of the signal writing?
Kind regards
Andrés
G&D System Development - FPGA design
-------------------------------------------------
-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_ram_package IS
CONSTANT ram_width : INTEGER := 8;
CONSTANT ram_depth : INTEGER := 2048;
TYPE word IS ARRAY(0 to ram_width - 1) of std_logic;
TYPE ram IS ARRAY(0 to ram_depth - 1) of word;
SUBTYPE address_vector IS INTEGER RANGE 0 to ram_depth - 1;
CONSTANT xram_width : INTEGER := 12;
CONSTANT xram_depth : INTEGER := 16;
TYPE xword IS ARRAY(0 to xram_width - 1) of std_logic;
TYPE xram IS ARRAY(0 to xram_depth - 1) of address_vector;
SUBTYPE xaddress_vector IS INTEGER RANGE 0 to xram_depth - 1;
END test_ram_package;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.test_ram_package.ALL;
ENTITY test_inferred_ram IS
PORT
( --reset : IN std_logic;
clock1 : IN std_logic;
clock2 : IN std_logic;
data : IN word;
write_address: IN address_vector;
read_address: IN xaddress_vector;
write_xaddress : IN xaddress_vector;
xdata : IN address_vector;
we : IN std_logic;
q : OUT word
);
END test_inferred_ram;
ARCHITECTURE rtl OF test_inferred_ram IS
SIGNAL ram_block : RAM;
SIGNAL xram_block : XRAM;
SIGNAL read_address_reg : xaddress_vector;
SIGNAL writing : std_logic;
BEGIN
PROCESS (clock1)
BEGIN
--IF reset='1' then
-- ram_block <= (others => (others=>'0'));
-- xram_block <= (others=>0);
-- writing <= '0';
IF (clock1'event AND clock1 = '1') THEN
IF (we = '1' and writing='0') THEN
ram_block(write_address) <= data;
xram_block(write_xaddress) <= xdata;
writing <= '1';
ELSIF (we='1' and writing='1') then
ram_block(write_address) <= data;
xram_block(write_xaddress) <= xdata;
writing <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clock2)
BEGIN
IF (clock2'event AND clock2 = '1') THEN
q <= ram_block(xram_block(read_address_reg));
read_address_reg <= read_address;
END IF;
END PROCESS;
END rtl;
Article: 61268I believe that it treats the port as a bit bashed parallel port and as such requires it to look exactly like a parallel port. so unless the USB <> parallel port has the same registers, it won't work. But this is just a belief. I would suggest you waste a PCI port.. but make sure that the parallel port card you buy can be returned if it doesn't work. Not all parallel ports are created equal. Simon "H. Peter Anvin" <hpa@zytor.com> wrote in message news:blakq0$nm$1@cesium.transmeta.com... > Hi all, > > Does anyone know if Altera Quartus II (3.0+) will let me use a > parallel port to USB adapter? I just got a new machine, in part so I > could upgrade to 3.0 from 2.2 (and in part so everything would go > faster), but it doesn't have a parallel port! I basically have three > options: waste the only PCI slot in the machine for a parallel port > card, use a USB adapter, or special-order a manufacturer-special > parallel port interface for the machine with unknown lead time. > > The question is basically: does Quartus II rely on it being a serial > port interface with the traditional I/O ports, or does it handle > anything that can drive a printer? > > Shelling out $300 for the yet-not-in-existence USB-Blaster cable is > not realistic, nor is $500 for MasterBlaster which doesn't even handle > the active serial configuration devices. > > -hpa > > -- > <hpa@transmeta.com> at work, <hpa@zytor.com> in private! > If you send me mail in HTML format I will assume it's spam. > "Unix gives you enough rope to shoot yourself in the foot." > Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 61269
Hello, Could anybody suggest, where to buy Cyclone devices by Altera in Europe for normal price? (for ex., EP1C3T144Cx) I need just 1-2 pieces for testing.. Tryed at Arrow: $50 handling fee they added for international orders (plus $50 for delivering, so $125 for a peace-?....). No any branch of Altera distributors or resellers in my country...:( Any Online catalogs, which has it (like Farnell, RS-Components, Elfa, Digikey) ? /Vakaras/Article: 61270
Hi Nicolas, Nicolas Hervé wrote: > Is there a human readable file of Xpower analysis (something in *txt format) > I only have seen the *.ncd file. Are you looking for a file that reports the results of XPower analysis ? If so, then within the XPower GUI you can select to view a text report file. (On Windows you can also choose to view a HTML report file.) You make this selection (text or html) in the explorer view. The explorer view by default is placed between the summary view and History bar on the left hand side. This view shows the design elements separated into views and also provides a way to show the Text or HTML Report view. There are two top level views, (represented by folder icons, ala Windows Explorer) Data Views, and Report Views. "Report Views" contains the report views. Note that there is no choice on Solaris or Linux. Your only option on Solaris or Linux is text. You can also choose to generate a text report file through the batch application's command line. BrendanArticle: 61271
Hi Aman, Aman Gayasen wrote: > Hi, > I have some questions about XPower. > > 1)Can we get a time-based "detailed" report using XPower? I would like > to know the power consumed by each logic block at different instances > of time. Is it possible? (using XPower or otherwise) The -tb switch in > XPower only reports the total power consumed by the entire FPGA at > different time instances. > > 2)XPower normally reports the average power consumed by different > components of the FPGA over the entire simulation time. Is it possible > to get the maximum power, instead of average power. As you know, time-based simulation file analysis can be performed any time a VCD file is loaded. (For those not familiar with this XPower feature, the time-based analysis will be performed if the file is being loaded from the command line and the -tb switch is used, or if it is being loaded in the Gui and the "Do Time based Simulation" box is selected. This will read in the VCD file and for every time indication it will record the number of transitions between this and the last and calculate how much power has be generated for that time period.) However, the time-based analysis also records the highest value, and this will be displayed as "Peak Power" in the Summary view and in the text (and html for Windows) report. It always writes out a text file recording the power for each time period. This file can be read into Excel or other graph making utility to produce a graph of power over time. Further to your "PS", I think this newsgroup is a good place to ask such questions. Hope this helps, Brendan > > > Any help will be highly appreciated. > > Thanks, > Aman > PS: BTW, Is there another place to ask these tool-specific questions? > My questions seem to be too Xilinx-specific; please let me know if > Xilinx provides any such user group which might be a better place to > ask such questions.Article: 61272
Yes, but there are a few reasons for that (Xerox machine, not paper bag): 1. We could learn how to use it, but we'd rather spend our time on more interesting stuff (the old Farside cartoon where the kid puts his hand up in class and says "Excuse me, sir, but my brain is full"). 2. We read Users Manuals as a last resort. If the user interace is designed well, we shouldn't need one. If it isn't designed well, it pisses us off and we don't want to use the thing :-) 3. If we figured it out, everyone else would expect us to help them with it :-) How tired are you of telling friends you work in computers and they immediately expect you to fix their problems with Word on their PC for them. 4. When we do decide to figure it out, we want to really understand how it works, not just how to push the buttons, and we don't have time for that. By the way, how many engineers do you know who do not have the clocks set on their VCR? Not many I bet ... As for marketing being full of engineers who couldn't design their way out of a paper bag, the key is whether they realize they couldn't design their way out of a paper bag or not ... ------------ Ron Huizen BittWare "Vinh Pham" <a@a.a> wrote in message news:R_qeb.18681$Ak3.11446@twister.socal.rr.com... > > Marketing is full of engineers who couldn't design their way out of a > paper > > bag. > > Ever seen three design engineers standing around, trying to figure out how > to work a Xerox machine? > >Article: 61273
Hi all, Sorry to ask about analog question, but it 's relative to FPGA too. Do you know a schematic to do 'Automatic I/O voltage sensing' as XILINX does with the ParallelCable IV. I am designing a new JTAG interface (USB), and I want to be able to drive correctly the target JTAG signals (3.3V, 2.5V, 1.8V, 1.2V). Are there any lvttl level shifter device to do this work? Thanks for your advice. Laurent Gauch www.amontec.comArticle: 61274
mikroprog@yahoo.com (Vakaras) writes: > Could anybody suggest, where to buy Cyclone devices by Altera in > Europe for normal price? (for ex., EP1C3T144Cx) I got mine from EBV (www.ebv.com). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
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