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Messages from 66025

Article: 66025
(removed)


Article: 66026
Subject: Re: NAND flash interface?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 14:55:16 -0500
Links: << >>  << T >>  << A >>
guille wrote:
> 
> Hello there,
> 
> Has anyone implemented a NAND interface in a PLD? I don't mean a
> 'smart' NAND controller, just an interface that lets you toggle ALE,
> CLE, CE externally and do read/write accesses to the NAND ports.
> 
> Thanks,
> Guillermo Rodriguez

I'm not sure what you are looking for.  If you control the ALE, etc,
then you are talking directly to the NAND part and don't need a
controller.  Or are you asking how to generate ALE, CLE and the other
inputs that are not typical MCU controls?  The timing for these control
inputs are the same as for what would be the address inputs on a NOR
flash part.  So I just tie them to address lines.  The MCU then writes a
command word by writing to an address that raises CLE and lowers ALE. 
It writes the address register by writing the data address to the
address that lowers the CLE signal and raises the ALE signal.  

I don't think you need a PLD for this unless you use it to decode the
address to generate the CE signal.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66027
Subject: Re: JAM and Xilinx/Altera CPLDs
From: Ville Voipio <vvoipio@kosh.hut.fi>
Date: 11 Feb 2004 21:56:23 +0200
Links: << >>  << T >>  << A >>
sdatta@altera.com (Subroto Datta) writes:

> Both the free Web Edition and the Quartus II Full subscription have
> the same capabilities for both programming and for
> generating/converting programming files.

Thank you very much! Very good. (Still, I'd like to suggest that
the differences between the Web edition and The Real Thing were stated
very clearly on the web page.)

BTW, do Altera have any plans of making Linux-compatible
programmin sw? At least in our case we'd like to keep
Windoze far away from the production line.

- Ville

-- 
Ville Voipio, Dr.Tech., M.Sc. (EE)

Article: 66028
Subject: Re: negative hold time
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 15:05:24 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Besides some meaningless semantic quibbling, Rudi's answer indicated
> basic conceptual differences.
> A component data sheet should have a component-centric view: The
> flip-flop has a window in time during which the D-input must be stable,
> to guarantee predictable operation. This window has an early edge
> (commonly called set-up time, often specified as a min, but I would call
> it a max), and it has a late edge (commonly called positive hold time
> when it is later than the clock edge, negative hold time when it is
> before the clock edge. I would like to call it the min set-up time, but
> it's too late to bring sanity to this issue).
> 
> Whether something is a min or a max depends on your perspective.
> With a bridge over a highway, the  "14 feet" specification is a min for
> the bridge builder, but a max for the truck driver...
> 
> Much of this is semantics, but semantics can interfere with
> understanding, sometimes.
> Peter Alfke

I don't know if any further comment is warrented or valuable, but I am
waiting for a download and thought I would post my 2 cents worth.  

I agree that the data sheet should be "component" centric.  But this is
normally done in terms of the interface.  The internal sampling of the
data input is what is going on, but that is not relevant given occam's
razor.  All the user needs to know is to maintain the data input stable
during a timing window.  Using one set of terms vs. the other does not
make the mechanics more clear in my point of view.  

I agree that the basis of this timing window is not clearly understood
by many engineers.  The way to improve the understanding is to have the
data sheets (or app notes) clearly explain the basis for the window (and
how it is measured) rather than just leaving it up to the engineer to
try to figure out what the data sheet writer is trying to spec.  I often
have trouble figuring out just what a spec is trying to say.  Perhaps a
JEDEC, EIA or other standards body could help by defining measurement
terms, what they are measuring and how they are measured?  

I especially find it interesting (not in a good way) when the spec I am
looking for is not in a data sheet, but instead a similar one is given
in its place.  For example, when I am looking for max static current
draw over temperature and I am given a typical current at 25C.  What is
the designer trying to tell me?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66029
(removed)


Article: 66030
Subject: Re: FIR filter coefficient (with COE file)
From: ccon <>
Date: Wed, 11 Feb 2004 12:24:40 -0800
Links: << >>  << T >>  << A >>
scale your numbers to integer, the coef width depends on the 
resolution(decimal points)you wish.



Article: 66031
Subject: Xilinx Platform Flash Prom
From: Petrov_101@hotmail.com (Pete)
Date: 11 Feb 2004 12:25:30 -0800
Links: << >>  << T >>  << A >>
This may be an odd question but here goes... 

  I would like to use the JTAG chain to program Xilinx's Virtex-II
fpga and the Platform Flash ISP Configuration PROM.  OK, that's not a
problem as it's detailed in document DS123 (v2.2).  However, I would
like to add a second Platform Flash PROM in the same chain as the
Virtex-II and it's config PROM.  This second PROM would be used to
hold general purpose data (ie. not FPGA config data).  I would like to
connect this PROM to unused I/O of the FPGA which would then reset the
PROM and pull data out of it serially to be used in other parts of the
product we're developing.

Each "box" we're designing will have analog control bits that need to
be tweaked when the unit is sealed up.  The only access I have to the
PROM is through the JTAG interface.  I was wondering if anyone has
seen any app notes detailing this sort of interface/design.

Pete

Article: 66032
Subject: Re: Pricing, 101
From: steve41@totalise.co.uk (Steve)
Date: 11 Feb 2004 12:36:15 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in message news:<4029259F.1BC8DDF6@xilinx.com>...
> This is really simple, Capitalism 101:
> 
> Manufacturer invents and makes part. 
> Uses seval competing distributors to sell the part to the public.
> Manufacturer optimizes his profit by charging distributor a certain
> price, and also publishes a pricebook with "Manufacturer Recommended
> Resale Price" MSRP. 
> Distributor can sell in any quantity and for any price he wants, high or
> low, but he will try to optimize his profit. 
> Customer will buy at the lowest possible price consistent with the
> desired level of service and support.
> This is true for food, shirts, cars, and ICs. For Tiffany's, Nordstrom,
> Safeway and CostCo.


This is really simple; Oligopoly 101:

Oligopolists value high order quantities highly and small order
quantities as not being worth the hassle.
Oligopolists watch competitors and are happy if all oligopolists in
the market view small order quantities as not being worth the hassle.
Certain oligopolists have a high vested interest in having smooth and
monotonic price vs size curves, which can be maintained by having few
distributors, and *possibly* a say on the prices they charge to
buyers, and *possibly* exert pressure on distributors to toe the line.
Oligopolists are happy. 
Those wanting to buy small order quantities are screwed.


> But rest assured that we are seriously looking at ways to improve the
> plight of the low-volume customer. Some of your complaints did not fall
> on deaf ears. 


I'll quote the British phrase "the proof of the pudding is in the
eating", or in other words I'll believe that when small quantity
prices come down...


--
Steve

Article: 66033
Subject: Re: JAM and Xilinx/Altera CPLDs
From: rkruger@altera.com (Rob Kruger)
Date: 11 Feb 2004 12:46:20 -0800
Links: << >>  << T >>  << A >>
Ville Voipio <vvoipio@kosh.hut.fi> wrote in message news:<i3k65ednatp.fsf@kosh.hut.fi>...
> armcc@lycos.com (Andre) writes:
> 
> > Are you sure that the free version of Quartus will output .jam files
> > ??
> 
> No, I am not sure. I did not even come to think of an alternative that
> evil. By looking at the Altera site they do not mention anything about
> this. This feature is not on the list of "if you pay more, you'll
> get these", but that does not necessarily mean anything.
> 
> > I thought you had to pay for the full version to anything other
> > than program directly from the IDE ??
> 
> Possible. Let's see... Anyway, if this is the case, the CPLD on our
> next design does not start with an "A".  Not giving out the software
> for free is one thing. Not telling the extent of the lobotomy of
> the "free" version is another.
> 
> - Ville

The free Quartus II Web Edition software does output .jam files. You
enable this by selecting Assignments -> Device -> Device and pin
options -> programming files tab.

The following page lists the general features of Quartus II Web
Edition software and what additional features customers get by
purchasing a software subscription:
http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html

Rob Kruger
Altera

Article: 66034
Subject: Spartan-3 shipping, or perhaps not!
From: Leon Heller <aqzf13@dsl.pipex.com>
Date: Wed, 11 Feb 2004 21:21:53 +0000
Links: << >>  << T >>  << A >>
According to the Xilinx home page two of the Spartan-3 family are in 
production and shipping. However, when the link is followed, one is 
taken to an old press release which says that four family members are 
shipping! Which is correct?

Leon
-- 
Leon Heller, G1HSM
Email: aqzf13@dsl.pipex.com
My low-cost Philips LPC210x ARM development system:
http://www.geocities.com/leon_heller/lpc2104.html


Article: 66035
Subject: Re: negative hold time
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 11 Feb 2004 13:37:00 -0800
Links: << >>  << T >>  << A >>

rickman wrote:
>  For example, when I am looking for max static current
> draw over temperature and I am given a typical current at 25C.  What is
> the designer trying to tell me?

Here is an explanation for that typical number:
In the olden days, static current was extremely low, microamps or a few
milliamps, and was usually swamped out by the dynamic power consumption.

So the argument went this way: 
If the part is hot because it is working hard, running with a fast
clock, nobody really cares about the leakage current. Even if it's
higher than the room temp spec, it is still an insignificant part of the
total current that made the chip get so hot.

When the part is not working hard, it will be near room temperature, and
because of the lack of dynamic power, the static current is a standby
value, and may be important. And everybody knows that leakage current
doubles for every 10 degree C increase in temperature. (The newly
increased leakage current is actually rising less dramatically).

With the recent dramatic increase in leakage current (by orders of
magnitude), that old reasoning may have to be revised...

Peter Alfke

Article: 66036
Subject: Re: Pricing, 101
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 11 Feb 2004 13:51:36 -0800
Links: << >>  << T >>  << A >>
The Columbia Encyclopedia describes oligopoly as: 
...the control of supply by a few producers...or by agreements among
members of an industry to restrain price competition...

Does that describe your impression of the relationship between X and A ?
 Wow !
Peter Alfke 
===========================
Steve wrote:

> This is really simple; Oligopoly 101:
> 
> Oligopolists value high order quantities highly and small order
> quantities as not being worth the hassle.
> Oligopolists watch competitors and are happy if all oligopolists in
> the market view small order quantities as not being worth the hassle.
> Certain oligopolists have a high vested interest in having smooth and
> monotonic price vs size curves, which can be maintained by having few
> distributors, and *possibly* a say on the prices they charge to
> buyers, and *possibly* exert pressure on distributors to toe the line.
> Oligopolists are happy.
> Those wanting to buy small order quantities are screwed.
> 
> > But rest assured that we are seriously looking at ways to improve the
> > plight of the low-volume customer. Some of your complaints did not fall
> > on deaf ears.
> 
> I'll quote the British phrase "the proof of the pudding is in the
> eating", or in other words I'll believe that when small quantity
> prices come down...
> 
> --
> Steve

Article: 66037
Subject: Re: Spartan-3 shipping, or perhaps not!
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 Feb 2004 14:06:33 -0800
Links: << >>  << T >>  << A >>
Leon,

Not the clearest presentation,I'll admit.

Two devices, the 50J and 1000J are ES only, as they are the non-3.3V 
versions of the part.  They are to be replaced with the non-J parts soon.

There are four devices that are 3.3V compliant, and out now.

Four are shipping and sampling with all features, with two of the four 
in production, and the remaining two in ES mode for a little longer.

Sorry for the confusion.

Austin

Leon Heller wrote:
> According to the Xilinx home page two of the Spartan-3 family are in 
> production and shipping. However, when the link is followed, one is 
> taken to an old press release which says that four family members are 
> shipping! Which is correct?
> 
> Leon


Article: 66038
Subject: Re: Pricing, 101
From: Ray Andraka <ray@andraka.com>
Date: Wed, 11 Feb 2004 17:10:37 -0500
Links: << >>  << T >>  << A >>
When was the last time you asked for technical support on a resistor?  Part of the pricing
pays for the tech support, which is more or less a per customer charge rather than a per piece
charge.  Naturally, if you are buying a large quantity, the tech support per peice is going to
be considerably less.  Tech support is one of the distributor's largest costs.

Jim Granville wrote:

> William Wallace wrote:
> > rickman <spamgoeshere4@yahoo.com> wrote in message news:<40286B1C.8BD933C4@yahoo.com>...
> <snip>
> >>
> >>And you will pay some 3 or 4 times what you would pay if you were buying
> >>1000's.  I know, I have looked.
> >>
> >
> >
> > How is this any different than any other product?  Resistors, for
> > example.  Go to digikey and try to buy 3 0805 100 Ohm resistors.  Your
> > price per resistor will be much higher than if you bought several
> > dozen reels from a distributor.
>
> I don't think anyone expects a flat price curve ( except in the
> promotion special case I mentioned earlier ).
>
> What is at issue, is the lazy application of the jelly-bean-resistor
> type price curves to much more expensive parts.
>
>   Each sales transacton has a cost, and each customer call has a cost,
> but those costs do not scale with the device price.
>
>   eg
> A price structure that has a 1 off price of $15, and volume price of $4
> is probably OK to most users.
> What's harder to justify, is a 1 off price of $150, and volume price of
> $40.
> In one case you are saying  "it costs $11 more to handle small volumes"
> - fine, but how can that possibly justify $110 extra on the larger
> device - ?
>
> -jg

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 66039
Subject: Re: Spartan-3 shipping, or perhaps not!
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 11 Feb 2004 22:23:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
Austin Lesea <austin@xilinx.com> wrote:
: Leon,

: Not the clearest presentation,I'll admit.

: Two devices, the 50J and 1000J are ES only, as they are the non-3.3V 
: versions of the part.  They are to be replaced with the non-J parts soon.

: There are four devices that are 3.3V compliant, and out now.

: Four are shipping and sampling with all features, with two of the four 
: in production, and the remaining two in ES mode for a little longer.

: Sorry for the confusion.

When can we expect these parts to be available at distributors?
E.g. nuhorizons list no XC3S available at the moment.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 66040
Subject: Re: attribute +generate statement
From: Ray Andraka <ray@andraka.com>
Date: Wed, 11 Feb 2004 17:23:46 -0500
Links: << >>  << T >>  << A >>
the naming of elements built by a generate statement is not
specified by the LRM, and is not consistent from tool to
tool.  To make it portable, as well as easier on yourself,
put the attribute in the generate statement declaration
rather than outside.  Also, you'll need to specify the value
for the generic with a generic map so that simulation
matches the hardware:

----------------------------

> architecture ...
>
> component ROM128X1
>  -- synthesis translate_off
>  generic (INIT : bit_vector := X"128");
>  -- synthesis translate_on
>  port (
>     O : out std_ulogic;
>     A0 : in std_ulogic;
>     A1 : in std_ulogic;
>     A2 : in std_ulogic;
>     A3 : in std_ulogic;
>     A4 : in std_ulogic;
>     A5 : in std_ulogic;
>     A6 : in std_ulogic
>  );
>  end component;
>
> attribute INIT : string;
>
> begin
>     t : for i in 0 to 1 generate

            attribute INIT of U:label is "..";

>
>     U : ROM128X1

        generic map(
            INIT =>  "...")

>
>     port map(
>         O => data_out(i),
>         A0 => addr_in(0),
>         A1 => addr_in(1),
>         A2 => addr_in(2),
>         A3 => addr_in(3),
>         A4 => addr_in(4),
>         A5 => addr_in(5),
>         A6 => addr_in(6)
>     );
>     end generate;
> end;

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 66041
Subject: Re: Spartan-3 shipping, or perhaps not!
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Wed, 11 Feb 2004 22:35:19 -0000
Links: << >>  << T >>  << A >>
> Four are shipping and sampling with all features, with two of the four
> in production, and the remaining two in ES mode for a little longer.

Austin,

Is that four parts in all footprints or four part/
footprint combinations?

Any more details on which four?

A client on mine has just spent a desperate couple of
days trying to source a Spartan3 device they've designed
in to their next generation product, they only need
a few (<10) for prototyping.

Any of the footprint compatible parts would probably
do, but it's hard finding out what's available.


Nial


------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 66042
Subject: Everything is not only shipping, but a lot of it shipped.....
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 Feb 2004 14:52:52 -0800
Links: << >>  << T >>  << A >>
Uwe,

The upturn in the electronics industry caught everyone off-guard.

As was disclosed in our last fiscal report, the Q to Q numbers were up 
16%, which is a lot like saying "wow!" or maybe "ouch!" -- depends on 
your point of view.

Unfortunately, we have to build our chips in advance of their need, and 
the fab cycle is not getting any shorter as the technology gets smaller. 
  No one was willing to make any committments in November.  Now everyone 
wants parts, and lots of them.

It is not only S3, but even some of the older parts as well.

Thus, the chips we find today to ship started their life sometime in the 
summer and early fall based on the projections and orders that we had, 
and anticipated.

We are doing our best to meet all requests.

Austin

Uwe Bonnes wrote:

> Austin Lesea <austin@xilinx.com> wrote:
> : Leon,
> 
> : Not the clearest presentation,I'll admit.
> 
> : Two devices, the 50J and 1000J are ES only, as they are the non-3.3V 
> : versions of the part.  They are to be replaced with the non-J parts soon.
> 
> : There are four devices that are 3.3V compliant, and out now.
> 
> : Four are shipping and sampling with all features, with two of the four 
> : in production, and the remaining two in ES mode for a little longer.
> 
> : Sorry for the confusion.
> 
> When can we expect these parts to be available at distributors?
> E.g. nuhorizons list no XC3S available at the moment.
> 
> Bye


Article: 66043
Subject: Re: Spartan-3 shipping, or perhaps not!
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 Feb 2004 14:54:18 -0800
Links: << >>  << T >>  << A >>
Nial,

FAEs have the documents, so I would suggest they put in the request to 
find out from them.

Austin

Nial Stewart wrote:

>>Four are shipping and sampling with all features, with two of the four
>>in production, and the remaining two in ES mode for a little longer.
> 
> 
> Austin,
> 
> Is that four parts in all footprints or four part/
> footprint combinations?
> 
> Any more details on which four?
> 
> A client on mine has just spent a desperate couple of
> days trying to source a Spartan3 device they've designed
> in to their next generation product, they only need
> a few (<10) for prototyping.
> 
> Any of the footprint compatible parts would probably
> do, but it's hard finding out what's available.
> 
> 
> Nial
> 
> 
> ------------------------------------------------
> Nial Stewart Developments Ltd
> FPGA and High Speed Digital Design
> www.nialstewartdevelopments.co.uk
> 
> 
> 


Article: 66044
Subject: Re: negative hold time (Typ/max)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 12 Feb 2004 12:22:55 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> rickman wrote:
> 
>> For example, when I am looking for max static current
>>draw over temperature and I am given a typical current at 25C.  What is
>>the designer trying to tell me?
> 
> 
> Here is an explanation for that typical number:
> In the olden days, static current was extremely low, microamps or a few
> milliamps, and was usually swamped out by the dynamic power consumption.
> 
> So the argument went this way: 
> If the part is hot because it is working hard, running with a fast
> clock, nobody really cares about the leakage current. Even if it's
> higher than the room temp spec, it is still an insignificant part of the
> total current that made the chip get so hot.
> 
> When the part is not working hard, it will be near room temperature, and
> because of the lack of dynamic power, the static current is a standby
> value, and may be important. And everybody knows that leakage current
> doubles for every 10 degree C increase in temperature. (The newly
> increased leakage current is actually rising less dramatically).
> 
> With the recent dramatic increase in leakage current (by orders of
> magnitude), that old reasoning may have to be revised...

... and designs need to consider complete power removal of those hungry 
devices during sleep times, which moves away from a single chip solution..

> 
> Peter Alfke

  I think rickman was asking about TYP vs MAX ?
Typical appears on a data sheet for many reasons :
- It's a better sounding number  (don't laugh..)
- It's easier/quicker to derive than a MAX corner value.
- It's also usefull for average battery life calculations.

but sometimes, customers want to know worst case battery life,
and they may even be using batteries good enough to spec that over
temperature. So they need a corresponding chip value.

If the spec omits MAX, the designer could be trying to say
any or all of :
- The silicon is so new, we don't know this number yet
- Our test coverage could not guarantee this on all devices
- We do not bother to test it
- A few devices have this very high, and we are unsure why
- Why does that number matter again ?

  The new Lattice 4000 family, and Xilinx Coolrunner II do seem
to have good Typ, and Max static Icc specs, so perhaps
those customers are more demanding ?

  Personally, I prefer to see Icc vs Temp plots, and in the old
days of data sheets, they would plot Typ and Max on the same graph!


-jg




Article: 66045
Subject: Re: Pricing, 101
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 12 Feb 2004 12:43:02 +1300
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> When was the last time you asked for technical support on a resistor? 

  Actually, more recently than I asked for support on a CPLD ;) but I do 
get your point...

> Part of the pricing
> pays for the tech support, which is more or less a per customer charge rather than a per piece
> charge.  Naturally, if you are buying a large quantity, the tech support per peice is going to
> be considerably less.  Tech support is one of the distributor's largest costs.

  I believe I said that.
  The question is how to justify the $40 -> $150, alongside
the $4 -> $15 device price/volume curve.
  FPGAs are a great example of where bigger devices just give you more 
of everything - the software tools are identical, and in most cases so 
are the building blocks, and even large chunks of data.
  So the tech support cost of the large/small fpgas are largely similar.

  The real reasons for such lazy pricing have more to do with the 
bean-counters, and wanting to have a certain % margin on stock.
  Which is OK if the disti's actually HAVE stock...

  Solution would be to have a WEB page sales system, that has a
relatively high ($20-$30-?) line item processing charge, and a
more sensible true device cost on the silicon itself.
  Still makes a nominal profit, but accelerates the design-wins,
and ramp-ups of the devices...

-jg


Article: 66046
Subject: Re: Pricing, 101
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 18:44:06 -0500
Links: << >>  << T >>  << A >>
Steve wrote:
> 
> Peter Alfke <peter@xilinx.com> wrote in message news:<4029259F.1BC8DDF6@xilinx.com>...
> > This is really simple, Capitalism 101:
> >
> > Manufacturer invents and makes part.
> > Uses seval competing distributors to sell the part to the public.
> > Manufacturer optimizes his profit by charging distributor a certain
> > price, and also publishes a pricebook with "Manufacturer Recommended
> > Resale Price" MSRP.
> > Distributor can sell in any quantity and for any price he wants, high or
> > low, but he will try to optimize his profit.
> > Customer will buy at the lowest possible price consistent with the
> > desired level of service and support.
> > This is true for food, shirts, cars, and ICs. For Tiffany's, Nordstrom,
> > Safeway and CostCo.
> 
> This is really simple; Oligopoly 101:
> 
> Oligopolists value high order quantities highly and small order
> quantities as not being worth the hassle.
> Oligopolists watch competitors and are happy if all oligopolists in
> the market view small order quantities as not being worth the hassle.
> Certain oligopolists have a high vested interest in having smooth and
> monotonic price vs size curves, which can be maintained by having few
> distributors, and *possibly* a say on the prices they charge to
> buyers, and *possibly* exert pressure on distributors to toe the line.
> Oligopolists are happy.
> Those wanting to buy small order quantities are screwed.
> 
> > But rest assured that we are seriously looking at ways to improve the
> > plight of the low-volume customer. Some of your complaints did not fall
> > on deaf ears.
> 
> I'll quote the British phrase "the proof of the pudding is in the
> eating", or in other words I'll believe that when small quantity
> prices come down...
> 
> --
> Steve


Hey Steve, why don't you get off the soapbox.  What you are doing is not
getting you anywhere and is starting to tick me off.  Until you give a
call to your distributor and *ask* what price you can get, I don't want
to listen to your rants.  

Don't make me come over there... ;)


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66047
(removed)


Article: 66048
Subject: Re: negative hold time
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 18:47:58 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> rickman wrote:
> >  For example, when I am looking for max static current
> > draw over temperature and I am given a typical current at 25C.  What is
> > the designer trying to tell me?
> 
> Here is an explanation for that typical number:
> In the olden days, static current was extremely low, microamps or a few
> milliamps, and was usually swamped out by the dynamic power consumption.
> 
> So the argument went this way:
> If the part is hot because it is working hard, running with a fast
> clock, nobody really cares about the leakage current. Even if it's
> higher than the room temp spec, it is still an insignificant part of the
> total current that made the chip get so hot.
> 
> When the part is not working hard, it will be near room temperature, and
> because of the lack of dynamic power, the static current is a standby
> value, and may be important. And everybody knows that leakage current
> doubles for every 10 degree C increase in temperature. (The newly
> increased leakage current is actually rising less dramatically).
> 
> With the recent dramatic increase in leakage current (by orders of
> magnitude), that old reasoning may have to be revised...
> 
> Peter Alfke


Uh, what if "room temp" is 85C?  That is a valid operating spec for many
chips, right? 

That was just one example I could think of off the top of my head. 
There are lots of timing related specs or even functional specs that are
just not clear in many data sheets.  I think that often these specs
reflect how the parts are tested, without thorough consideration of how
they are used.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66049
Subject: Sine Wave Generation
From: "SneakerNet" <nospam@nospam.org>
Date: Thu, 12 Feb 2004 12:51:11 +1300
Links: << >>  << T >>  << A >>
Hi all

I need some help with regards to generating a sine wave. I thought abt this
problem and some thoughts that came to mind are as follows:
1. Generate sine values using spreadsheet
2. Store these values either in ROM or make a table withing VHDL
3. Write VHDL code and output these values.

My question is:
Is it better to store these values in ROM (eg. LUT) or directly hardcode the
values.
Is there a website that will explain or give more explanation in this area.

Cheers





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