Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Peter Alfke wrote: > I was just pointing out that ultra-low power and 100 MHz do not go together, > unless you run very small voltage swing. > Peter Thinking about this issue, a look at Torex http://www.torex.co.jp/english/product/product_10.html shows some Xtal Osc modules, with lowish Iccs, and a note therein that Icc Buffer OFF, but OSC ON, can be ~1mA @ 80MHz. vs 10mA buffers ON and 15pF loaded, 3.3V Vcc. ( so one can keep a XTAL spinning for quite low currents ) Thus the idea occurs of using a Differential IO std (Vref based) on CR2, to avoid the large swing, and the Power Diss problems this causes. Question is, if one connects an external OSC buffer directly to Diff IP ( IP & Vref )on a CR2, will it operate correctly - and at what Icc levels, from the linear-mode IP that results ? There does not appear to be an Icc adder in the data for the Diff Comparitor, that is enabled - presumably that does not come 'for free', but has some Icc cost ? With no Schmitt action mentioned on the Diff Comparitor, this approach would likely have a minimum Xtal freq, in order to meet IP slew rates ( so it's unlikely to work at 32Khz..., but >50MHz should be OK ? ) Comments from the Xilinx crew welcome... -jgArticle: 67626
Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on teaching VHDL during the past years with very good results from our students. However, we have the impression that these students have difficulties working with schematics as tools to document and express their architectural ideas, in part because we did not provide them with such a schematic edition tool and thus, we are currently thinking about adding such a tool to our design flow. Among the requirements that we have collected for such a tool would be: - real schematic edition tool, and not just a drawing tool, i.e: - recognizes and keep the connectivity - understands connectors and inversion bubbles - can select whole nets and name them - is able to work with hierarchical schematics - makes a graphic difference between scalars and vectors (buses) - available for different plattforms: Wintel, Linux, Mac OSX - from the cost viewpoint, affordable by students, i.e: no high-end tool - a library with block level (adder, multiplier, ALU, registers, datapath elements, memory, etc.) symbols is available, or can easily be buit. - the tool must be able to netlist any schematic hierarchy into a VHDL skeleton with entities declaration, instantiation statements and architecture templates so that it support the VHDL code writing. Any suggestions? FranArticle: 67627
hi simon, i thought about before, i tried to get two flex10k designs into one acex and it should work. my ram use is 1/4 of the total number of the ram-bits so the rest of the ram must be used by max plus 2 who puts the logic into ram. but how can i find it and tell max plus 2 to don?t use so much eab?s regards, rolandArticle: 67628
sir/madam have added an ILA and ICON unit to my design ...however when i load it using the analyser it simply hangs and says "wainting to be uploaded". Please tell me whether this is due to the trigger. am not exaclty sure whether this is due to wrong triggering...can u help me in this regard...does this trigger have to be an externally generated signal....Article: 67629
PACE in ISE5.2 gave me the functionality of using a bare naked top level entity with only port declaration, and a few internal wires, as a model to lay out the pin assignment without any fuss. Now PACE in ISE6.2 just shows me the pins that are actually assigned internally, not everything. I wanted to knwo what do I need to do in order to regain this functionality, that is, how can PACE let me do pin assignment on ports that haven't been connected internally. Thanks JacArticle: 67630
> No, in fact, I had not noticed that there are also some pure PCI > backplanes, so that should be better for you. After some searching I found this: http://www.bsicomputer.com/bsistore/aspx/accessory3.aspx?item=BP6021-8G&subcat=BACKPLANE It appears to be a pure PCI backplane. It also appears to have some sort of Intel chip on board (could help answer the other poster's question). > First, you need to do more than just look at web pages. ISI is a > company that you need to talk with to get info on just what they do and > don't have. They have a full line of PGA adapters. It is unlikely that > they can't fit another socket. I've already contacted them about the issue and I'm currently waiting for a response. > I have not seen any PCI cards with FPGAs setup to be bus masters, but if > they are there that would be fine. Keep in mind that it will need > memory on the card since PCI transfers are much slower than SDRAM or > DDR. Yes. I realize that all these issue of actual hardware are not central to design issues but it would be nice to have some idea of how I want the architecture as a whole to work before the FPGA logic is actually designed. I believe that I have seen a few (but not many) FPGA based PCI cards that are setup as bus masters (often multiple FPGAs which can get expensive). Your point about the motherboard being ideal is sounding better and better. Hopefully ISI will come through on something to make that work. A few questions: Would using the motherboard socket give the FPGA access to some PCI bus controller (master) or would that need to be implemented in the FPGA? and How would the device be programmed? The only thing that worried me about using the CPU socket was possible overhead clutter that would fill the FPGA just to let it interface with the board. If that isn't needed then it sounds like the optimal solution. > Heck, if push comes to shove, you can use one of my boards if you will > be happy with an XC3S400. It will have SDRAM and SBSRAM, (you can > ignore the DSP chip) but only a PC104 interface, no PCI... at least not > this version. Sounds interesting, the XC3S400 is actually one of the devices near the top of my list. I doubt that the board would be right for this situation but sounds interesting none the less. > Good Luck. :) Thanks!Article: 67631
Greg Steinke wrote: > Newer Altera FPGAs (APEX II, Cyclone, Stratix) have a programmable > pull up on the IOs. This is turned on through the Quartus software. > The typical value is 25 kohms. > > There's also an option for a bus hold. This weakly holds the IO in the > last state, either high or low. It acts as a ~7 kohm resistor to VCCIO > or GND, depending on what the pin was last driven to. The > pullup/pulldown is weak enough that it can be overcome by an external > driver. Thanks for the information. Actually, in our design it is APEX EP20KE. Due to a wrong parameter we _did_ experience that the device became hot without any visible reason. Another device burnt out making a power short circuit between VCCint and GND. Thus we always declare unused pins as Output driving Ground. Janos Ero CERN Div. EPArticle: 67632
"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com... > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: (...) > Any suggestions? EagleCAD? It does not fulfill all your needs but it's free (small version suitable for students) and scalable to a full-blown system. Unfortunately it can't easily handle transition to logic/FPGA.Article: 67633
Hi, can someone tell me how to highlight a net in the schematic editor? How can I change the colour of the highlight? Thank you very much. Kind regards Andrés VázquezArticle: 67634
<snip> > Any suggestions? Haven't checked if it fulfills all your requirements but maybe this would help: http://www.expressivesystems.com/ --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.622 / Virus Database: 400 - Release Date: 14/03/2004Article: 67635
In article <4056A867.9351BC4D@nospam.com>
nospam@nospam.com "Francisco Camarero" writes:
>
>
> Hello !
>
> We are an academic institution teaching our students VLSI design, from FPGA
> to full custom ASIC. We have put great value on teaching VHDL during the
> past years with very good results from our students.
>
> However, we have the impression that these students have difficulties
> working with schematics as tools to document and express their
> architectural ideas, in part because we did not provide them with such a
> schematic edition tool and thus, we are currently thinking about adding
> such a tool to our design flow.
If you are using MS-Win platforms then "Electronics Workbench" with
the UltiCap and UltiBoard tools is excellent and not too expensive.
You should be able to cut an educational deal with them.
OrCAD is similar but I find it not as friendly to use (although I can
use either).
I should have URL's around somewhere but I think they are on my system
at work (won't be back in the office until next Monday).
--
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-811095 .... see http://www.feabhas.com for details.
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************
Article: 67636"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com... > > > Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > Fran There are some integrated schematic and VHDL tools that come with the free Xilinx ISE web edition and free versions of Altera Quartus.Article: 67637
Hi Brian Much thanks for your help. Your recollections are correct and helped me work around the problem. Thanks Denis Brian Philofsky <brian.philofsky@no_xilinx_spam.com> wrote in message news:<404D11AE.3090703@no_xilinx_spam.com>... > Denis Gleeson wrote: > > > Hi Brian > > > > Thanks for your answer, directed at my problem. > > > > I should have said that at the end of all the warnings I received, > > was the following. > > > > Warning: No Global(GSR) net could be used in the design because there > > is not a unique net that sets or resets all the sequential cells. > > > > So I am assuming that the STARTUP block has been included, even though > > I didnt specifically stipulate that it should. > > > > I am also assuming that my synthesis tool is trying to assign a signal > > assigned to a pin as a stimulus for this global net. > > As soon as one register is not cleared by this signal the GSR net is > > no more. > > > OK. Now this is starting to come back to me. In the "old days" the > synthesis tool would look to see if an asyncronous reset is described > for all FFs in a circuit and try to infer a STARTUP block for the > design. What this warning is saying is that it sees you have specified > a reset for most but not all FFs and thus could not infer the STARTUP > block and thus use the dedicated GSR resources. This should not be a > big problem for you. For what you have described, you do not want to > use the GSR resources as you do not want all FFs to be reset by that signal. > > > > I ran a simulation to see what I would get. The simulation was done > > with the scenario described, i.e. one register is not cleared by the > > input "clear" pin and synthesis gives the warnings described. > > > > I get one BUS signal at xxx? and another at 000?. Even though I am > > setting my external clear signal high. > > This is new and not what I normally get from this simulation. I > > normally get things cleared when the > > clear signal is high. > > This is a little odd. First off, are you performing an initial GSR > pulse to initialize your simulation you should have a few lines in your > testbench like: > > initial begin > force glbl.GSR = 1'b1; > #100 force glbl.GSR = 1'b0; > end > > This will put all registers into thier intial state as written in the > docs (Synthesis and Simulation Design Guide). If you are using 6.1i or > newer, this will be done automatically for you but in the earlier > versions of the software you must drive this from your Verilog > testbench. You should hold off feeding stimulus until GSR completes. > > Next, internal signals in your HDL code can get renamed by the synthesis > tool. Ensure that this internal bus does exist and has not been renamed > or possibly removed by the synthesis tool. That could also be a source > to what you are seeing. > > > > From this I assume that my efforts to clear a section of the FPGA > > leaving one register un cleared > > is not working. > > Perhaps but I would guess the problem is not with the fact you are not > rseting one register but elsewhere. Perhaps what I said above could > help you determine that. > > > > Now this is really confusing me. I have a pin assigned to have an > > external signal(with the name clear). > > This signal is sent to all FFs and counters in the FPGA in my verilog > > code. Now because I have not complied with the requirements for a GSR > > signal, I effectivly have no clear? > > I do not follow you here. First off, you do not have to use GSR, it is > just there is you want to use it. It will automatically be asserted > after power-up but whether you use it after that is up to you. From > what you have describe before, it sounds like you do not want to use it. > In that case, your code sounded fine the way it was. You do not have to > describe the reset for every FF. If you do tie it to every FF which you > can, the synthesis tool can infer a STARTUP appearently and use that > dedicated resource and you would have a "clear" signal to add FFs. > Perhaps I am missing what you are trying to say here. > > > -- Brian > > > > > > > > > Many thanks for your input. > > > > > > Denis > > __________________________ > > From Concept to Production > > http://www.centronsolutions.com > >Article: 67638
I am in the process of building a very large and demanding system on the Altera Stratix EP1S60 device. It will require most of the memory resources and has some very tricky parts for timing, since it will interface a DDR SDRAM at 167 MHz (using the Altera IP for this specific job). The custom design will also have some parts on 167 MHz and some others on multiple clock domains. To avoid huge compilation times, plus the fact that place & route tools become less efficient when dealing with big designs, I want to use the Logiclock approach. My flow is running on Linux machines and since many developers will be involved I want to automate the procedure by providing them with TCL scripts. I am using Quartus II 3.0 service pack 2 (trying to get Quartus 4.0 but not succeeded yet). My idea is to make a floorplanning on the FPGA by hand (say dividing it in around 10 big blocks), fixing these logiclock regions manually and then letting each developer do his own block. If the blocks are too big to handle, each developer may repeat this process (specifying his own regions inside his big region). So I guess I have two script requirements: - A "bottom" TCL script which defines a LOCKED region, compiles the design and back-annotates all info (locations, routing, etc) - A "top" TCL script which reads all the "bottom" regions plus back-annotated information and simply routes the top-level connections. I have proceeded in my own, and I am listing the current version of my two scripts below. It seems I have the following problems: - When the regions are imported by the top script, they lose their LOCKED state and become FLOATING. The fitter puts the regions wherever it wants, although you can still see their original assignment. - Each botttom design is compiled as a stand-alone project. Is there any way I can convince Quartus that its I/Os are NOT chip pins? Now it considers them as I/O pins, and does a less efficient time-driven fit. - I cannot store routing information with the bottom script. The "-routing" option does nothing on logiclock_export - Most commands in the logiclock package do not have help in the TCL modes! Trying for example "set_logiclock -h" returns nothing! I have figured out most of the options for the scripts below by googling and... guessing! Is there any official source like a TCL commands manual? Even the TCL chapter of the 810-pages new Quartus II 4.0 manual does not say anything on commands and their options... In the Altera website I have found a simple skeleton for importing logiclock regions, but there is no skeleton that _exports_ any logiclock region. My two scripts are below. I am using them with "quartus_cdb -t <script>". Your suggestions/comments/tributes will be greatly appreciated. Thanks you all in advance for reading so far... ================================================================================ == BOTTOM SCRIPT ================================================================================ package require ::quartus::project package require ::quartus::logiclock package require ::quartus::backannotate package require ::quartus::flow project_new "bottom" set_global_assignment -name "VHDL_FILE" "bottom.vhd" set_global_assignment -name "COMPILER_SETTINGS" "bottom" set_global_assignment -name "FAMILY" "Stratix" set_global_assignment -name "DEVICE" "EP1S60F1020C6" set_global_assignment -name "FMAX_REQUIREMENT" "167 MHz" execute_module -tool map initialize_logiclock set_logiclock -region "reg_bottom" -auto_size 0 -width 10 -height 10 -origin X1_Y1 -floating off set_logiclock_contents -region reg_bottom -to bottom execute_module -tool fit logiclock_back_annotate -region reg_bottom -routing export_assignments qexec "quartus_cdb bottom --vqm=./bottom.vqm" execute_module -tool tan project_close ================================================================================ == TOP SCRIPT ================================================================================ package require ::quartus::project package require ::quartus::logiclock package require ::quartus::backannotate package require ::quartus::flow project_new top set_global_assignment -name "VQM_FILE" "bottom.vqm" # (the rest of the "bottom" vqms are put here) set_global_assignment -name "VHDL_FILE" "top.vhd" set_global_assignment -name "COMPILER_SETTINGS" "top" set_global_assignment -name "FAMILY" "Stratix" set_global_assignment -name "DEVICE" "EP1S60F1020C6" execute_module -tool map initialize_logiclock logiclock_import -no_pins uninitialize_logiclock execute_module -tool fit execute_module -tool tan project_closeArticle: 67639
Hi everybody, I would like to get some dev. board with FPGA. I am now thinking about the Spartan 3, especially the one provided by Avnet. Could you please tell me following infos: - Are there some troubles by using this board on a 5V or 3.3V PCI bus? - What is the AvBus? How many pins on this bus? What are the signal provided (several reset, clk?...). - One of my aims is to manage video inputs or output with this device, and I plan to use some daughter boards I would use or design by my own. Has somebody tried it (including ADC, RAMDAC......)? With this kit or others? some feedback? If somebody has some other advices about development boards? others FPGAS? Any feedback is welcome, Thanks, Jerome.Article: 67640
Hi all, I'm designing a host pci cell to be mapped in an fpga (so needing the design of a specific board with pci slots). The cell is configured and managed by a tiny microprocessor, also mapped in the fpga. The aim is to allow the microprocessor to transfer data with the many devices pci bus can connect through a pci-ethernet controller or a pci-usb controller. My problem is now to find the minimal pci buffer size needed to make this configuration work. The buffer is a double port ram, connected from the one side to the microprocessor memory space, and from the other to the pci cell. Has anyone had experience in making such a minimal host ? Any help would be appreciated. Thanks Benoit Additionnal infos : - in slave mode, the cell doesn't support the burst mode and needs 4 pci cycles to transfer a 32 bit word (maximum throughput of 264 Mbits/s). - the microprocessor can read/write data from/to the buffer with a maximum throughput of 300 Mbits/s (no dma) - I plan to support at least usb1.1 and ethenet 100 Mbit/sArticle: 67641
Have a look at www.expressivesystems.com this tool is used by a few European Uni's to teach language based design. Regards, Steve Francisco Camarero <nospam@nospam.com> wrote in message news:<4056A867.9351BC4D@nospam.com>... > Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > FranArticle: 67642
Hi all, I'm trying to distribute my proyect files into different subdirectories in my ISE 6.1 proyect. All has gone well until I've tried to store files from Core Generator into an specific folder. I add the "xco" file into my proyect but when I synthesize, it generates and error telling that "vhd" file couldn't find. I have opened the "xco" file with a text editor and changed the paths. I have also changed the "top.prj" file actualizing the path of the "xco" files. I synthesys once and it works well, but if it gives me an error, I resynthesize it and it tells again that he couldn't find the "vhd" file. Then I open the "xco" file again with a text editor and I see how the path has been changed to the project folder. How can I achieve this? Thanks in advance, Arkaitz.Article: 67643
Clicking on the net will highlight (i.e select it). You can use the Tools->Options->Block/Symbol Editors->Colors and choose Node Bus and Conduit names to change the colors. - Subroto Datta Altera Corp. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0403160027.21096968@posting.google.com... > Hi, > > can someone tell me how to highlight a net > in the schematic editor? > How can I change the colour of the highlight? > > > Thank you very much. > > Kind regards > > Andrés VázquezArticle: 67644
The Quartus product from Altera will suit your needs, and includes a schematic editor with netlisting capabilities.. The Quartus design entry system allows you to mix and match VHDL, Verilog and Schematics. The product however does not support the MacOS, but will meet all the other requirements, and is widely used by universities today. The built in text editor has support for HDL language templates, and the language parser has good error location capabilities into the Text Editor. More information about the University program can be found at: http://www.altera.com/education/univ/unv-index.html A free version of the Tool can be downloaded at: http://www.altera.com/education/univ/software/unv-software.html - Subroto Datta Altera Corp. "Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com... > > > Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > FranArticle: 67645
"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com... > > > Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > Fran The best of both worlds is to do all the design in HDL, and then use a tool like Synplify's "HDL Analyst" to look at a schematic version of the synthesized code. Using Synplify one can see either the RTL or structural schematic. -KevinArticle: 67646
I guess it depends on the level of granularity you want to control. I find PACE very usefull for dropping big modules in predetermined areas, UCF to manually instantiate primitives and/or add timing constraints. I use the floorplanner to "look at the high level" and FPGA editor to modify stuff I'm not satisfied with after PAR. YMMV, I hope this helps. Fernando Philip Freidin <philip@fliptronics.com> wrote in message news:<5k3b50pv614vnfib6rs98prdmrke6rc1d0@4ax.com>... > There seem to be at least 6 ways of specifying area constraints > for a XC2V6000 design I am working on: > > 1) The constraints editor > > 2) My favorite editor UltraEdit, on the UCF file > > 3) The Floorplanner > > 4) PACE > > 5) FPGA editor > > 6) Embedded in the Verilog source > > > I expect that I will be doing both area constraints for each section > of sub-hierarchy in the design, plus some detailed placement of some > specific logic like I/O FFs, Memories, and multipliers. > > I would appreciate comments on which tool is the right one for the > job, or if the answer is that multiple of these will be needed, what > are the pros and cons of each, especially Floorplanner vs PACE > (and maybe vs FPGA editor) > > > Thanks, > PhilipArticle: 67647
Hello All, I'm doing a Stratix design using Quartus VHDL, I'm using memory blocks to double-sync signals crossing clock domains from slow to fast. Clocks are fractional multiples. (1) Static timing analysis checks the paths and complains. (2) The synthesizer rips up the memory blocks to consolidate the instances which are in different places. I'd like to cut the timing paths, but when I try I get Timing Constraint Ignored messages saying memory block MMM was removed by synthesis. I'd like to let the synthesizer combine the memories (saves device resources), I'd like not to consolidate the memories by hand (preserves my existing organization), and I'd like the timing analysis complaints to go away. What's the right thing to do ? Thanks in advance for your help and suggestions, -rajeev-Article: 67648
Hi, I invoke the Modelsim simulator from ISE Foundation (version 6.1). After changing one or more vhdl source files in the ISE, how can I hierarchically read in the modified vhdl sources ? Background: While invoking Modelsim by double click on "Simulate Behavioral Model" for the top-level testbench vhdl file, the vhdl files used for simulation do not correspond to the actual ones. Any ideas ? JürgenArticle: 67649
hello Are there any forum (on-line) or newsgoup on channel coding (and its implementation)? If any, please guide me to where it is (web or news).....to exchange idea...... thankyou
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z