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Messages from 70825

Article: 70825
Subject: File format *.eqn in Altera IDE
From: Markus Koechy <markus.koechy@web.de>
Date: Tue, 29 Jun 2004 17:31:29 +0200
Links: << >>  << T >>  << A >>
Hi,

Altera Quartus-II produces *.eqn files. Does anyone know where I can 
find a detailed description of this fileformat?

Thanks, Markus.


Article: 70826
Subject: Re: simprim X_FF component
From: c.chen@gmx.de (Chao)
Date: 29 Jun 2004 08:53:49 -0700
Links: << >>  << T >>  << A >>
Hi, Niv

thank you for your answer. yes, I knew that was caused by the setup
time requirement. It is a good idea to avoid the meta-stability for
sampling the input data. Can you give me some explanation to the X_FF
component? because it is appeard very often in the timing_sim.vhd
(i.e. tool-generated timing simulation file). Thanks

Chao.


"Niv" <niv.nospam.goaway@ntlworld.com> wrote in message news:<JpRDc.20$444.0@newsfe4-gui>...
> > when I did my timing simulation, I got the warning message:
> > # ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
> > #   Expected := 0.67 ns; Observed := 0.258 ns; At : 1.9 ns
> >
> > Can someone tell me more about the X_FF component from the simprim
> > library? Or is there any link for the explanation. I failed to find
> > out any in the past 60 minutes. Thanks for your help.
> >
> This looks like a setup & hold type violation.
> Is the signal into the flip-flop asynchronous to its clock? most likely.
> So pass the signal thru several stages of FFs to reduce meta stability.
> You'll still get the above message though.  The massage can be turned off
> but it's probably better to leave it on & check that each one really is a
> meta stability issue.
> 
> (Unless of course you have an incredibly fast clock, like GHz range).
> 
> Anyway, that's what I think, others are wlecome to correct me or re-enforce!

Article: 70827
Subject: Re: simprim X_FF component
From: Gary Michels <i_ll_reply_to_the_group@hotmail.com>
Date: Tue, 29 Jun 2004 18:28:11 +0200
Links: << >>  << T >>  << A >>
c.chen@gmx.de (Chao) writes:

> thank you for your answer. yes, I knew that was caused by the setup
> time requirement. It is a good idea to avoid the meta-stability for
> sampling the input data. Can you give me some explanation to the X_FF
> component? because it is appeard very often in the timing_sim.vhd
> (i.e. tool-generated timing simulation file). Thanks

X_FF is just the simulation model of a Flip-Flop. As far as I remember
the sources of the model are delivered with your copy of ISE. Search
the Xilinx directory for the simlation sources. Normally you compile
these sources to build your simulation library. 

If you don't like the original simulation model, just write your own one :-)

But if your problem is asynchronous inputs that cause many 'X' in simulation, 
then I'd suggest searching the group on how to switch of x-propagation of your
simulator.

BR

Article: 70828
Subject: Re: simprim X_FF component
From: "Barry Brown" <brown0_news1@agilent.com>
Date: Tue, 29 Jun 2004 09:47:21 -0700
Links: << >>  << T >>  << A >>
For ModelSim, you add this option to your vsim command:
          -GXon=FALSE

"Gary Michels" <i_ll_reply_to_the_group@hotmail.com> wrote in message
news:1xjywcpw.fsf@inter.net...
> c.chen@gmx.de (Chao) writes:
>
> > thank you for your answer. yes, I knew that was caused by the setup
> > time requirement. It is a good idea to avoid the meta-stability for
> > sampling the input data. Can you give me some explanation to the X_FF
> > component? because it is appeard very often in the timing_sim.vhd
> > (i.e. tool-generated timing simulation file). Thanks
>
> X_FF is just the simulation model of a Flip-Flop. As far as I remember
> the sources of the model are delivered with your copy of ISE. Search
> the Xilinx directory for the simlation sources. Normally you compile
> these sources to build your simulation library.
>
> If you don't like the original simulation model, just write your own one
:-)
>
> But if your problem is asynchronous inputs that cause many 'X' in
simulation,
> then I'd suggest searching the group on how to switch of x-propagation of
your
> simulator.
>
> BR



Article: 70829
Subject: ANN: Xilinx Delivers Lowest Cost, Easy-to-use $99 Spartan-3 FPGA Starter Kit
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Tue, 29 Jun 2004 09:55:31 -0700
Links: << >>  << T >>  << A >>
I thought this might be of interest to the group.

The Spartan-3 Starter Kit Board "Market-ese" press release is below.  The
details, including the full board documentation and schematics is available
via the
following links.  Likewise, you can order the US$99 board online.  If you
need additional system capabilities, Xilinx' distributor partners offer
boards with even more capabilities.

Spartan-3 Starter Kit Board
http://www.xilinx.com/products/spartan3/s3boards.htm

UG130:  Spartan-3 Starter Kit Board User Guide [2.32 MB]
http://www.xilinx.com/bvdocs/userguides/ug130.pdf

Order Online
http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=PURCHASE&sSecondaryNavPick=&category=-21488

Spartan-3 Partner Boards
http://www.xilinx.com/xlnx/xebiz/board_results.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1210305&device_family=1799&category=/Xilinx+Product+Catalog/Hardware+and+Cables/Development+Boards/Spartan-3


RELEASE:  Xilinx Delivers Lowest Cost, Easy-to-use $99 Spartan-3 FPGA
Starter Kit

Complete Environment to Develop and Verify Spartan-3 FPGA Designs

SAN JOSE, Calif., June 29, 2004 - Xilinx, Inc. (NASDAQ:XLNX) today announced
the immediate availability of its Spartan-3 Starter Kit, an easy-to-use, low
cost development system that provides instant access to the complete
platform capabilities of the Xilinx Spartan-3 FPGA family. The $99 kit
provides all the elements needed to develop, debug and complete a design,
including software, JTAG programming cables and training material. It
provides designers with an industry-leading FPGA-based solution for bringing
to market a broad range of consumer electronics, industrial, data processing
and communication applications.

"The Spartan-3 Starter Kit offers an excellent introduction to the redefined
programmable logic landscape pioneered by the Spartan-3 Platform FPGA
family," said Kapil Shankar, senior director of marketing at Xilinx. "We're
committed to making it as easy as possible for engineers to quickly harness
the flexibility of FPGAs and accelerate the transition from ASICs for their
low cost, high volume system applications."

Spartan-3 Starter Kit
---------------------------------------------------------
The Starter Kit is a complete development environment based on the Xilinx
XC3S200, a 200,000-gate Spartan-3 Platform FPGA, and includes the following
design resources:

  a.. Development board with the XC3S200 FPGA, configuration PROM and 1Mbyte
SRAM
  b.. Rich set of I/O and interfaces such as RS232, VGA and PS/2 ports
  c.. JTAG Programming Cable and Universal Power Supply
  d.. Xilinx ISE Foundation and WebPACK Design Software
  e.. Programmable Logic Guide and Spartan-3 Resource CD

About Xilinx Spartan-3 Platform FPGAs
---------------------------------------------------------
Ranging from 50,000 to 5 million system gates, the 90nm Spartan-3 platform
is the world's lowest-cost FPGA with unrivaled price points to address
customer demand for low-cost solutions. Spartan-3 FPGAs offer more density
and features in its class to allow customers to reduce overall system costs
through integration. Spartan-3 FPGAs offer a combination of highest embedded
block and distributed RAM and up to 784 I/Os. For complete information about
Spartan-3 FPGAs, visit http://www.xilinx.com/spartan3.

Pricing and Availability
---------------------------------------------------------
Priced at just $99 USD, the Spartan-3 Starter Kit is immediately available
through authorized Xilinx distributors or direct from the Xilinx online
store. For more information, visit www.xilinx.com/s3boards.

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC




Article: 70830
Subject: Re: Family Photo Album
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 29 Jun 2004 17:15:54 GMT
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

(snip)

> As soon as we have production, no one wants the ES anymore.  Sometimes 
> we have to write off a lot of ES material as it can not be sold (or 
> donate it to schools and universities -- see the Xilinx University 
> Program online!  Do not email me for the parts!).

I remember (from about 1977) someone with a whole box full of
a popular Intel DRAM chip, maybe 16kbit, but without any markings
on them at all.   I believe donated to the university, as you say.

Do your ES parts have labels on them?

-- glen


Article: 70831
Subject: Re: Family Photo Album
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 29 Jun 2004 11:06:18 -0700
Links: << >>  << T >>  << A >>
Glen,

Yes they do (have markings).  All of our ES parts are marked clearly as ES:

2V3000
ES

or

2V3000
CES

(CES is sometimes used interchangably with ES)

We generally use laser marking now on all of our components to make it 
more difficult for someone to clone the markings.

Why would anyone want to make a counterfeit FPGA?  So they can get your 
money before you discover the parts are empty.

Another really good reason to only buy from a qualified distributor.

Speaking of shoe boxes, in 1974, Gordon Moore came by UC Berkeley with a 
shoebox of 1702 EPROMs where only half of each one was good.  Sometimes 
universities get some pretty useful stuff, but mostly not.  We also had 
Western Electric #24 PNP germanium transistors donated by the old Bell 
system.....

Austin


glen herrmannsfeldt wrote:
> Austin Lesea wrote:
> 
> (snip)
> 
>> As soon as we have production, no one wants the ES anymore.  Sometimes 
>> we have to write off a lot of ES material as it can not be sold (or 
>> donate it to schools and universities -- see the Xilinx University 
>> Program online!  Do not email me for the parts!).
> 
> 
> I remember (from about 1977) someone with a whole box full of
> a popular Intel DRAM chip, maybe 16kbit, but without any markings
> on them at all.   I believe donated to the university, as you say.
> 
> Do your ES parts have labels on them?
> 
> -- glen
> 

Article: 70832
Subject: Altera SOPC Master Peripheral Design?
From: pinod01@sympatico.ca (Pino)
Date: 29 Jun 2004 12:01:16 -0700
Links: << >>  << T >>  << A >>
I developed a custom state machine design as a Master Peripheral using
the Avalon Bus specifications.  The purpose of this peripheral is to
read/write to external memory (i.e. SDRAM).   I then include this in
SOPC Builder as a User-Defined Logic and define it as a Master
Peripheral and associate my top-level entity ports to the appropriate
names for the Avalon Bus. When I include the SDRAM controller as a
slave, the SOPC Builder indicates that the Master is not connected to
the slave, and the Slave is not connected to a Master.  Since this is
an off-chip device, I include an Avalon Tri-state Bridge into SOPC
builder in order to allow SOPC Builder to automatically connect the
Master to the Slave.  However, when I do so, the message window
indicates the contrary.  The message I receive is as follows:

tri_state_bridge_0/avalon_slave is not connected to any Master. 
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave?   Why does the
tristate bridge not allow this connection to occur?

P.S.  If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors.  The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

Article: 70833
Subject: Re: FPGA jobs in Germany
From: Rene Tschaggelar <none@none.net>
Date: Tue, 29 Jun 2004 21:39:27 +0200
Links: << >>  << T >>  << A >>
lenz wrote:
> Hi,
> 
> I will finish the University within the next months. Now I am looking
> for companies in Germany in the field of FPGA. 
> 
> I have found some companies specialized in FPGA design and consulting
> - El Camino
> - Polar Design
> - Array Electronics
> 
> Are there any other FPGA design/consulting companys in Germany ?
> Which companys employ FPGAs in their products and therefore could
> be a potential employer for me ?


I guess quite a few engineers use FPGA technology without making a big 
fuss about it. Not that many will do it full time though.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 70834
Subject: Re: Nios stops responding to interrupts
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 29 Jun 2004 13:27:38 -0700
Links: << >>  << T >>  << A >>
Have you read the STATUS reg? You can read it with a RDCTL %g7
instruction. Bit 15 of the reg is the interrupt enable and 9..14 are
the current interrupt priority. If these aren't what they should be
(ie. IE is 0, IPRI is <= IRQ #) then something wierd is definitely
going on.

-- Pete

tns1 <tns1@cox.net> wrote in message news:<oEWDc.15991$6r1.6614@fed1read06>...
> I have an 8ms delay in my main loop now, and I still have the problem so 
> it does not seem like the same one. I can try adding more code to my 
> loop. Still, neither the behavior you describe nor the one I am seeing 
> are correct so what's the root cause?
> 
> My user logic module clears the IRQ whenever I read a register. Normally 
> this is done in the ISR. Eventually the IRQ does not clear because the 
> ISR is not called. (This does not seem to be the case of the ISR getting 
> called, but not clearing the IRQ for some reason). I tried adding a read 
> of the same clearing register in my main loop every 100ms. This 'kick 
> starts' the Nios when it is ignoring IRQs, but probably at a cost of a 
> lost IRQ - it works, but is not acceptable.
> 
> I can also exit my main loop (via a terminal key press), and perform a 
> manual read of the clearing register. This does clear the asserted IRQ 
> signal, but does NOT restore the system to normal operation. Even though 
> main line code runs OK, subsequent IRQs are still ignored. The only way 
> to re-enable interrupts is to reset everything. This really sounds like 
> an IRQ is being blocked in the Nios core kinda like interrupts were 
> never re-enabled internally during the previous context restore (or 
> vector table corruption or...). I guess I need to try the debugger so I 
> can look at stack pointers, status registers, etc.
> 
> I read about an option on the CWP manager that selects between HW & SW 
> handling of overflows on the register window but I don't see this choice 
>   on any tool dialog.
>

Article: 70835
Subject: Trouble with $readmemh in ModelSim
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Tue, 29 Jun 2004 13:29:07 -0700
Links: << >>  << T >>  << A >>
Hi:

I'm trying to use a memory in a Verilog testbench to generate arbitrary 
waveforms to stimulate my Verilog module.

I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.

Modelsim complains with this message:

# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
# -- Compiling module testbench
# ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4): 
near "$readmemh": syntax error
vlog -reportprogress 300 -work work 
{E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}



The offending line of testbench code looks like this:

-------------------------------------------
module testbench();

   reg [3:0] wave [0:191];  // create 192 x 4-bit waveform data table

   $readmemh( "testhex.txt", wave );  //  Load RAM from file

endmodule
-------------------------------------------

The text file looks like:

-------------------------------------------
4'h1  //count1(referringtothe74LS193datahere)
4'h1
4'h1
4'h1

4'h0
4'h0
4'h0
4'h0

4'h1  //count2
4'h1
// etc.
--------------------------------------------


Any clues?


Thanks.



-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 70836
Subject: Re: Trouble with $readmemh in ModelSim
From: Duane Clark <junkmail@junkmail.com>
Date: Tue, 29 Jun 2004 13:47:09 -0700
Links: << >>  << T >>  << A >>
Chris Carlen wrote:

module testbench();

    reg [3:0] wave [0:191];  // create 192 x 4-bit waveform data table
initial
begin
    $readmemh( "testhex.txt", wave );  //  Load RAM from file
end
endmodule

-- 
My real email is akamail.com@dclark (or something like that).

Article: 70837
Subject: Re: Trouble with $readmemh in ModelSim
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Tue, 29 Jun 2004 20:57:20 GMT
Links: << >>  << T >>  << A >>

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbsjei0nld@news2.newsguy.com...
> Hi:
>
> I'm trying to use a memory in a Verilog testbench to generate arbitrary
> waveforms to stimulate my Verilog module.
>
> I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.
>
> Modelsim complains with this message:
>
> # Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
> # -- Compiling module testbench
> # ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4):
> near "$readmemh": syntax error
> vlog -reportprogress 300 -work work
> {E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}
>
>
>
> The offending line of testbench code looks like this:
>
> -------------------------------------------
> module testbench();
>
>    reg [3:0] wave [0:191];  // create 192 x 4-bit waveform data table
>
>    $readmemh( "testhex.txt", wave );  //  Load RAM from file
>
> endmodule
> -------------------------------------------
>
> The text file looks like:
>
> -------------------------------------------
> 4'h1  //count1(referringtothe74LS193datahere)
> 4'h1
> 4'h1
> 4'h1
>
> 4'h0
> 4'h0
> 4'h0
> 4'h0
>
> 4'h1  //count2
> 4'h1
> // etc.
> --------------------------------------------
>
>
> Any clues?
>
>
> Thanks.
>
Chris,
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc  // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin



Article: 70838
Subject: Re: EDK 6.2 ISE verilog toplevel possible ?
From: "Antti Lukats" <antti@case2000.com>
Date: Tue, 29 Jun 2004 16:23:59 -0700
Links: << >>  << T >>  << A >>

"Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message
news:40D8C416.8060607@NOSPAM.com...
> This seems to be a bug in projnav when using the XMP as a source file.
>
> ISE creates the EDK project in VHDL mode. This has to be changed.
> The only way to do that today is to open the xmp file in an editor
> and change VHDL to VERILOG.
>
> Basically the projnav could not resolve the path to the edk data from
> the xmp. One way around this is to generate the netlist in XPS and
> then take that system.v file and instantiate it as a source
> in projnav. You will need to remove the xmp as a source.
-- 
> / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
> \ \ `  Xilinx                              hotline@xilinx.com
> / /    2100 Logic Drive                    http://www.xilinx.com
> \_\/.\ San Jose, California 95124-3450 USA

Dear Paulo!

there is exists a real workaround that allows normal flow in ISE having a
verilog toplevel and system.xmp !
http://xilinx.openchip.org
the fix is posted there :)

Antti Lukats,
who would accept paypal donations to antti@case2000.com email address to
help me to post more real fixes and hints where Xilinx hotline fails to help
;)

kidding, I am just an unemployed FPGA-guru living in foreign country far
away from home who hopes this "ISE/EDK verilog top" hint is useful to some
one at least!

And to Xilinx: I have fighted months and monhts with ISE/EDK/V2PDK bugs, its
getting better all the time, but still has some gotchas that may make the
use of the tools a real frustration for those who just obtain the SW and try
to use it.












Article: 70839
Subject: Re: simprim X_FF component
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Tue, 29 Jun 2004 18:01:34 -0600
Links: << >>  << T >>  << A >>


Let me start by saying, do not write your own X_FF model and do not use 
the -GXon switch.  Neither is good advice in my opinion and both of 
these can get you into far more trouble than help in almost any 
situation.  Let me first address the initial question: "Can someone tell 
me more about the X_FF component from the simprim library? Or is there 
any link for the explanation."

Simulation is covered in the Synthesis and Verification Design Guide. 
The current version is located at: 
http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
If you go to chapter 6 and go to the section "Debugging Timing Problems" 
(page 265) it will explain the timing message and how to understand what 
it is telling you, how to debug the issue and hopefully solve the 
problem.  This is also explained in less detail in Answer Record #5255 
SIMPRIM, Timing Simulation - What are "$setup" and "$hold" violations, 
and how do I fix them? (VHDL, Verilog) (at www.xilinx.com/techdocs/5255.htm)

If the input is truly an asynchronous input, then you need to design 
your circuit to avoid the side-effects of missing timing such as 
metastability and once you are satisfied, you can put an ASYNC_REG 
attribute on that register.  This has the advantage of disabling 
X-propogation on that register only so if you have a timing violation 
elsewhere, it will still behave appropriately.  The global disabling of 
X-propogation adds the danger of missing a timing violation in a 
synchronous path which can cause a very unpredictable circuit.  This too 
is covered in more detail in the documents referenced above.  Look at 
the "Disabling 'X' Propagation" section in the Synth & Verification 
Guide which is also referenced from the above section on debugging 
timing problems and the link in the Answer record.

I highly suggest you browse through the chapters of this book as it may 
explain other things you are seeing in functional and timing simulation 
and give more elegant solutions that you may have thought otherwise. 
Also the on-line answer records cover many of these topics.  Finding the 
right answer record is not always easy as there is a lot of information 
available there but if you type in the right key words, it generally 
comes out in the top few and should not be too hard to find.  You should 
not need anything near 60 minutes to find this information and if that 
is the case, then something is wrong.  If you have suggestions on 
improving how this data is presented, let me know and I can be sure to 
pass that on to the appropriate people.


--  Brian


Barry Brown wrote:
> For ModelSim, you add this option to your vsim command:
>           -GXon=FALSE
> 
> "Gary Michels" <i_ll_reply_to_the_group@hotmail.com> wrote in message
> news:1xjywcpw.fsf@inter.net...
> 
>>c.chen@gmx.de (Chao) writes:
>>
>>
>>>thank you for your answer. yes, I knew that was caused by the setup
>>>time requirement. It is a good idea to avoid the meta-stability for
>>>sampling the input data. Can you give me some explanation to the X_FF
>>>component? because it is appeard very often in the timing_sim.vhd
>>>(i.e. tool-generated timing simulation file). Thanks
>>
>>X_FF is just the simulation model of a Flip-Flop. As far as I remember
>>the sources of the model are delivered with your copy of ISE. Search
>>the Xilinx directory for the simlation sources. Normally you compile
>>these sources to build your simulation library.
>>
>>If you don't like the original simulation model, just write your own one
> 
> :-)
> 
>>But if your problem is asynchronous inputs that cause many 'X' in
> 
> simulation,
> 
>>then I'd suggest searching the group on how to switch of x-propagation of
> 
> your
> 
>>simulator.
>>
>>BR
> 
> 
> 


Article: 70840
Subject: Re: Answer Record # 18857 compiling modelsim library
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Tue, 29 Jun 2004 18:17:16 -0600
Links: << >>  << T >>  << A >>

John,

    ISE 6.1i was updated to VITAL2000 in order to get faster and more 
accurate timing on the libraries, especially for the RAM models. 
ModelSim did not support VITAL2000 until their 5.6 release (they are 
currently at 5.8) so you need at least that release to simulate a 
current ISE design.  You have the choice of either upgrading your 
simulator or downgrading your ISE tool but the two need to follow 
somewhat in sync in order to get the best features of both.

Wish I had better news for you.

--  Brian


John Craven wrote:

> Hello,
> 
> I get the same error as described by Record Number: 18857. I run 
> ModelSim 5.5F SE and ISE 6. Both tools are 2002 and later versions hence 
> must be VITAL compliant.
> 
> I keep my fingers crossed for the solution. Tnx,
> 
> Johnny
> 
> 6.1i COMPXLIB - "ERROR: Could not open library vital2000 at vital2000: 
> No such file or directory"
> 
> General Description:
> Using COMPXLIB to compile simulation libraries from the command line 
> results in an error similar to the following:
> 
> "ERROR: Could not open library vital2000 at vital2000: No such file or 
> directory
> ###### C:\Xilinx\vhdl\src\simprims\simprim_Vcomponents_mti.vhd(74): 
> library VITAL2000;
> ERROR: C:\Xilinx\vhdl\src\simprims\simprim_Vcomponents_mti.vhd(74): 
> Library vital2000 not found.
> ###### C:\Xilinx\vhdl\src\simprims\simprim_Vcomponents_mti.vhd(75): use 
> VITAL2000.VITAL_Timing


Article: 70841
Subject: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
From: csim036@ec.auckland.ac.nz (Colin)
Date: 29 Jun 2004 17:29:40 -0700
Links: << >>  << T >>  << A >>
Hi, 

I'm trying to use the Nios Ethernet Development Kit to run a simple
example program, it build fine, but when I run it it comes up with a
"spurious interrupt number: 0000 001C" error.  Does anyone know how to
solve this problem.

I'm using the Excalibur Apex development board, Nios 3.0, and the Nios
Ethernet Development Kit 2.0.

Thanx.

Article: 70842
Subject: Re: Trouble with $readmemh in ModelSim
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Tue, 29 Jun 2004 18:29:44 -0600
Links: << >>  << T >>  << A >>



I agree that the omission of the initial statement is the most likely 
cause of the syntax error but the format of the file also needs to be 
modified to avoid the next error so both follow-up posters are correct. 
  The original poster is using 5.2i so this may not help him but for the 
benefit of those on the more recent version of ISE, version 6.2i, the 
Language Templates were updated for that release and include a fairly 
good example I wrote for this function if I must say so myself.  For 
those that want to see this, open up the 6.2i Language Templates and go 
to: Verilog --> Simulation Constructs --> System Tasks and Functions --> 
File I/O --> Read Memory.  There you will find an info file that explain 
how to use this as well as a template that includes the missing initial 
statement:

INFO:

// Information on the $readmemb and $readmemh system functions
// ===========================================================
//
// $readmemb is a system function which will read binary data from a
// specified file. The syntax is the following:
// $readmemb ("<file_name>", <reg_name>); where the <file_name> is
// the name and location of the file containing the binary data and
// the <reg_name> is a 2-D register array in which the memory data
// is stored.  The data file may only contain binary data, white
// spaces and comments.  This function is generally executed within
// an initial block.
//
// $readmemh is the same as $readmemb with the exception that it
// inputs hex data as the read values.
//
// Example of reading binary data from a file:

    reg  [31:0] prom_data[1023:0];

    initial
      $readmemb("../data/mem_file.dat", prom_data);


Template for $readmemh:

    reg [<memory_width>] <reg_name> [<memory_depth>];

    initial
       $readmemh ("<file_name>", <reg_name>);



I did not include a sample file as I did not think it would be necessary 
but perhaps I should based on what I have seen here.  I may add that as 
a possible enhancement for a future release.

--  Brian


Article: 70843
Subject: Re: Trouble with $readmemh in ModelSim
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Tue, 29 Jun 2004 17:39:30 -0700
Links: << >>  << T >>  << A >>
Duane Clark wrote:
> Chris Carlen wrote:
> 
> module testbench();
> 
>    reg [3:0] wave [0:191];  // create 192 x 4-bit waveform data table
> initial
> begin
>    $readmemh( "testhex.txt", wave );  //  Load RAM from file
> end
> endmodule


Duh, of course!  You can't assign to regs except inside initial/always

Thanks!


-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 70844
Subject: Re: Trouble with $readmemh in ModelSim
From: Chris Carlen <crcarle@BOGUS.sandia.gov>
Date: Tue, 29 Jun 2004 17:42:55 -0700
Links: << >>  << T >>  << A >>
Kevin Neilson wrote:
> Chris,
> The format of the text file has to be in hex bytes, like this:
> ff // first byte
> ff ff // second and third byte
> aa bb cc  // more bytes
> 
> You can't use the 4'hf notation of Verilog.
> You can get more flexibility by using the Verilog 2001 I/O commands.
> -Kevin


Thanks for the input.

Using the tip provided by Duane Clark, I have fixed the syntax error.  I 
simply needed to use an initial statement.

But while my compiler is no longer reporting a syntax error, I have yet 
to run a sim and verify that the data is correctly read.

So I will have to confirm what you are saying later.  But if you are 
correct, then I will need this part of the picture too, so thanks!

Where can I learn about these Verilog 2001 IO commands?  Are they 
implemented in Modelsim?  I have read the documentation a little bit. 
I'll have to look in there some more.

Good day!



-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 70845
Subject: a question in the pci interface design
From: "rat" <rattt@col.edu.cn>
Date: Wed, 30 Jun 2004 10:00:50 +0800
Links: << >>  << T >>  << A >>
Hi,friends
  I am designing a pci target interface with cpld. And I want to meet the
66Mhz pci timing requirement with lattice's ispMACH 4256V-5 (Tpd=5ns). It
seems that it is hard to meet the Tsu (<= 3ns) requirement with all of the
input pins. One way is to register every signal at the input side, just like
pipeline. But is it possible to register the IRDY signal? from my
understanding, I have to check the IRDY every clock phase in a transaction
to see if the data is valid to send or receive, and the target has to
respond immediately ( from example, in a single data phase read transaction,
once irdy is asserted and data is valid at some posedge of clock, we should
deassert the trdy signal immediately)
  Any suggestion is welcome:) Thanks!

Regards

BTW: is the performance of the Altera QuartusII web edition worse than ISE
webpack or Lattice's tool? I synthesize the same design in Quartus and
Lattice's ispLevel starter ( with synplicity lattice edition), in Quartus,
the device choosed is max3128a-5, in ispLevel, device is ispMACH4128v-5. But
the timing analysis result is so different, ispMACH is better. What is the
problem?



Article: 70846
Subject: Re: Nios stops responding to interrupts
From: tns1 <tns1@cox.net>
Date: Tue, 29 Jun 2004 22:34:39 -0700
Links: << >>  << T >>  << A >>
Thanks for the tip. Right now my code is all C, but I have hopes of 
getting GDB working tomorrow - should answer many questions. One thing 
that I did find is that delays in either the ISR or the main loop did 
not help. Since the problem behavior masks interrupts, I forced an 
interruptenableblah() but it did not fix things. Odd, I believe the 
debug port uart uses interrupts and it never stops working.

I looked for vector table corruption and noticed that all the vectors, 
including my installed ones, point to addresses in flash. My system is 
supposed to copy the flash code to sram and execute from there. This 
does not seem correct unless all IRQs are first directed thru a trapping 
routine like I have seen for some RTOSes. The debugger should tell all.


Peter Sommerfeld wrote:
> Have you read the STATUS reg? You can read it with a RDCTL %g7
> instruction. Bit 15 of the reg is the interrupt enable and 9..14 are
> the current interrupt priority. If these aren't what they should be
> (ie. IE is 0, IPRI is <= IRQ #) then something wierd is definitely
> going on.
> 
> -- Pete
> 
> tns1 <tns1@cox.net> wrote in message news:<oEWDc.15991$6r1.6614@fed1read06>...
> 
>>I have an 8ms delay in my main loop now, and I still have the problem so 
>>it does not seem like the same one. I can try adding more code to my 
>>loop. Still, neither the behavior you describe nor the one I am seeing 
>>are correct so what's the root cause?
>>
>>My user logic module clears the IRQ whenever I read a register. Normally 
>>this is done in the ISR. Eventually the IRQ does not clear because the 
>>ISR is not called. (This does not seem to be the case of the ISR getting 
>>called, but not clearing the IRQ for some reason). I tried adding a read 
>>of the same clearing register in my main loop every 100ms. This 'kick 
>>starts' the Nios when it is ignoring IRQs, but probably at a cost of a 
>>lost IRQ - it works, but is not acceptable.
>>
>>I can also exit my main loop (via a terminal key press), and perform a 
>>manual read of the clearing register. This does clear the asserted IRQ 
>>signal, but does NOT restore the system to normal operation. Even though 
>>main line code runs OK, subsequent IRQs are still ignored. The only way 
>>to re-enable interrupts is to reset everything. This really sounds like 
>>an IRQ is being blocked in the Nios core kinda like interrupts were 
>>never re-enabled internally during the previous context restore (or 
>>vector table corruption or...). I guess I need to try the debugger so I 
>>can look at stack pointers, status registers, etc.
>>
>>I read about an option on the CWP manager that selects between HW & SW 
>>handling of overflows on the register window but I don't see this choice 
>>  on any tool dialog.
>>


Article: 70847
Subject: Re: a question in the pci interface design
From: Luc Braeckman <luc.braeckman@pandora.be>
Date: Wed, 30 Jun 2004 06:55:32 GMT
Links: << >>  << T >>  << A >>
Hi,

There are some enhancements in the architecture that make the ispMACH
better than the Max7k (or Max3k).
1. Have you tried the ispExplorer in the ispLEVER software? This tool
gives you the opportunity to optimize your design and make a
comparison between different settings.
2. Study the architecture and make use of it.
3. work with your local FAE to find a solution, he will be able to
judge the settings and the design.

Best regards

On Wed, 30 Jun 2004 10:00:50 +0800, "rat" <rattt@col.edu.cn> wrote:

>Hi,friends
>  I am designing a pci target interface with cpld. And I want to meet the
>66Mhz pci timing requirement with lattice's ispMACH 4256V-5 (Tpd=5ns). It
>seems that it is hard to meet the Tsu (<= 3ns) requirement with all of the
>input pins. One way is to register every signal at the input side, just like
>pipeline. But is it possible to register the IRDY signal? from my
>understanding, I have to check the IRDY every clock phase in a transaction
>to see if the data is valid to send or receive, and the target has to
>respond immediately ( from example, in a single data phase read transaction,
>once irdy is asserted and data is valid at some posedge of clock, we should
>deassert the trdy signal immediately)
>  Any suggestion is welcome:) Thanks!
>
>Regards
>
>BTW: is the performance of the Altera QuartusII web edition worse than ISE
>webpack or Lattice's tool? I synthesize the same design in Quartus and
>Lattice's ispLevel starter ( with synplicity lattice edition), in Quartus,
>the device choosed is max3128a-5, in ispLevel, device is ispMACH4128v-5. But
>the timing analysis result is so different, ispMACH is better. What is the
>problem?
>


Article: 70848
Subject: Re: simprim X_FF component
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Wed, 30 Jun 2004 11:41:37 +0100
Links: << >>  << T >>  << A >>
Brian Philofsky wrote:
> Finding the right answer record is not always easy as there
> is a lot of information available there but if you type in
> the right key words, it generally comes out in the top few
> and should not be too hard to find.

But nowhere near as easily as if you had a Google-style search
interface.  Searching answers at X is absurdly difficult unless
you are in the priesthood.



Article: 70849
Subject: Problems with custom IP in Xilinx Project Navigator
From: Michael Dales <mwd24@thompson.cl.cam.ac.uk>
Date: 30 Jun 2004 12:49:59 +0100
Links: << >>  << T >>  << A >>
Hi there,

I've been trying to build a verilog module wrapping a DCM and an IBUFGDS, 
which inputs a differential 62.5 MHz clock source for feeding into the Xilinx 
GEMAC core. Most of this project is being built in XPS, with the actual
synthesis being done in Project Navigator.

However, I keep get warnings in Project Navigator when I build my 
design about nets that aren't on my DCM wrapper. I tried scaling my 
verilog back until I contained just a IBUFGDS, and then to just an OR gate 
(for testing purposes), and still I get these errors:

ERROR:NgdBuild:455 - logical net 'diff_clk_input_0/N309678' has multiple
   drivers. The possible drivers causing this are:
     pin G on block diff_clk_input_0/XST_GND with type GND,
     pin PAD on block diff_clk_input_0/N309678 with type PAD
ERROR:NgdBuild:466 - input pad net 'diff_clk_input_0/N309678' has illegal
   connection. Possible pins causing this are:
     pin G on block diff_clk_input_0/XST_GND with type GND

My verilog module is called diff_clk_input and the instance name in XPS is 
diff_clk_input_0.

Nowhere in any file can I find reference to XST_GND or N309678 (the number 
after N changes every time I try a new design revision).

I tried playing about the with ..._xst.scr file options, but that didn't
seem to help.

Anyone have any ideas? It's a really stupid little thing to be stuck on,
but it's holding me up completely.

Cheers,

-- 
Michael Dales
University of Cambridge Computer Laboratory
http://www.cl.cam.ac.uk/~mwd24/



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