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Thanks for both your replies Paul. Just one point of clarification. I haven't looked carefully at Lattice's Flash products, but I did look at Actel's products. Actel's Flash devices do not use SRAM at all. Instead, the configuration memory is using Flash cells instead of SRAM cells. You are absolutely right that due to this, they are one process node behind Xilinx/Altera; they will ship 130nm this year. Ok, I think I am now beginning to see the picture a bit. It sounds like a very daunting task to choose a FPGA device. The free software tools on the web help (have to download and fire those up). Paul, do you have any idea how many people are using FPGAs for shipping products ? I am wondering if most FPGAs are still being used for prototyping. I remember reading that the Rio MP3 player had FPGAs - were those relatively small FPGAs or CPLDs ? I ask because the large multi-million gate devices seem to be too expensive, both in terms of price and power, to ship in products .. right ? Thanks again. SumitArticle: 72001
Is anyone using the JTAG UART as the console port for microblaze? I've
figured out that you can type 'term' from 'xmd' to open a (very crummy,
always line buffered) terminal window which allows you to send lines
as console input, but console output still appears in the xmd window.
Does anyone know of any way to improve this situation: i.e., so I can have a
simple real (VT100) terminal window connected to the JTAG UART? Perhaps
there is a better tcl script for xmd?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 72002Hi Mark, When I say fail, I mean the tool works fine and I d/l the design to my chip, but then after I run the design it fails in the lab after a few minutes. I know most of the logic is still functioning but some critical parts of it have stopped causing complete failure. Matt On Thu, 5 Aug 2004, Marc Randolph wrote: > Matthew E Rosenthal wrote: >> Has anyone seen output pins cause a design to randomnly fail? >> >> I have a very solid design that I accidently left two OBUFs with no ucf >> LOC contraint. depending how much i fill a v2pro device my logic will >> fail seemingly randmonly with these two OBUFs instantiated. >> >> I know that the randomn locations that ISE is choosing is not colliding >> with anything on my board but the design fails consistenly. > > Howdy Matt, > > First off, what do you mean by fail? Does PAR or MAP stop? Or does it make > it through the tools and then somehow not work when you put it on the board? > > I'm assuming you meant MAP or PAR would abort... in which case, I've had > situations like that before. It seems like the tool isn't especially smart > about how it assigns locations of things (especially GBUFs and DCMs) and > walks itself into a corner it can't get out of. I seem to recall also having > some problems with IOBs from time to time - it is as if the tools sometimes > pick pins but ignore the banking rules. Then later, it detects the rule > violation and stops. Again, this is from memory, so I may be remembering the > situation incorrectly. > > But since you have a board, you want all the pins nailed down, right? > > Have fun, > > Marc >Article: 72003
Larry, You can purchase the Embedded Development Kit (EDK) from the Xilinx Store for $495. EDK will include the compiled MicroBlaze core to use in your design. A list of the other IP included with EDK can be found at: http://www.xilinx.com/ise/embedded/edk_ip.htm Cheers, Shalin- Lawrence D. Lopez wrote: > I was wondering if someone could tell me > what is free and what is not. > > I've purchased (and it's on the way) the $99 > Spartan-3 development kit and I'm wondering > if any additional expenses are invoked by > using the various IP property on xilinx's web > pages. > > Larry >Article: 72004
Hello, I have recently read some articles on superconducting circuits, and I would like a n opinion on if the area of superconducting circuits is a good and growing for doing research. particularly at stony brook, where researchers have produced a lot of work. Does this area require lot of knowledge on superconductivity and physics. you suggestions are welcome. thanking you supradeepArticle: 72005
Hi, I am looking for a topic for my Ms thesis on reconfigurable systems design. I would like to know which are the current topics of research in this area. I would very much appreciate your help. thanking you, supradeepArticle: 72006
> Thanks for both your replies Paul. Just one point of clarification. > I haven't looked carefully at Lattice's Flash products, but I did look > at Actel's products. Actel's Flash devices do not use SRAM at all. > Instead, the configuration memory is using Flash cells instead of SRAM > cells. You are absolutely right that due to this, they are one > process node behind Xilinx/Altera; they will ship 130nm this year. I stand corrected -- I forgot about ProASIC. I'm not sure how efficient a Flash-based cell is vs. a SRAM cell or SRAM + seperate Flash. You've got the pain of having to distribute higher-voltage rail for writing (I think) the Flash and other such overhead. Who knows... > Ok, I think I am now beginning to see the picture a bit. It sounds > like a very daunting task to choose a FPGA device. The free software > tools on the web help (have to download and fire those up). I can make your decision easy -- buy Altera :-) > Paul, do you have any idea how many people are using FPGAs for > shipping products ? I am wondering if most FPGAs are still being used > for prototyping. I remember reading that the Rio MP3 player had > FPGAs - were those relatively small FPGAs or CPLDs ? I ask because > the large multi-million gate devices seem to be too expensive, both > in terms of price and power, to ship in products .. right ? Many customers are shipping production products using FPGAs, otherwise there's no way FPGAs would be $2.5B+ per year. If you look at Cyclone, the last publicly disclosed numbers said we'd shipped 2M devices. That's either a lot of prototyping, or we've got customers going to production :-) Development, debugging, time to market, mask & tool costs, etc. make ASICs pricey. When you compare to ~$10 FPGAs, you need volumes of 200,000+ for you to even start considering an ASIC. That's a pretty hefty volume. Similar economics hold true for higher-end FPGAs -- the cost per device is higher, but so is the development cost of the equivalent ASIC, especially if you need PLLs + RAMs + fancy I/Os, and you want them to work correctly. If you listen to the quarterly earnings conference call from Altera last month, I think there were some stats on customers in production vs. pre-production, etc. While consumer is a growing part of our business, much of the FPGA consumption in this area is in things like high-end DVDs, TVs, broadcasting equipment, modems and other such wall-powered devices. Most battery powered devices are tiny, have very low power budgets and strict stand-by current requirements, and have very high volumes. Plus there are enough players and volume in these markets that some company can make (for example) a custom MP3 player chip that will do very well addressing all these concerns and be cheaper to boot. CPLDs still make their way into these devices (everyone needs glue logic), but my guess is there are few battery applications that will tolerate the constant trickle of a 90nm cutting-edge FPGA on board! Regards, Paul Leventis Altera Corp.Article: 72007
Matt North wrote: > Hi, > > I have written VHDL code which generates standard VGA Timing signals; 640 x > 480 resolution 60Hz refresh rate. > My question is this; my test monitor is a SONY SDM-S93 which has a > resolution of 1280 x 1024, the HSync, VSync and Blanking > periods all meet with the specifications of the monitor. > However how does the monitor know that i will only use 640 out of a possible > 1280 dots per line, and 480 lines out of 1024? > Do i have to send it some control info via the DC0-3 pins? > > I understand that the monitor can display lower resolutions because this can > be done inside windows! > When selecting 640x480 resolution in windows the screen is stretched to fill > the monitor; does this mean that the graphics card > is always running at the 1280x1024 frequency and adds pixel data to fill the > screen? > > Thanks for the help. > > Matt > > Some monitors simply detect the ratio between V-SYNC and H-SYNC. If there are 480 H-SYNC for each V-SYNC, it assume input is 640x480. If there are 600 H-SYNC for each V-SYNC, it assume input is 800x600. If there are 768 H-SYNC for each V-SYNC, it assume input is 1024x768, etc. It also need to determine the refresh rate, this is done by checking the frequency of V-SYNC. From these information it can then work out the exact time to sample each pixel. JoeArticle: 72008
As is suprnova, etc. no luck at all... I can't be the only person in the world using StateCAD to generate C code!! sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>... > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > Due to a calamtity of computer problems, including some affecting my > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > possibly Version 5.0) to support an active project. An evaluation > > version is fine. Can anyone help? > > eMule is your friend. Check it out and see if you can find a copy there. :)Article: 72009
Hey all, Does anybody know of a good tutorial for EDK 6.2 that doesn't explicitly use a premade dev board. I want to create a project from scratch and add a plb buss and a few devices to the plb buss. There are so many wires and unknowns that I can't do this without some useful instruction manual or tutorial to copy from. Does this exist and if not am i crazy for asking for it? MattArticle: 72010
> Vivek Joshi wrote: > > I had a question on whether you can use Chipscope pro to load an > external SRAM connected to the FPGA. I want to use ChipSCope Pro to > load data into an SRAM, is there a way to automate this, any > suggestions or comments regarding this? Is this a feasible idea? the TCL interface does allow to talk to BSCAN yes, but if you want to use ChipScope and load memories you need a bit more work, its doable but you must regenerate ICON with no BSCAN instance and connect ICON to it manually, and connect your custom cores for ram loading to the other free BSCAN user port. then you can use tcl to download rams and at the same time keep chipscope funtionlity Antti http://xilinx.openchip.orgArticle: 72011
Derek Simmons wrote: > > Does anybody know how this works for a LCD display? > > Using my laptop as a reference system, if I select the 1024 x 768 I > get a full screen display. If I select a lower resolution display, 800 > x 600 I get a smaller size image inset on the display. Is this > characteristic of LCD displays? > > If somebody could point me to a resource that describe how to generate > the signals necessary for LCD display I would greatly appreciate it. There are LCD monitors and LCD laptop displays. The difference is the interface. The LCD in the laptop uses an all digital interface so that the computer has full control over the operation of the LCD. The interface to a monitor is normally VGA like analog signal (unless you use a digital interface) so that the monitor has to receive an analog signal. This signal is converted back to digital by using a PLL to sync a clock to the pixel rate. This requires the monitor to be a bit smart about how it decides to select a pixel rate. So the two different display types have different capabilities and level of control. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72012
rickman wrote: > Jim Granville wrote: > >>rickman wrote: >><snip> >> >>>I have one socket on a board that Xilinx could not fill. I needed 5 >>>volt compatibility in a relatively low power device. All of the newer >>>(read supported by current software) devices that are 5 volt tolerant >>>have a power on current surge that makes it hard to use in a low power >>>design without extra circuitry. So I ended up using an Altera ACEX >>>(EP1K) device which is only about 3-4 years old. Otherwise their newer >>>chips are mostly similar. >> >>.. Perhaps the new Virtex-4 that Peter A. is dying to tell us about also >>solves the 5V i/o issues ;) > > > I can assure you that it does not. The problem is twofold, 1) with the > thinner oxides that are being used, it gets harder and harder to provide > 5 volt tolerance without adding processing steps which drives up the > cost and 2) 5 volt tolerance is becomming less and less important as > various standards evolve away from the use of 5 volt interfaces. > > It has been explained to me several times that in the FPGA world, they > had two choices, retain 5 volt tolerance or compete effectively in the > high dollar, most current technology markets. You may have missed my smiley ? ;) -jgArticle: 72013
Matt, Do you have any mates at Insight? Their tutorial for Ultracontroller is meant to run on their dev. board, but the Insight chap got it up and running on my company's board from scratch in 2 hours. Cheers, Syms. "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.GSO.4.60-041.0408051728040.2770@unix3.andrew.cmu.edu... > Hey all, > Does anybody know of a good tutorial for EDK 6.2 that doesn't explicitly > use a premade dev board. > I want to create a project from scratch and add a plb buss and a few > devices to the plb buss. There are so many wires and unknowns that I > can't do this without some useful instruction manual or tutorial to copy > from. > Does this exist and if not am i crazy for asking for it? > > MattArticle: 72014
I don't use it. I tried it or a similar program awhile back and I found that it just put another level of confusion between me and the hardware. I normally like to have better control over the bits in an FPGA. If you read some examples on the web, I am sure you will find it easy to code FSMs directly in VHDL (or verilog). If you email me a GIF or PDF of your state diagram I would be happy to show you how I would code it. mmock wrote: > > As is suprnova, etc. no luck at all... I can't be the only person in > the world using StateCAD to generate C code!! > > sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>... > > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > > Due to a calamtity of computer problems, including some affecting my > > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > > possibly Version 5.0) to support an active project. An evaluation > > > version is fine. Can anyone help? > > > > eMule is your friend. Check it out and see if you can find a copy there. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72015
Kelvin,
Sorry. I didn't see your post on the netgen problem. I am aware
that there was a problem in Map in a previous version of the tools that
could cause Netgen to crash with hierarchical designs under certain
circumstances however that should be fixed by the latest service pack.
If possible, could you try it again with the 6.2i SP3 version of the
software. If that does not work for you, I would be happy to work with
you to correct this problem. Just contact me directly (remove the no_
and _spam from the e-mail address) if you want to take me up on this
offer. It should be working for you and if not, I would like to know why.
-- Brian
Kelvin wrote:
> Thank you Brian.
>
> The problem was, the netgen always crashed when I attempted to write a
> hierarchical netlist.
> I was doing some partial reconfigurable design in V2-6000.
> I asked this crash question in this ng also but I can't solve that so fat.
> Flattening was my
> last resort.
>
> Kelvin
>
>
>
>
>
>
> "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
> news:cerpdb$li15@xco-news.xilinx.com...
>
>>
>>Eyck Jentzsch wrote:
>>
>>>Hi Kevin,
>>>
>>>Kelvin wrote:
>>>
>>>
>>>>Hi, there:
>>>>
>>>>My Xilinx software generated a flattened netlist and SDF each over
>>>>100MB...Now NC_Verilog
>>>>takes hundreds of hours to simulate that.
>>>>
>>>>Now if I write a perl to replace all the long wire names with some
>
> random
>
>>>>10-alphabet string,
>>>>it will probably shrink the file size to 10MB...But will that make my
>>>>simulation faster?
>>>>---sample
>>>> wire
>>>>
>
> \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
>
>>>>0)/F ;
>>>> wire
>>>>
>
> \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
>
>>>>0)/G ;
>>>>
>>>>
>>>>Thanks.
>>>>Kelvin
>>>>
>>>>
>>>>
>>>
>>>This will not help much, it will just speedup the simulation startup
>>>because of less file reading.
>>>It will help more to check if you used all performance switches (and
>>>aviod performance degrading options like +access+rwc or linedebug ;-)).
>>>The online documentation (cdsdoc) has a dedicated chapter ('Maximising
>>>simulation performance') for it.
>>>HTH
>>>
>>>-Eyck
>>>
>>
>>I agree with what has been said here but offer another possible
>>suggestion to help out with this situation. Why are you flattening the
>>netlist? If you keep some hierarchy (some not all of it), it will
>>likely allow you to better manage the simulation in multiple ways.
>>First, that will likely shrink many of the signal names you are having
>>problems with as the hierarchy is no longer needed to be preserved into
>>each individual signal name. Second, it would allow you to set
>>accessibility to separate portions of the design by allowing you to
>>specify the optimizing of portions you are not currently debugging and
>>allowing visibility to the portions you are. Third, you can do a full
>>timing simulation of part of your design so rather than trying to
>>simulate the whole thing at once, you could do it in pieces. This not
>>only makes for smaller and usually faster simulations but also can allow
>>the re-use of sub-level testbenches, allow for parallel simulations (if
>>you have more licenses available), uses less memory/less machine
>>requirements, easier debug since it is smaller and better understood,
>>and a handful of other benefits. Fourth, you could replace the portions
>>of the design you are not currently trying to perform a timing
>>verification on with behavioral or RTL code thus doing a mixed
>>behavioral/RTL/Timing simulation which should perform much better than a
>>full structural simulation.
>>
>>At some point in the design, it is always beneficial to do a full
>>netlist timing simulation as it can detect problems that can be easily
>>missed in functional simulation and static timing analysis (even in
>>fully synchronous designs) however that is generally best done at the
>>very end of the design cycle. Much of the timing verification can many
>>times be done more efficiently in pieces by retaining the hierarchy and
>>using it in this phase of verification. For information on hierarchy
>>preservation for simulation, look at Chapter 6 in the Synthesis and
>>Verification design Guide, the section titled, "Design Hierarchy and
>>Simulation":
>>http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
>>
>>Hope this helps.
>>
>>-- Brian
>>
>
>
>
Article: 72016I am a full professor in a US school and do research in the area of synthesis. I also teach logic design for Undergraduate students. I had a six month sabbatical recently in a design house and I used many FPGA cad tools. I would like to shed my experiences in this group. I worked on 15 big designs, already coded, targeting both virtexII and StratixII. All the designs were in verilog and I used Xilinx XST and Altera QNS at the front end. I spent lot of time to see the quality of results from the synthesis tools. For 11 designs, QNS won both in area and final fmax. XST was not even comparable in the quality of results. QNS compiler seems to do very good job compared to XST. Also, QNS does very good job in removing redundant logic and registers. So in my experience, QNS is a much better logic synthesis tools compared to XST. At the end of my sabbatical, I was able to use the latest (beta) synplify PRO. I did not have much time, but I did run these 15 designs targeting StartixII, as I was interested in comparing with the best known results. Synplify Pro did excellent job in implementing operators, and it found optimal five, six and seven inputs functions on the critical paths. For my ten designs, Pro results were superior in terms of area and fmax compared to QNS. Synplify Pro has a very fast run time. For the remaining five designs, QNS seems to remove lot of redundant logic and registers, which pro did not remove. I did not have time to analyze these designs. QNS area was much smaller for these five designs. I am back to my school and I use free XST and QNS tools. I am going to do more research using these tools. I would like to share my experience in this group. I am also interested in listening the quality of results from various tools. Prof. John Smith a2003zz@yahoo.comArticle: 72017
"John Smith" <a2003zz@yahoo.com> wrote in message news:b97fd375.0408051432.6baf5760@posting.google.com... > I am a full professor in a US school and do research > in the area of synthesis. I also teach logic design for > Undergraduate students. I had a six month sabbatical recently > in a design house and I used many FPGA cad tools. I would > like to shed my experiences in this group. > > I worked on 15 big designs, already coded, targeting both virtexII > and StratixII. All the designs were in verilog and I used > Xilinx XST and Altera QNS at the front end. I spent lot > of time to see the quality of results from the synthesis > tools. For 11 designs, QNS won both in area and final > fmax. XST was not even comparable in the quality of results. > QNS compiler seems to do very good job compared to > XST. Also, QNS does very good job in removing redundant logic > and registers. So in my experience, QNS is a much better logic synthesis > tools compared to XST. I'm not sure what this is telling us. It looks like you compared the fmax of some designs in VirtexII (quite old technology) and StratixII (quite new/future technology), and observed that the StratixII implementation was faster. From this you deduced that the Altera synthesis was better. What am I missing here?Article: 72018
On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote: >I am a full professor in a US school and do research >in the area of synthesis. I also teach logic design for >Undergraduate students. I had a six month sabbatical recently >in a design house and I used many FPGA cad tools. I would >like to shed my experiences in this group. > Let's see: - name is John Smith - full professor at US school, but no mention of school name - yahoo e-mail address - Having attended engineering school, I realize that English is not a top priority for students or faculty. Even so, the phrase "I would like to shed my experiences" is not exactly confidence-inspiring. I suppose this could be legit, but the ol' bogosity meter is sitting near full scale. For starters, could you give us the university and department names? Thanks, Bob Perlman Cambrian Design WorksArticle: 72019
Pete Fraser wrote: > "John Smith" <a2003zz@yahoo.com> wrote in message > news:b97fd375.0408051432.6baf5760@posting.google.com... > >>I am a full professor in a US school and do research >>in the area of synthesis. I also teach logic design for [snip] > > From this you deduced that the Altera synthesis was better. > > What am I missing here? My B.S. detectors are hitting full scale deflection on this one! "John Smith"? Pseudo-anonymous name, anonymous email, simple grammatical errors, explicitly saying "full professor", not identifying which school... nah.... But why?Article: 72020
I would rather not use the ultracontroller design anymore. I want to create a EDK project from scratch, add a plb buss, add a few peripherials(gpio and uart). Doesnt sound like i am asking for the world but i am having a tough time finding some simple instructions on how to do it. anybody know where i can find some instructions for this? Matt On Thu, 5 Aug 2004, Symon wrote: > Matt, > Do you have any mates at Insight? Their tutorial for Ultracontroller is > meant to run on their dev. board, but the Insight chap got it up and running > on my company's board from scratch in 2 hours. > Cheers, Syms. > "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message > news:Pine.GSO.4.60-041.0408051728040.2770@unix3.andrew.cmu.edu... >> Hey all, >> Does anybody know of a good tutorial for EDK 6.2 that doesn't explicitly >> use a premade dev board. >> I want to create a project from scratch and add a plb buss and a few >> devices to the plb buss. There are so many wires and unknowns that I >> can't do this without some useful instruction manual or tutorial to copy >> from. >> Does this exist and if not am i crazy for asking for it? >> >> Matt > > >Article: 72021
John Williams wrote: > Pete Fraser wrote: > >> "John Smith" <a2003zz@yahoo.com> wrote in message >> news:b97fd375.0408051432.6baf5760@posting.google.com... >> >>> I am a full professor in a US school and do research >>> in the area of synthesis. I also teach logic design for > > > [snip] > >> >> From this you deduced that the Altera synthesis was better. >> >> What am I missing here? > > > My B.S. detectors are hitting full scale deflection on this one! > > "John Smith"? Pseudo-anonymous name, anonymous email, simple > grammatical errors, explicitly saying "full professor", not identifying > which school... nah.... > > But why? Perhaps the author is the Prof. John Smith that google turns up here :) http://www.a2zcolleges.com/adm/samplereco.html -jgArticle: 72022
supradeep@gmail.com (supradeep narayana) wrote in message news:<3e4ee61a.0408051028.1f0d694d@posting.google.com>... > Hello, > I have recently read some articles on superconducting circuits, and I > would like a n opinion on if the area of superconducting circuits is a > good and growing for doing research. particularly at stony brook, > where researchers have produced a lot of work. > Does this area require lot of knowledge on superconductivity and > physics. > you suggestions are welcome. > thanking you > supradeep For the purposes of the digital engineer, superconducting chips are super dead, IBM cancelled that no-producing technology 10-15yrs ago. But for power engineering and magnetics theres still some future I guess. regards johnjakson_uas_comArticle: 72023
Is there some way of comparing how big Altera devices are versus Xilinx devices. Whereas Xilinx lists the "System Gates", Altera lists logic elements. So, I am not sure how to equate the product families from the two vendors. Any help will be appreciated. Thanks SumitArticle: 72024
Anyway, maybe it is because I didn't upgrade my software. I am using 6.2.02i
only.
The error is pasted below, though my partial implementation and assembly had
no error.
Kelvin
C:\projects\bt11a_jul28\top_bt\assemble>netgen -sim -ofmt
verilog -w -ism -sdf_anno true -ngm top_sdr_map.ngm top_sdr.ncd
Release 6.2.02i - netgen G.30
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Loading device database for application netgen from file "top_sdr.ncd".
"top_sdr" is an NCD, version 2.38, device xc2v6000, package bf957,
speed -6
Loading device for application netgen from file '2v6000.nph' in environment
C:/Xilinx6.2.
The STEPPING level for this design is 0.
ERROR:Anno - Cannot correlate logic element
'"Mmux__n0004_inst_mux_f6_0/MUXF6"
(tag=32161 in view "FRAGCOVERED")' is with this component 'bus_left(0)' -
cannot continue hierarchical correlation)
ERROR:Anno -
-
- This application found errors in the Ngm and/or Ncd data files
- KEEP_HIERARCHY was corrupted and ignored (database will be flattened)
-
"Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
news:4112B258.1070403@no_xilinx_spam.com...
> Kelvin,
>
> Sorry. I didn't see your post on the netgen problem. I am aware
> that there was a problem in Map in a previous version of the tools that
> could cause Netgen to crash with hierarchical designs under certain
> circumstances however that should be fixed by the latest service pack.
> If possible, could you try it again with the 6.2i SP3 version of the
> software. If that does not work for you, I would be happy to work with
> you to correct this problem. Just contact me directly (remove the no_
> and _spam from the e-mail address) if you want to take me up on this
> offer. It should be working for you and if not, I would like to know why.
>
>
> -- Brian
>
>
> Kelvin wrote:
> > Thank you Brian.
> >
> > The problem was, the netgen always crashed when I attempted to write a
> > hierarchical netlist.
> > I was doing some partial reconfigurable design in V2-6000.
> > I asked this crash question in this ng also but I can't solve that so
fat.
> > Flattening was my
> > last resort.
> >
> > Kelvin
> >
> >
> >
> >
> >
> >
> > "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
> > news:cerpdb$li15@xco-news.xilinx.com...
> >
> >>
> >>Eyck Jentzsch wrote:
> >>
> >>>Hi Kevin,
> >>>
> >>>Kelvin wrote:
> >>>
> >>>
> >>>>Hi, there:
> >>>>
> >>>>My Xilinx software generated a flattened netlist and SDF each over
> >>>>100MB...Now NC_Verilog
> >>>>takes hundreds of hours to simulate that.
> >>>>
> >>>>Now if I write a perl to replace all the long wire names with some
> >
> > random
> >
> >>>>10-alphabet string,
> >>>>it will probably shrink the file size to 10MB...But will that make my
> >>>>simulation faster?
> >>>>---sample
> >>>> wire
> >>>>
> >
> >
\modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
> >
> >>>>0)/F ;
> >>>> wire
> >>>>
> >
> >
\modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
> >
> >>>>0)/G ;
> >>>>
> >>>>
> >>>>Thanks.
> >>>>Kelvin
> >>>>
> >>>>
> >>>>
> >>>
> >>>This will not help much, it will just speedup the simulation startup
> >>>because of less file reading.
> >>>It will help more to check if you used all performance switches (and
> >>>aviod performance degrading options like +access+rwc or linedebug ;-)).
> >>>The online documentation (cdsdoc) has a dedicated chapter ('Maximising
> >>>simulation performance') for it.
> >>>HTH
> >>>
> >>>-Eyck
> >>>
> >>
> >>I agree with what has been said here but offer another possible
> >>suggestion to help out with this situation. Why are you flattening the
> >>netlist? If you keep some hierarchy (some not all of it), it will
> >>likely allow you to better manage the simulation in multiple ways.
> >>First, that will likely shrink many of the signal names you are having
> >>problems with as the hierarchy is no longer needed to be preserved into
> >>each individual signal name. Second, it would allow you to set
> >>accessibility to separate portions of the design by allowing you to
> >>specify the optimizing of portions you are not currently debugging and
> >>allowing visibility to the portions you are. Third, you can do a full
> >>timing simulation of part of your design so rather than trying to
> >>simulate the whole thing at once, you could do it in pieces. This not
> >>only makes for smaller and usually faster simulations but also can allow
> >>the re-use of sub-level testbenches, allow for parallel simulations (if
> >>you have more licenses available), uses less memory/less machine
> >>requirements, easier debug since it is smaller and better understood,
> >>and a handful of other benefits. Fourth, you could replace the portions
> >>of the design you are not currently trying to perform a timing
> >>verification on with behavioral or RTL code thus doing a mixed
> >>behavioral/RTL/Timing simulation which should perform much better than a
> >>full structural simulation.
> >>
> >>At some point in the design, it is always beneficial to do a full
> >>netlist timing simulation as it can detect problems that can be easily
> >>missed in functional simulation and static timing analysis (even in
> >>fully synchronous designs) however that is generally best done at the
> >>very end of the design cycle. Much of the timing verification can many
> >>times be done more efficiently in pieces by retaining the hierarchy and
> >>using it in this phase of verification. For information on hierarchy
> >>preservation for simulation, look at Chapter 6 in the Synthesis and
> >>Verification design Guide, the section titled, "Design Hierarchy and
> >>Simulation":
> >>http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
> >>
> >>Hope this helps.
> >>
> >>-- Brian
> >>
> >
> >
> >
>
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