Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
KCL wrote: >> Hi, list, >> I got a few questions when I was using the XILINX webpack software for a >> homebrew small project. I appreciate your answers. >> >> 1. Will the software try to use a global clock network to route a >> non-clock >> signal, if the signal drives many inputs? > > NO, If you want to use global clock network you should infer a global > clock buffer (bufg) component , I did not assign any pins. I just let the software to give a free run, and it automatically infered a global clock buffer for my HOST_WR input (supposed to be connected to a CPU WR\ pin). vax, 9000Article: 81051
> Ah. The RPM is not supposed to contain ANY IOBs. You have to turn OFF > IOB instantiation in both the Synthesis and Translate phases (either via > command line, or "Properties" for each tool. > > You can confirm that IOBs have been successfully disabled in the "map" > report file. > > Then create the RPM .ngc file as now, and multiple instantiations should > work. Connecting up IOBs is best done at the top level. > > Even if it is possible to build an RPM with package pins included, and > you can live with the restrictions placed on placing the resulting RPMs > (they have to be aligned with IOBs!) it is quite likely that tool > support for this practice may be buggy. Last I looked, RLOCs and LOCs were incompatible - kind of a problem when your pins are locked down by LOCs :) JeremyArticle: 81052
xing1234@yahoo.com wrote: > Then what's the best way to know how fast my logic can run on the > FPGAs? Do I have to use the synthesis(from synplify for example) result > to fgiure out the maximum frequency? any other methods? Howdy, Synthesis tools can give you a first order approximation of the maximum frequency, but unless you have some experience with the design and know what place and route will do with it, I'd be skeptical until I'd run it all the way through at least once. There are just too many variables (high fanout and many levels of logic being the two largest) involved with an unknown design, especially if it is coming from an ASIC. Good luck, MarcArticle: 81053
Ok I don't recall OTOH but google for <USB logic analyzer> brings up a no of devices, some of which have been posted (advertised) here and from $200 to $4K. I'm sure most are programmable too in C but you will have to review them yourself, and google back here in groups for same, maybe even user comments. regards johnjakson at usa dot comArticle: 81054
Hi list, I don't have ethernet connection though I do have an ethernet card installed. My computer can boot either with linux or win XP. I have dial up connection under linux only. I downloaded ALTERA software version 4.2 (yeah, overnight dialup), obtained the license (with an arbitrary ethernet number), and copied the files to windows partition and installed. The problem is now that under XP, when I run the software it does not think the license is a valid one. My question is whether I really need ethernet connection under XP to run ALTERA. If I obtain another license with the correct ethernet card number I have, will this license be valid when I don't really have ethernet connection? Too tired today to do the experiment. I will appreciate it if you have a quick answer. Otherwise I will have to do the experiment and report the result here. vax, 9000Article: 81055
Hi, I need to know if my pci device with dma capabilities can read-modify-write in one cycle. Whether such a things at all exists ? I want to read host main memory from a pci device without the operating system modifying it till I am done, in other words I need some form of mutual exclusion. Is this at all possible ? your help is greatly appreciated! AllisonArticle: 81056
vax, 9000 wrote: > Hi list, > I don't have ethernet connection though I do have an ethernet card > installed. My computer can boot either with linux or win XP. I have dial up > connection under linux only. I downloaded ALTERA software version 4.2 > (yeah, overnight dialup), obtained the license (with an arbitrary ethernet > number), and copied the files to windows partition and installed. > The problem is now that under XP, when I run the software it does not > think the license is a valid one. My question is whether I really need > ethernet connection under XP to run ALTERA. If I obtain another license > with the correct ethernet card number I have, will this license be valid > when I don't really have ethernet connection? > Too tired today to do the experiment. I will appreciate it if you have a > quick answer. Otherwise I will have to do the experiment and report the > result here. > > vax, 9000 Just a data point: I have an ethernet card, but use a wireless card to access DSL. Quartus works fine with that card's number. Wade HArticle: 81057
Thank you JJ. I have found some of them. "JJ" <johnjakson@yahoo.com> wrote in message news:1111028775.560833.217490@o13g2000cwo.googlegroups.com... > Ok I don't recall OTOH but google for <USB logic analyzer> brings up a > no of devices, some of which have been posted (advertised) here and > from $200 to $4K. I'm sure most are programmable too in C but you will > have to review them yourself, and google back here in groups for same, > maybe even user comments. > > regards > > johnjakson at usa dot com >Article: 81058
Hiya, > Hi list, > I don't have ethernet connection though I do have an ethernet card > installed. My computer can boot either with linux or win XP. I have dial > up connection under linux only. I downloaded ALTERA software version 4.2 > (yeah, overnight dialup), obtained the license (with an arbitrary ethernet > number), and copied the files to windows partition and installed. > The problem is now that under XP, when I run the software it does not > think the license is a valid one. My question is whether I really need > ethernet connection under XP to run ALTERA. If I obtain another license > with the correct ethernet card number I have, will this license be valid > when I don't really have ethernet connection? > Too tired today to do the experiment. I will appreciate it if you have a > quick answer. Otherwise I will have to do the experiment and report the > result here. The problem is that when the network card isn't plugged in, and is set to get an IP address over DHCP, it doesn't give out a valid ethernet address. You can disable the DHCP media sensing using the registry. Microsoft's support website has an article about this at the following URL: http://support.microsoft.com/kb/q239924/ This boils down to: Use Registry Editor (regedit.exe) to view the following key in the registry: HKEY_LOCAL_MACHINE\System\CurrentControlSet\Services\Tcpip\Parameters Add the following registry value: Value Name: DisableDHCPMediaSense Data Type: REG_DWORD Value Data Range: 0, 1 (False, True) Default: 0 (False) Description: This parameter controls DHCP Media Sense behavior. If you set this value data to 1, DHCP, and even non-DHCP, clients ignore Media Sense events from the interface. By default, Media Sense events trigger the DHCP client to take an action, such as attempting to obtain a lease (when a connect event occurs), or invalidating the interface and routes (when a disconnect event occurs). So if you create the key and set its value to 1, everything should work properly. Best regards, BenArticle: 81059
I want to experiment the parallel port with eight LEDs tied to a cut parallel port cable, then send instructions with Visual Basic to create some patterns. Is there any danger to my laptop? Thanks.Article: 81060
I found PP is unable to drive such LEDs, which needs 20mA, but what is the converter chip I shall order? Thanks "Sea Squid" <Sea.Squid@hotmail.com> wrote in message news:423928c3@news.starhub.net.sg... > I want to experiment the parallel port with eight LEDs tied to > a cut parallel port cable, then send instructions with Visual Basic > to create some patterns. Is there any danger to my laptop? > > Thanks. > > > >Article: 81061
Hi ALL!
I started large DSP project by Xilinx System Generator.
1.I have some problems in my design with "loop back".
I inserted "Use explicit sample period" for all components in loop.
But in simulation i have :
"The Relational Block received data in an indeterminate ("don't care")
state" .
Design have no errors - VHDL Netlist Generation - OK .
Any idea to help simulator ? I have some attempts by inserted Register
with Reset - no good results.
2. Who have good experience with Xilinx System Generator ?
I need in your opinion. Is this Soft equal to new funny toy or real CAD
product ?
Thank you.
Alexander Litvinov
Article: 81062Hello, We have designed a Cyclone-based FPGA board which is handy in two situations : - Quick prototyping for industrial control and robotics systems - Education (even self-) You can find a description of the Education KIt (and of the board) at : http://alse-fr.com/Tornado/Torn_Educ_us.pdf Feedback (like ideas about more Labs) are welcome, but orders too :-) The board (& kit) is available on-shelf. Best regards, BertArticle: 81063
Sea Squid wrote: > I found PP is unable to drive such LEDs, which needs 20mA, but what is the > converter chip I shall order? Any logic would be rather inconvenient because there is no power supply at the parallel port. The parallel port can drive at least 2mA which is not extremly bright but visible for most leds. Just connect a series resistor of 300 ohms or so to each LED. Kolja SulimmaArticle: 81064
Sea Squid wrote:
> I found PP is unable to drive such LEDs, which needs 20mA, but what is the
> converter chip I shall order?
>
> Thanks
>
Look here:
http://www.logix4u.net/parallelport1.htm
There is a schematic for doing exactly what you want to do.
(comp.arch.fpga?)
--
Regards,
Robert Monsen
"Your Highness, I have no need of this hypothesis."
- Pierre Laplace (1749-1827), to Napoleon,
on why his works on celestial mechanics make no mention of God.
Article: 81065Hi, It's very odd and frustrating, if i start with the port on memec, i have to change the IDCODE in a .bsd file (http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13529) and i can't debug; if i start with an example from Xilinx, which works fine in SRAM and i modify it to include the sources of uC/OS-II, i can't build the system : /xygdrive/c/DOCUME~1/GAILLI~1/LOCALS~1/Temp/ccvN6OEm.s: Assembler messages: /xygdrive/c/DOCUME~1/GAILLI~1/LOCALS~1/Temp/ccvN6OEm.s:339: Error: Variable is accessed using small data read write anchor, but it is not in the small data read write section Any suggestions ?Article: 81066
Thank you Mr. Bilski ! > > The memory blocks in EDK can only have the size of 2**N so you need two memory > blocks, one of 16kbyte and one of 8 kbyte. > This should give you enough memory. > The .elf can reside in bram and my project is "marked to initialise BRAMs". > > But I would suggest that you starting to use the external memory on the board. > With SRAM or only BRAMs, i have the same problem concerning the debugging : "Unable to Stop MicroBlaze Verify if FPGA is configured and MicroBlaze System Clock is connected properly Unable to connect to MicroBlaze" > > On the problem with debugging, much more information is needed about your system. > Have you enabled HW debug logic on MicroBlaze? > I don't know exactly what does "HW debug logic enabling" mean, but i have a debug_module connected to microblaze. Concerning my system with brams, here is my .mhs : PARAMETER VERSION = 2.1.0 PORT tx = tx, DIR = OUT PORT sys_rst = sys_rst_s, DIR = IN PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK PORT sw = sw, VEC = [0:7], DIR = IO PORT rx = rx, DIR = IN BEGIN opb_uartlite PARAMETER INSTANCE = myuart PARAMETER HW_VER = 1.00.b PARAMETER C_DATA_BITS = 8 PARAMETER C_CLK_FREQ = 50000000 PARAMETER C_BAUDRATE = 57600 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER C_BASEADDR = 0x80002000 PARAMETER C_HIGHADDR = 0x800020ff BUS_INTERFACE SOPB = myopb PORT TX = tx PORT RX = rx END BEGIN opb_timer PARAMETER INSTANCE = mytimer2 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x80002100 PARAMETER C_HIGHADDR = 0x800021ff BUS_INTERFACE SOPB = myopb PORT Interrupt = timer2 PORT CaptureTrig0 = net_gnd END BEGIN opb_timer PARAMETER INSTANCE = mytimer1 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x80002200 PARAMETER C_HIGHADDR = 0x800022ff BUS_INTERFACE SOPB = myopb PORT CaptureTrig0 = net_gnd PORT Interrupt = timer1 END BEGIN opb_v20 PARAMETER INSTANCE = myopb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 0 PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN opb_intc PARAMETER INSTANCE = myintc PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x80002300 PARAMETER C_HIGHADDR = 0x800023ff BUS_INTERFACE SOPB = myopb PORT Intr = timer1 & timer2 PORT Irq = interrupt END BEGIN opb_gpio PARAMETER INSTANCE = mygpio_c PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x80002400 PARAMETER C_HIGHADDR = 0x800025ff BUS_INTERFACE SOPB = myopb PORT GPIO_IO = sw END BEGIN microblaze PARAMETER INSTANCE = mblaze PARAMETER HW_VER = 2.10.a PARAMETER C_USE_BARREL = 0 PARAMETER C_FSL_LINKS = 0 PARAMETER C_FSL_DATA_SIZE = 32 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_USE_MSR_INSTR = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 BUS_INTERFACE DLMB = d_lmb BUS_INTERFACE ILMB = i_lmb BUS_INTERFACE DOPB = myopb BUS_INTERFACE IOPB = myopb PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s PORT DBG_TDI = DBG_TDI_s PORT INTERRUPT = interrupt PORT DBG_CLK = DBG_CLK_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT CLK = sys_clk_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = islmb PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = porta END BEGIN lmb_v10 PARAMETER INSTANCE = i_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dslmb PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = portb END BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x80002600 PARAMETER C_HIGHADDR = 0x800026ff BUS_INTERFACE SOPB = myopb PORT OPB_Clk = sys_clk_s PORT DBG_UPDATE_0 = DBG_UPDATE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_REG_EN_0 = DBG_REG_EN_s END BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN bram_block PARAMETER INSTANCE = bram1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = portb BUS_INTERFACE PORTA = porta END BEGIN bram_block PARAMETER INSTANCE = bram2 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = porta2 BUS_INTERFACE PORTB = portb2 END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = islmb2 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00006000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = porta2 END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dslmb2 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00006000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = portb2 END I hope it will help you...Article: 81067
Sorry no help here, just a confirmation that I see the same thing. I've successfully run it previously and never touch the seed setting, but it doesn't work for me anymore -- just stops after the first iteration regardless of how many point there are. Strange. Tommy PS: 4.2.SP1 also Douglas Sykora wrote: > "Douglas Sykora" <djsykoraNOSPAMM@execpc.com> wrote in message > news:113djevp68pa56d@corp.supernews.com... > >>Thomas, >> Thanks for the tip. I will try the enumerated seed specification as > > soon > >>as I get into work. I have been using the range specification such as >>2-10. >>Thanks >>Doug >>"Thomas Entner" <aon.912710880@aon.at> wrote in message >>news:42369e19$0$15878$91cee783@newsreader02.highway.telekom.at... >> >>>Hi Doug, >>> >>>there are versions of DSE that supports seeds like 1-10 20-30, other >>>versions need that you write 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 > > 27 > >>28 >> >>>29 30. Maybe you are writing "1-10" in a version that does not support >> >>this? >> >>>Beside that DSE worked always fine for me (not tested distributed usage >>>yet). >>> >>>Thomas >>> >>>www.entner-electronics.com > > > Thomas, > I tried the typing in the seeds as you suggested, but it did not help. > The version I am using (4.2 SP1) allows entering seeds in either format. > Thanks, > Doug > > > >>>"Douglas Sykora" <djsykoraNOSPAMM@execpc.com> schrieb im Newsbeitrag >>>news:113cqgdrss51rbf@corp.supernews.com... >>> >>>>Altera includes the Design Space Explorer (DSE) along with Quartus II. >> >>I >> >>>>have found this tcl script to be very helpful when I can get it to > > work > >>>>for >>>>me. But lately, it has been very frustrating because it fails to >> >>explore >> >>>>the space I set it up to explore. >>>> >>>>Has anyone else seen this behavior? >>>> - I set up the exploration space in the DSE GUI, for example, to do a >>>>seed >>>>sweep. >>>> - DSE starts by running a compilation flow on the base. >>>> - DSE finishes this and archives the results. >>>> - DSE stops and displays a message that there are no errors or >> >>warnings. >> >>>>It doesn't go on to the next point in the exploration space. >>>> >>>>I have also tried this with the distributed computing option. DSE > > will > >>>>create archives, one for each exploration point. It then submits one > > to > >>a >> >>>>remote computer and fails to actually compile it, and the process > > ends. > >>>>If you have seen this behavior, do you know what could be causing it > > and > >>>>how >>>>to correct it. >>>> >>>>I have not found any references to this problem in the archives and >>>>haven't >>>>received much help yet from the Altera support group, but I am hoping >> >>this >> >>>>is forthcoming. >>>> >>>>I am running with the Windows XP operating system (also tried Windows >>>>2000) >>>>and using the latest version of Quartus II (4.2 SP1). >>>> >>>>I have used DSE successfully, so it doesn't always display this >> >>behavior. >> >>>>Thanks in Advance, >>>>Doug >>>> >>>> >>> >>> >> > >Article: 81068
It is a "normal" synchronous DRAM (Infineon HYB25L128160AC). MichaelArticle: 81069
Preben Holm wrote: > Hi everyone, > > why doesn't this synthesize: > > > architecture Behavioral of datacontroller is > type states is std_logic_vector(4 downto 0); > constant stateStart : states := "00001"; > constant stateWait : states := "00010"; > constant stateTrigger : states := "00100"; > constant stateHold : states := "01000"; > constant stateRead : states := "10000"; > > signal holdoff : std_logic; > signal holdoff_counter_enable, holdoff_counter_reset : std_logic; > > component counter19bit > Port ( clk, ce, reset : in std_logic; > preset : in std_logic_vector(19 downto 0); > c : out std_logic; > q : out std_logic_vector(18 downto 0)); > end component; > begin > [SNIP] > > > It's directly taken from the book "VHDL made easy". > I'm using Xilinx Webpack 6.3i! > > Are you sure? I would expect subtype states is std_logic_vector(4 downto 0); regards Alan -- Alan Fitch Doulos Ltd http://www.doulos.comArticle: 81070
> > If I obtain another license >> with the correct ethernet card number I have, will this license be valid >> when I don't really have ethernet connection? >> Too tired today to do the experiment. I will appreciate it if you have a >> quick answer. Otherwise I will have to do the experiment and report the >> result here. > > The problem is that when the network card isn't plugged in, and is set to > get an IP address over DHCP, it doesn't give out a valid ethernet address. I don't think this is relevant Ben, the license file is generated against the 12 hex digit MAC address of the ethernet card, not the IP address. The MAC address should be unique for every piece of ehternet connectable kit. You can get your MAC address by opening a (windows) command window and typing ipconfig -all, it's listed as Physical Address. Nial.Article: 81071
Whichever way you go, get the revised classic
HDL Chip Design, A Practical Guide for Designing, Synthesizing and
Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J Smith,
published by Doone Publications.
I have the much earlier ASIC edition which compares 100 or more typical
small problems such as datapaths, FSMs etc in V & V and with well drawn
(hand, not machine IIRC) schematics of what's synthesized. It seems its
been brought upto date with added C & FPGA stuff, must treat myself.
I prefer Verilog too inspite of its own wierdness and shortcomings,
after all it was designed more at the wirehead level where VHDL came
from the DOD as a committee language. Both langs are very bloated and
you will likely use <20% of either.
As for the noted Verilog C likeness, thats only true for expressions
which can sometimes be almost C compiled but then you would lose most
of the expressive HW power. If only C expressions could handle {,,} =
{,,,,}, very large size expressions, logic reductions, continuous &
registered <= assignments etc. The rest of the language is much more
Pascal'ish as is VHDL. VHDL certainly enforces more rigourous type
checking in the ADA style by multiple descriptions as in the C++ way of
prototypes and implementations. Note that Java moved away from that
idea since multiple compiler passes can resolve all the forward
backward references of declare before or after useage..
Also on a syntax note, C is far more complex to describe from a
compiler pt of view, HDLs in general have always had powerfull but
consistant BNF structures where C allows trully lazy coding style (10
ways to say the exact same thing), Verilog's BNF is way easier to
describe than C, its in the back of most Verilog books.
Certainly for synthesis about 20% or less can be synthesized either
way, the rest is there for modelling which came long before synthesis
(early 90s). Indeed Verilog contains a chunk of language (UDPs) usefull
only to the distant past of gate level table driven modelling.
I'd like to see a unified Verilog C language which looks like either &
both but with most of the useless stuff thrown out, ie a cycle/event C
with Verilogs expressiveness that is synthesizeable when using that
syntax and not when using the C syntax. (I'm not too keen on
Confluence).
Career wise though Verilog in USA, Japan & ASICs, VHDL in EU, Mil, and
FPGAs although most ASIC guys are gonna end up doing FPGAs so the war
will continue. Anyway both languages are now under the same roof!
http://www.accellera.org/home
my 2c
regards
johnjakson at usa dot com
Article: 81072are there c compiler for picoblaze? how can i load program FPGA or ROM? JTAG???Article: 81073
Ulf, I'm having trouble replying to you directly. Is your mail address correct. ulf@a-t-m-e-l.com Or am I being stupid!!Article: 81074
Check the "data2mem" program installed with ise. HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips "Sea Squid" <Sea.Squid@hotmail.com> wrote in message news:4238e536$1@news.starhub.net.sg... > I made use of two 1K*10B single port RAMs generated with coregen > which is modified to contain my test vector, and P&R with that. However, > I have one thousand test vector files in plain text to send to the FPGA one > at a time. > > I am wondering about whether I can write a perl script to manipulate the > bitstream and generate an *incremental* bitstream so that I can avoid > running ISE for one thousand times? Where can I find such information? > > Thanks. > > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z