Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 82400

Article: 82400
Subject: Re: Xilinx VirtexII master serial mode problem(cclk)
From: "eou4" <false0@gmail.com>
Date: 12 Apr 2005 03:38:07 -0700
Links: << >>  << T >>  << A >>

Hal Murray wrote:
> >M0 M1 M2 correct("000").
>
> Your previous post said:
> > M0 M1 M2 is tied with pull-up resistors.
>
> I usually think of "up" as being a 1.  If you really
> have pullups, that's probably your problem.
>
> --
> The suespammers.org mail server is located in California.  So are all
my
> other mailboxes.  Please do not send unsolicited bulk e-mail or
unsolicited
> commercial e-mail to my suespammers.org address or any of my other
addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.

Oh, my mistake.. It Connected pull-down resistors. No pull-up resistors.


Article: 82401
Subject: Re: How do I disable Microblaze on-chip hw debug
From: John <nospam.nospam@nospam.com>
Date: Tue, 12 Apr 2005 12:42:45 +0200
Links: << >>  << T >>  << A >>
Thanks Antti,

I am very fresh with processor capabilties in FPGA's and I still don't  
understand how I can make my program "free running". After I download the  
program it seems to stop - probably at a breakpoint. I need to run XMD to  
get beyond this breakpoint. I have tried to set set C_DEBUG_ENABLE = 0 and  
C_NUMBER_OF_PC_BRK = 0 in the MicroBlaze parameter settings but still the  
program does not seem to run. Any further suggestion anyone?


John




På Tue, 12 Apr 2005 12:16:10 +0200, skrev Antti Lukats  
<antti@openchip.org>:

> "John" <nospam.nospam@nospam.com> schrieb im Newsbeitrag
> news:opso36rgfbg6mgav@visitech-jd.visitech.local...
>> Hi,
>>
>> I have used the Xilinx XPS to debug a design on a custom board (on-chip  
>> hw
>> debug). Now, I want to disable the debug so the code run once the FPGA  
>> is
>> programmed. Beleive or not, but I don't find a easy way to to do this.  
>> Can
>> anyone help me?
>>
>> Thanks,
>>
>> John
>
> there is no disable and its also not needed, you can leave the MDM  
> component
> in the system it doesnt do anything if not accessed by XMD, so it doesnt
> matter. After cold start the Microblaze starts from the initialized  
> BRAMs.
> If you are sure you dont need the MDM anymore just remove the MDM core
> instance and related signals and resynthesize in XPS
>
> antti
> http://gforge.openchip.org
>
>



-- 
Sendt med M2 - Operas revolusjonerende e-postprogram:  
http://www.opera.com/m2/

Article: 82402
Subject: Re: Xilinx 7.1 ISE patch - for XC9500/XL/XV and CoolRunnerXPLA3
From: "eou4" <false0@gmail.com>
Date: 12 Apr 2005 03:57:29 -0700
Links: << >>  << T >>  << A >>
I had many many problems with xc9500 before this patch available .

Divider, counter, even output just connected '1' or '0' through buffer.

My time back, Xilinx~


Article: 82403
Subject: Re: How do I disable Microblaze on-chip hw debug
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Apr 2005 13:02:15 +0200
Links: << >>  << T >>  << A >>
"John" <nospam.nospam@nospam.com> schrieb im Newsbeitrag
news:opso371ja0g6mgav@visitech-jd.visitech.local...
> Thanks Antti,
>
> I am very fresh with processor capabilties in FPGA's and I still don't
> understand how I can make my program "free running". After I download the
> program it seems to stop - probably at a breakpoint. I need to run XMD to
> get beyond this breakpoint. I have tried to set set C_DEBUG_ENABLE = 0 and
> C_NUMBER_OF_PC_BRK = 0 in the MicroBlaze parameter settings but still the
> program does not seem to run. Any further suggestion anyone?
>

in order to have stand-alone system you can not use 'download' the program
must be located completly in the on chip BRAM's, so you use XPS "update
bitstream" this will merge the software (.ELF file) and the FPGA hardware
(.BIT), then you program the FPGA with the result. And microblaze starts..

you must have marked your software application 'MARK to init BRAMs' in XPS
!!

if your application does not fit into BRAM, (XPS will warn you if that is
the case) then you need some bootloader and nonvolatile media in order to
initialiaze any other memories connected to the system. This may indeed be
painful as you need custom linker scripts, etc. etc..

antti





Article: 82404
Subject: 2 bit multiplier
From: xiibweb@hotmail.com
Date: 12 Apr 2005 04:27:38 -0700
Links: << >>  << T >>  << A >>

Hi,

I hv tried to run the following 2bit multiplier vhdl code in xilinx...
and getting following error...

HDLParsers:164 - "C:/Projects/knm/2bit.vhd" Line 11. parse error,
unexpected INTEGER_LITERAL, expecting IDENTIFIER

I am just a beginner any1 kindly help....

thnx

John

here is the code...

**********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity 2bit is
    Port ( A0 : in std_logic_vector(1 downto 0);
           A1 : in std_logic_vector(1 downto 0);
           B0 : in std_logic_vector(1 downto 0);
           B1 : in std_logic_vector(1 downto 0);
           B2 : in std_logic_vector(3 downto 0);
           C0 : out std_logic_vector(3 downto 0);
           C1 : out std_logic_vector(3 downto 0);
           C2 : out std_logic_vector(3 downto 0);
           C3 : out std_logic_vector(3 downto 0));
end 2bit;

architecture Behavioral of 2bit is

begin
     C0 <= A0 and B0;

     C1 <= (A0 and not A1 and B1) or
                  (A0 and not B0 and B1) or
                  (not A0 and A1 and B0) or
                  (A1 and B0 and not B1);

     C2 <= (A1 and B1 and not B0) or
                   (A1 and not A0 and B1);

     C3 <= A1 and A0 and B1 and B0;

end Behavioral;

**********************************************************


Article: 82405
Subject: Global buffer feeding non clock pins in VIRTEX II
From: giachella.g@laben.it (g. giachella)
Date: 12 Apr 2005 04:30:52 -0700
Links: << >>  << T >>  << A >>
In my design (in a Virtex II) there are 2 clocks, each of them on
global buffer and feeding 2 sets  of distinct registers (block A and
block B). The clocks then feed a clock switching circuit (not a
BUFGMUX) and the resulting clock feeds another part of the design
(block C).
 
From PAR report I get 

WARNING:CLK Net:FPGA_CLK_BUFGP
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.

WARNING:CLK Net:SMP_CK_MASTER_TO_CPU
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.

I suppose this message warns about a potentially unacceptable skew
between blocks A/B and block C , but the skew inside block A or block
B is still guaranteed to be low.

Am I right ?
  
Thanks

Article: 82406
Subject: Re: Reverse engineering masked ROMs, PLAs
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Tue, 12 Apr 2005 11:31:47 GMT
Links: << >>  << T >>  << A >>
Regarding the guy who read the antique calculator ROMs in metal cans, could 
he not have simply read them out by whatever method the CPU did?




Article: 82407
Subject: Re: 2 bit multiplier
From: "eou4" <false0@gmail.com>
Date: 12 Apr 2005 04:37:30 -0700
Links: << >>  << T >>  << A >>

xiib...@hotmail.com wrote:
> Hi,
>
> I hv tried to run the following 2bit multiplier vhdl code in
xilinx...
> and getting following error...
>
> HDLParsers:164 - "C:/Projects/knm/2bit.vhd" Line 11. parse error,
> unexpected INTEGER_LITERAL, expecting IDENTIFIER
>
> I am just a beginner any1 kindly help....
>
> thnx
>
> John
>
> here is the code...
>
> **********************************************************
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity 2bit is
>     Port ( A0 : in std_logic_vector(1 downto 0);
>            A1 : in std_logic_vector(1 downto 0);
>            B0 : in std_logic_vector(1 downto 0);
>            B1 : in std_logic_vector(1 downto 0);
>            B2 : in std_logic_vector(3 downto 0);
>            C0 : out std_logic_vector(3 downto 0);
>            C1 : out std_logic_vector(3 downto 0);
>            C2 : out std_logic_vector(3 downto 0);
>            C3 : out std_logic_vector(3 downto 0));
> end 2bit;
>
> architecture Behavioral of 2bit is
>
> begin
>      C0 <= A0 and B0;
>
>      C1 <= (A0 and not A1 and B1) or
>                   (A0 and not B0 and B1) or
>                   (not A0 and A1 and B0) or
>                   (A1 and B0 and not B1);
>
>      C2 <= (A1 and B1 and not B0) or
>                    (A1 and not A0 and B1);
>
>      C3 <= A1 and A0 and B1 and B0;
>
> end Behavioral;
>
> **********************************************************

Your Entity and file name is "2bit".

I GUESS the problem is first character '2'.

Try alphabet at first.


Article: 82408
Subject: Ethnet samples using EDK??
From: "Chinix" <qx0103@gmail.com>
Date: 12 Apr 2005 05:18:20 -0700
Links: << >>  << T >>  << A >>
hello,
i am freshly learning using EDK now
and i want to try a simple webserver application
but i found the doc of EDK really confusing
could any kind guy provide me some examples of websever using edk

tools
or is there any website provides these examples?
it is really very kind of you if you could send some simple

applications to 
qx0103@gmail.com
Thanks a lot and a lot!


Article: 82409
Subject: Re: Ethnet samples using EDK??
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Apr 2005 14:18:35 +0200
Links: << >>  << T >>  << A >>
just get any reference design, there you find EDK examples for the webserver
demo
try memec reference design centre downloads and look also for the xilinx
ML401 ref designs

antti
http://gforge.openchip.org



"Chinix" <qx0103@gmail.com> schrieb im Newsbeitrag
news:1113308300.767079.166270@o13g2000cwo.googlegroups.com...
> hello,
> i am freshly learning using EDK now
> and i want to try a simple webserver application
> but i found the doc of EDK really confusing
> could any kind guy provide me some examples of websever using edk
>
> tools
> or is there any website provides these examples?
> it is really very kind of you if you could send some simple
>
> applications to
> qx0103@gmail.com
> Thanks a lot and a lot!
>



Article: 82410
Subject: Re: 2 bit multiplier
From: xiibweb@hotmail.com
Date: 12 Apr 2005 05:20:06 -0700
Links: << >>  << T >>  << A >>
thnx a lot... problem is solved


Article: 82411
Subject: Re: Global buffer feeding non clock pins in VIRTEX II
From: "Marc Randolph" <mrand@my-deja.com>
Date: 12 Apr 2005 06:13:09 -0700
Links: << >>  << T >>  << A >>

g. giachella wrote:
> In my design (in a Virtex II) there are 2 clocks, each of them on
> global buffer and feeding 2 sets  of distinct registers (block A and
> block B). The clocks then feed a clock switching circuit (not a
> BUFGMUX) and the resulting clock feeds another part of the design
> (block C).
[...]
> I suppose this message warns about a potentially unacceptable skew
> between blocks A/B and block C , but the skew inside block A or block
> B is still guaranteed to be low.
>
> Am I right ?

Howdy,

Depending on how you are getting signals between blocks A/B and C,
there is the potential for trouble - but the MUCH bigger problem is
that you will have unacceptable skew *within* block C.  Unless you
floorplan the flops within block C (and do so VERY intelligently),
you're asking for trouble.  Even if you do the muxing with LUTs, send
the output of the LUT to a global clock.

And yes, the skew within blocks A and B should be fine.

   Marc


Article: 82412
Subject: Re: problem in driving I2C bus through memory-mapped register
From: Will <will_munns@iname.com>
Date: 12 Apr 2005 13:45:20 GMT
Links: << >>  << T >>  << A >>
shankar.vk@gmail.com wrote in
news:1113222190.466570.106750@l41g2000cwc.googlegroups.com: 

> As I  said, the memory access works through jtag debugger 
> Trace32. 
> 
> What is the difference in execution flow of   memory access
> through debugger
> command and  software instruction ?  This is the key  to
> solve this problem.

stepping the code will cause a drain of the write buffer on 
every instruction to syncronize 'memory', Your first post has 
expired here - so I don't know what core you are using. Is the 
write buffer coelessing?

Article: 82413
Subject: Re: How do I disable Microblaze on-chip hw debug
From: John <nospam.nospam@nospam.com>
Date: Tue, 12 Apr 2005 16:01:14 +0200
Links: << >>  << T >>  << A >>

I feel more and more stupid here, because I cannot figure this out. I have  
now followed your steps but still no running microblaze.

These are the steps I am following:
First I build a XPS system, then I export this. I do some modification to  
the system_stub.vhd with regard to instatiated buffers then I run a P&R  
with other VHDL. Finally I import the result into XPS.

I have "Mark to Initialize BRAMs" set then I run update bitstream (as you  
said). I download the resulting bit file using IMPACT. The VHDL part of  
the system is running but the microblaze seems to be stuck. Something I  
miss now?






På Tue, 12 Apr 2005 13:02:15 +0200, skrev Antti Lukats  
<antti@openchip.org>:





-- 
Sendt med M2 - Operas revolusjonerende e-postprogram:  
http://www.opera.com/m2/

Article: 82414
Subject: Re: How do I disable Microblaze on-chip hw debug
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Apr 2005 16:07:58 +0200
Links: << >>  << T >>  << A >>
"John" <nospam.nospam@nospam.com> schrieb im Newsbeitrag
news:opso4g8cafg6mgav@visitech-jd.visitech.local...
>
> I feel more and more stupid here, because I cannot figure this out. I have
> now followed your steps but still no running microblaze.
>
> These are the steps I am following:
> First I build a XPS system, then I export this. I do some modification to
> the system_stub.vhd with regard to instatiated buffers then I run a P&R
> with other VHDL. Finally I import the result into XPS.

you should never edit the system_stub.vhd, there is no need also

and its better not to import export but have the ISE project as main and
include the XPS system as submodule in the ISE project

> I have "Mark to Initialize BRAMs" set then I run update bitstream (as you
> said). I download the resulting bit file using IMPACT. The VHDL part of
> the system is running but the microblaze seems to be stuck. Something I
> miss now?

No, dont think so, if the BRAMs are at absolute address 000000 and they are
initialized then microblaze should start

antti

>
>
>
> På Tue, 12 Apr 2005 13:02:15 +0200, skrev Antti Lukats
> <antti@openchip.org>:
>
>
>
>
>
> -- 
> Sendt med M2 - Operas revolusjonerende e-postprogram:
> http://www.opera.com/m2/



Article: 82415
Subject: 5V PCI interface
From: "Dr Justice" <sorry@no.spam.wanted>
Date: Tue, 12 Apr 2005 16:12:24 +0200
Links: << >>  << T >>  << A >>
Hi!

I'm making a PCI card which currently has the Xilinx Spartan-II
designed in beacuse of its ability to interface directly to the 5V bus.

I notice that the Spartan-II has partly disappeared from the Xilinx site,
as in hard to find (not longer listed amongst their FPGA products)
and not available in their online shop anymore.

I strikes me that "the world" really needs a 5V capable device,
and that it's just a bit strange that a major manufacturer decides
to no longer make devices that has 5V support. It is likely that
this capability will be useful for another few tens of years.

Of course there are level converters and that is probably the obvious
solution. However, that seems inelegant, and they bring in a new set
of problems, such as increased cost and complexity and increased
set up and hold times etc.. Also there seems to not be a particularily
good selection of level converters.

Thus I have two questions:

1.
How do you go about building FPGA based PCI cards, or indeed
anything that needs to interface to 5V; What's your favourite
device (family) for this? Do you use level converters, if so which ones?

2.
I'd prefer that the parts we end up with will be easily available
in small quantities for the next 4 or 5 years.
Does that make the Spartan-II a bad choice?

Any advice will be appreciated - thanks!

DJ
--



Article: 82416
Subject: Re: xapp134 on sdram controllers: @ bits reordering?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 12 Apr 2005 15:34:29 +0100
Links: << >>  << T >>  << A >>
robertp <robertp@wyig.com> writes:

> In this design, and in others I've seen around, the bank bits are MSB.
> 
> What would you think about reordering address bits, so that MSB are
> plugged to row bits: the idea is to avoid the ACTIVE command latency,
> because MSB [so row bits] are less likely to change.

Depending on your access pattern, this might help.

IIRC the SHARC DSP has the option to do this...

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 82417
Subject: Re: How do I disable Microblaze on-chip hw debug
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Tue, 12 Apr 2005 16:39:13 +0200
Links: << >>  << T >>  << A >>
If you choose for import, do you choose the right .bmm file? It should be 
something like system_stub_bd.bmm. If you choose the wrong one, your 
microblaze won't run.

Frank


"John" <nospam.nospam@nospam.com> wrote in message 
news:opso4g8cafg6mgav@visitech-jd.visitech.local...
>
> I feel more and more stupid here, because I cannot figure this out. I have 
> now followed your steps but still no running microblaze.
>
> These are the steps I am following:
> First I build a XPS system, then I export this. I do some modification to 
> the system_stub.vhd with regard to instatiated buffers then I run a P&R 
> with other VHDL. Finally I import the result into XPS.
>
> I have "Mark to Initialize BRAMs" set then I run update bitstream (as you 
> said). I download the resulting bit file using IMPACT. The VHDL part of 
> the system is running but the microblaze seems to be stuck. Something I 
> miss now?
>
>
>
>
>
>
> På Tue, 12 Apr 2005 13:02:15 +0200, skrev Antti Lukats 
> <antti@openchip.org>:
>
>
>
>
>
> -- 
> Sendt med M2 - Operas revolusjonerende e-postprogram: 
> http://www.opera.com/m2/ 



Article: 82418
Subject: Re: Ethnet samples using EDK??
From: "wonttellyahere" <ituccc@yahoo.com>
Date: 12 Apr 2005 07:41:39 -0700
Links: << >>  << T >>  << A >>
Any idea how to access memec reference design center without a "kit
serial number"? If buying a kit, can I access to the resouces only
related to the kit, or all the design resources at the center? Thanks a
lot!

Antti Lukats wrote:
> just get any reference design, there you find EDK examples for the
webserver
> demo
> try memec reference design centre downloads and look also for the
xilinx
> ML401 ref designs
>
> antti
> http://gforge.openchip.org
>
>
>
> "Chinix" <qx0103@gmail.com> schrieb im Newsbeitrag
> news:1113308300.767079.166270@o13g2000cwo.googlegroups.com...
> > hello,
> > i am freshly learning using EDK now
> > and i want to try a simple webserver application
> > but i found the doc of EDK really confusing
> > could any kind guy provide me some examples of websever using edk
> >
> > tools
> > or is there any website provides these examples?
> > it is really very kind of you if you could send some simple
> >
> > applications to
> > qx0103@gmail.com
> > Thanks a lot and a lot!
> >


Article: 82419
Subject: Re: Ethnet samples using EDK??
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Apr 2005 16:49:29 +0200
Links: << >>  << T >>  << A >>
"wonttellyahere" <ituccc@yahoo.com> schrieb im Newsbeitrag
news:1113316899.943287.299030@z14g2000cwz.googlegroups.com...
> Any idea how to access memec reference design center without a "kit
> serial number"? If buying a kit, can I access to the resouces only
> related to the kit, or all the design resources at the center? Thanks a
> lot!

you can buy the cheapest kit and you will get access to all the reference
desingns.
its an valuable resource.

antti
I might have some unused serial numbers as I have many boards, but I dont
think I find them so can not directly help with the rdc access


> Antti Lukats wrote:
> > just get any reference design, there you find EDK examples for the
> webserver
> > demo
> > try memec reference design centre downloads and look also for the
> xilinx
> > ML401 ref designs
> >
> > antti
> > http://gforge.openchip.org
> >
> >
> >
> > "Chinix" <qx0103@gmail.com> schrieb im Newsbeitrag
> > news:1113308300.767079.166270@o13g2000cwo.googlegroups.com...
> > > hello,
> > > i am freshly learning using EDK now
> > > and i want to try a simple webserver application
> > > but i found the doc of EDK really confusing
> > > could any kind guy provide me some examples of websever using edk
> > >
> > > tools
> > > or is there any website provides these examples?
> > > it is really very kind of you if you could send some simple
> > >
> > > applications to
> > > qx0103@gmail.com
> > > Thanks a lot and a lot!
> > >
>



Article: 82420
Subject: Re: State of MAX7000S I/O pins before programming
From: ajholme@hotmail.com
Date: 12 Apr 2005 08:11:23 -0700
Links: << >>  << T >>  << A >>

Ben Twijnstra wrote:
> Hi Andrew Holme,
>
> > In the MAX7000S datasheet, it says the I/O pins are tri-stated and
> > (weakly)
> > pulled-up, to avoid board conflicts, during programming.  What
should the
> > state of the I/O pins be _before_ programming?  I have a sample
EPM7128S
> > device here which appears to be pulling them low - but it also
fails the
> > blank test, so I think it must have been programmed.  How should a
> > brand-new part behave?
>
> There's some internal bit in the MAX7000A and later that says that
the
> device contains a valid configuration. If this bit is not set, the
device
> remains in tristate. In the MAX7000S, this bit is not present, but if
the
> device is blank, it should still stay in slightly-pulled-up-tristate.
>
> Only if the device is not blank (this does _not_ mean that it has a
_valid_
> configuration), it will go out of tristate and do something.

Thanks.

> Blank that sample and see what happens ;-)

How do I do that?  Is there an option in Quartus for this?  I couldn't
see anything ....


Article: 82421
Subject: Re: 5V PCI interface
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 12 Apr 2005 08:12:27 -0700
Links: << >>  << T >>  << A >>
Dr,

Spartan 2 will be around a long time.  That we have demoted it from the 
limelight is a marketing issue (just so much shelf space for the new 
products to showcase).

As you may be aware, we still provide the 3100A series of FPGAs, which 
are still supporting designs done 15 years ago!

We discontinue devices once they are not able to be manufactured and 
sold economically.  This means that there is little business, and the 
process used to make the chips has become obsolete at the fabrication 
facilities.  We also may discontinue a particular part/package 
combination when that package is running at extremely low volumes or 
becomes difficult to procure.

Since we are still making almost all of our FPGA products, I don't think 
you have anything to worry about with Spartan II.

The original Virtex, and Spartan II are a lot like classic Coca-Cola -- 
they may never go away.

However, the cost/function of newer devices is so much better than the 
older devices, that you may want to consider designing with the latest 
devices (at some point).

The app notes we have published for 5V PCI details all of the tricks to 
make the latest 90nm devices work on the 5V PCI bus. (Xapp 646, 311)

I hope this helps,

Austin

Article: 82422
Subject: Re: State of MAX7000S I/O pins before programming
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Tue, 12 Apr 2005 15:30:20 GMT
Links: << >>  << T >>  << A >>
Hi Andrew,

>> Blank that sample and see what happens ;-)
> 
> How do I do that?  Is there an option in Quartus for this?  I couldn't
> see anything ....

Wups... I don't have an actual EPM7128S device lying around here, but from
the command line try "quartus_pgm --operation=R". If you need more help,
type "quartus_pgm --help=operation".

Best regards,



Ben


Article: 82423
Subject: Re: 5V PCI interface
From: "Dr Justice" <sorry@no.spam.wanted>
Date: Tue, 12 Apr 2005 18:13:56 +0200
Links: << >>  << T >>  << A >>
Austin,

thanks a lot for your reply - that was most reassuring,
and I got both questions answered!

> The original Virtex, and Spartan II are a lot like classic Coca-Cola -- 
> they may never go away.

That's kind of what I was hoping for :-)

> The app notes we have published for 5V PCI details all of the tricks to
> make the latest 90nm devices work on the 5V PCI bus. (Xapp 646, 311)

I have overlooked said application note - shall download it at once
and study it carefully. Anyway it's good to know that the Spartan-II
will remain in production.

Regards,

DJ
--




Article: 82424
Subject: Re: running microblaze from bram through OPB-bus
From: Paul Hartke <phartke@Stanford.EDU>
Date: Tue, 12 Apr 2005 09:32:32 -0700
Links: << >>  << T >>  << A >>
Yes.  

Frank van Eijkelenburg wrote:
> 
> Thanks for the answers. So it shouldn't give any problems.
> 
> I assume that having only the LMB bus, will still allow me to divide the
> code into a bootloader and application part. And to download the application
> into a reserved address range in the BRAM?!
> 
> Frank
> 
> "Paul Hartke" <phartke@Stanford.EDU> wrote in message
> news:42569481.C1817F26@Stanford.EDU...
> > No problem having both LMB and OPB BRAM visible to the same processor as
> > long as the addresses are not overlapping as indicated in the original
> > post.
> >
> > I agree that LMB is likely preferred if the Microblaze is the only
> > entity to access the memory space.  OPB BRAM might be needed if other
> > peripherals require access to the memory such as a DMA engine.
> >
> > Paul
> >
> > Aurelian Lazarut wrote:
> >>
> >> Frank,
> >> why not having the whole bram (sum of your LMB and OPB) attached to LMB
> >> only? how is helping you if you have two mems on different buses? (OBP
> >> can get slow if you have to many peripherals...)
> >> Aurash
> >>
> >> Frank van Eijkelenburg wrote:
> >>
> >> >Hi,
> >> >
> >> >We have a design with a microblaze which runs from bram at startup
> >> >(connected through the LMB bus). After startup it is possible to
> >> >download an
> >> >application to sdram (connected through the OPB bus) and run from sdram.
> >> >Since we are going to change the fpga type and get a lot more brams
> >> >available; we are thinking to remove the sdram (to reduce costs) and
> >> >replace
> >> >it by bram.
> >> >
> >> >My question is: is it possible to have a microblaze with bram connected
> >> >to
> >> >the LMB bus and a seperate bram connected to the OPB bus and have
> >> >different
> >> >programs in the brams (a bootloader in de bram which is connected to the
> >> >LMB
> >> >bus, and an application downloaded at runtime in the bram which is
> >> >connected
> >> >to the OPB bus) and run both of them (not at the same time of course)?
> >> >
> >> >As far as I can see, it doesn't matter what kind of memory is used for
> >> >the
> >> >application (bram or sdram) as long as the code is built to run from the
> >> >correct addresses. Can anyone confirm this and/or has experience with
> >> >this?
> >> >
> >> >Thanks in advance,
> >> >Frank
> >> >
> >> >
> >> >
> >> >
> >>
> >> --
> >>  __
> >> / /\/\ Aurelian Lazarut
> >> \ \  / System Verification Engineer
> >> / /  \ Xilinx Ireland
> >> \_\/\/
> >>
> >> phone:  353 01 4032639
> >> fax:    353 01 4640324
> >>
> >>



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search