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Messages from 84225

Article: 84225
Subject: Re: FPGA design under Mac OS X ?
From: "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com>
Date: Sun, 15 May 2005 07:54:38 -0400
Links: << >>  << T >>  << A >>
On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote:

> Are there any FPGA design tools which will run under Mac OS X?
> 
> I've found that the Icarus Verilog simulator and synthesis tool
> will run under OS X, but I'm not sure whether that's actually useful
> for programming any current FPGA part.
> 
> Thanks.

Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your
FPGA development environment. You can use the Mac as an X-Server, but
thats as close as you are going to be able to get. It's inconceivable that
the FPGA or CAE companies would add a third platform.  

Article: 84226
Subject: Serial communication
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Sun, 15 May 2005 16:44:05 +0200
Links: << >>  << T >>  << A >>
Hello,

I have a system composed of a Cyclone device and an
8051-like CPU, which acts as a passive-serial configuration
device and later as a USB2.0 coupler. The FPGA
configuration image is clocked to Cyclone using the UART 
interface (synchronous mode 0, i.e. TXD acts as DCLK
and RXD presents one bit at a time to the DATA0 pin).
There are also two inverters at these lines: the first one
inverts DCLK, because Cyclone uses the opposite edge
than '51 to latch a configuration bit.  The second inverter
(at RXD -> DATA0) relaxes timing constraints by compensating
the delay introduced by DCLK inversion. 

Now I would like to reuse resources and add a serial
synchronous communication channel between Cyclone
and '51, where Cyclone acts as a slave device. So, is
it possible to read DCLK and DATA0 from an operating
Cyclone, i.e. to simulate an ASMI-like interface?

    Best regards
    Piotr Wyderski


Article: 84227
Subject: Re: floorplanning
From: Lukasz Salwinski <lukasz@ucla.edu>
Date: Sun, 15 May 2005 08:14:43 -0700
Links: << >>  << T >>  << A >>
wow.. quite a flood of comments ;o)

Phil Hays wrote:

> For the second case, my most recent design is fairly low speed, ~50
> MHz in a Spartan-3.  At one point in time, I was getting a timing
> failure on a BlockRam -> some data path logic -> multiplier path.  The
> only reason why this was failing was that the automatic placement put
> the BlockRam in one corner of the part and the multiplier in the far
> corner of the part.  I'm not sure why the tools have such problems
> with the large blocks, but my experience is that the automatic
> placement of BlockRams and multipliers is often poor.  The cure was
> simple: I fixed placed all the BlockRams and multipliers to something
> reasonable.  I've also seen cases where, to meet timing, a LUT or FF
> had to be in a specific location or a few specific locations.  The
> automatic placement would often get close, but close wasn't good
> enough.

exactly my experience - especially with large FPGAs when most BRAMs
(or presumeably other coarse-grain elements are used). once you fix
position of those the rest seems to fall in place much easier. one
can figure out what and where to fix after a few trial runs. and it
seems to be more effective than constraining critical paths.
dealing with LUT placement seems to be a mess - especially after
havoc wreaked by synthesis tool optimizations ;o)

the problem is these trial runs/experience thing makes it black art-
like. too bad noone bothered to write up the experiences gathered
while trial running...

anyways, thansk to all for responses ;o)

lukasz

Article: 84228
Subject: Re: floorplanning
From: Phil Hays <Spampostmaster@comcast.net>
Date: Sun, 15 May 2005 09:13:48 -0700
Links: << >>  << T >>  << A >>
Lukasz Salwinski wrote:

>exactly my experience - especially with large FPGAs when most BRAMs
>(or presumeably other coarse-grain elements are used). once you fix
>position of those the rest seems to fall in place much easier.

I'd like to add a reasonable pinout to that.


>dealing with LUT placement seems to be a mess - especially after
>havoc wreaked by synthesis tool optimizations ;o)

Before trying LUT placement, try register placement.  Register names
are more much stable.  And again, with the registers correctly placed
the rest can fall into place neatly.

To do LUT placement, the best way I've seen to do this is to prevent
synthesis optimization by putting the logic for the LUT into an entity
and putting the correct attribute on it.  Then you can instantiate and
place it with a generate loop in VHDL.


--
Phil Hays
Phil-hays at posting domain (- .net + .com) should work for email


Article: 84229
Subject: Re: floorplanning
From: Paul Boven <p.boven@chello.nl>
Date: Sun, 15 May 2005 23:58:13 +0200
Links: << >>  << T >>  << A >>
Hi JJ, everyone,

JJ wrote:
> I forgot to say that manual design is inherantly bottom up design which
> means you assemble objects and see their interactions as you edit them
> even if the logic is incomplete. The tools should not care as long as
> you believe the logic is correct.
> 
> But the FPGA layout tools don't like that, they insist on a complete
> design that interferes with what you are trying to accomplish.
> 
> I have been fighting this battle for 20+ years with EDA writers, they
> don't use their own tools the way some of us would wish, only in the
> proscribed way. At one time I did IC mask layout and had no way to turn
> DRC off which is like driving around with a cop in your passenger seat,
> only much worse!

Being from the 'hey, I just got my Spartan 3 kit' subgroup, I can hardly 
boast 20+ years of battles with, well, anything. But so far I've been 
doing al my designing trough schematic entry, and seeing how it gets 
routed/placed has been quite surprising. And the thing I'm developping 
right now has very tight timing requirements so I end up placing all the 
  important flip-flops by hand and wishing I could also control what 
kind of interconnect gets used.

> I wonder how much demand there would be for a realy slick and
> commercial FPGA layout tool that had at least a basic model of the LUTs
> and wiring delays that could be correlated with actual devices. I have
> some ideas on this but other projects come 1st.

Having studied the datasheet quite well before getting into this, it is 
a lot easier for me to map a desired circuit into FFs, LUTs and the 
like. Learning VHDL or even using the schematic editor, feels like a 
terribly involved way to convince the software to configure those LUTs 
the way I want them. So yes, I can imagine some demand for a FPGA layout 
tool that stays this close to the hardware. But 'realy slick and 
commercial' probably would put it out of my reach.

Regards, Paul Boven.

Article: 84230
Subject: Universal logic modules vs NAND-like modules
From: "Candida Ferreira" <cferreira@seehomepage.com>
Date: Sun, 15 May 2005 22:09:53 GMT
Links: << >>  << T >>  << A >>
Hi everyone,

Is there a proper name to distinguish NAND-like universal modules from
ordinary ones, that is, the ones formed by a function F, plus NOT, plus ONE,
and ZERO?

Thanks,
Candida
---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp

GEP: Mathematical Modeling by an Artificial Intelligence
http://www.gene-expression-programming.com/gep/Books/index.asp
Modeling Software
http://www.gepsoft.com/gepsoft/
                          Get APS 3.0 Std free with the book!




Article: 84231
Subject: Re: Update Picoblaze Code in Bitstream
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 16 May 2005 09:00:59 +1000
Links: << >>  << T >>  << A >>
Hi Michael,

Michael Dreschmann wrote:
> in my actual design im using a few picoblazes. Now I wonder if it is
> possible to update the code in the bitstream without a new
> implementation run like it is possible with the microcblaze. I checked
> data2bram but it allows only an update of 16 Bit wide Brams, not the
> necessary 18 Bit.

The following may be of interest to you (full-text PDF available from 
the link):

http://eprint.uq.edu.au/archive/00002080/

Programmable Parallel Coprocessor Architectures for Reconfigurable 
System-on-Chip.

Williams, John A. and Bergmann, Neil W. (2004)

We propose a hybrid rSoC parallel processing architecture consisting of 
a central 32-bit RISC microprocessor interconnected to an array of 8-bit 
microcontrollers as coprocessing nodes. The central processor runs an 
embedded Linux operating system, with the coprocessor nodes mapped into 
a virtual file system, by which they can be controlled and reprogrammed. 
The hardware and software architectures are detailed, and several useful 
application contexts are proposed. Supporting theoretical analysis is 
also presented.

Regards,

John

Article: 84232
Subject: Re: microblaze and 64 bit memory over PLB bus
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 16 May 2005 09:05:55 +1000
Links: << >>  << T >>  << A >>
Hi Antti,

Antti Lukats wrote:

> anyone has made it own microblaze soc (eg not using ML401 derivate) where
> PLB is connected to microblaze OPB over bridge and some peripherals live on
> the PLB bus? I am struggling with this and can find the problem, for testing
> I just connected PLB GPIO, it seems to be kind of visible over OPB2PLB
> bridge, but there is defenetly any writes working :(
> 
> This can be done and is used in ML401 ref design, but there seem to be some
> 'special gotchas' that one has to know to make it work, so if anyone had
> some problem with similar design and has some hints I would be extremly
> thankful

I'm not quite understanding you here - what "gotchas" are you 
describing?  I was able to easily modify the ML401 reference design for 
example to make it uClinux-capable, there were no tricks there.  The PLB 
bus had the DDR controller and Xilinx TFT VGA controller.  Adding 
another core on the PLB bus is simple.

One thing to note, that design is very very tight on timing at 100MHz. 
I did have trouble meeting timing when I started adding and moving cores 
around in the system.  Is that what you are talking about?

Regards,

John

Article: 84233
Subject: Re: Update Picoblaze Code in Bitstream
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 16 May 2005 12:01:01 +1200
Links: << >>  << T >>  << A >>
John Williams wrote:
> Hi Michael,
> 
> Michael Dreschmann wrote:
> 
>> in my actual design im using a few picoblazes. Now I wonder if it is
>> possible to update the code in the bitstream without a new
>> implementation run like it is possible with the microcblaze. I checked
>> data2bram but it allows only an update of 16 Bit wide Brams, not the
>> necessary 18 Bit.
> 
> 
> The following may be of interest to you (full-text PDF available from 
> the link):
> 
> http://eprint.uq.edu.au/archive/00002080/
> 
> Programmable Parallel Coprocessor Architectures for Reconfigurable 
> System-on-Chip.
<snip>

Impressive.
Did you look at data links between the PicoBlaze units ? - that would
further off-load the main CPU, and ease situations where a single
task proved too much for one Picoblaze ?
-jg


Article: 84234
Subject: Re: Input Maximum Delay timing assignment in Altera (Delay settings in Quartus)
From: "Subroto Datta" <sdatta@altera.com>
Date: Mon, 16 May 2005 00:53:07 GMT
Links: << >>  << T >>  << A >>
Here is some more detail and information on the Input Max Delay/Min Delay 
for the benefit of other readers of this newsgroup:

You can just type "In" and you will see the Assignment Editor quickly show 
all assignments that start with "In". The second one in the drop down should 
be "Input Maximum Delay" and third is "Input Minimum Delay". You need to 
enter both a "From" and "To" node, where "From" represents your clock 
reference and the "To" represents the input pin name. Both fields accept 
wildcards and/or timegroups



If you want to go directly to the QSF file, you can enter:



    set_instance_assignment -from <your clk> -to <your pin> -name 
INPUT_MAX_DELAY <value>

    set_instance_assignment -from <your clk> -to <your pin> -name 
INPUT_MIN_DELAY <value>



Or if you use Tcl scripting, type



    set_input_delay -max/-min -clk_ref <your clk> -to <your pin> <value>

in the Quartus Tcl console (View->Utility Windows->Tcl Console) or in the 
quartus_sh Tcl prompt. quartus_sh is lauched from the command line or DOS 
box. Make sure that the quartus\bin is on your path where quartus quartus 
represents the path to the Quartus Installation directory.



For more on the Tcl command, use "quartus_sh --qhelp" and look at the 
"project" Tcl package.



Output Delays

-------------------

Also note you can do the same for output pins, and use "Output 
Maximum/Minimum Delay" (Tcl: set_output_delay) instead of "Tco/Min Tco" 
requirements.



What do these delays represent

---------------------------------------

If you have an ASIC background, you will recognize this type of constraints 
as most EDA tools use them. They represent the external delay on your board. 
A simplistic way to see this is that "Input Max/Min Delay" represents the 
"Tco/Min Tco" of the chip feeding the FPGA plus the board delay, while 
"Output Max/Min Delay" represents the "Tsu/Th" of the chip fed by the FPGA 
plus the board delay. These assignments tell the Quartus II Timing Analyzer 
to basically consider the pins as registers and do simple register to 
register analysis. This means that you can use Multicycle, Clock 
Uncertainty, and other features on your I/O paths.



If you want to use this methodology and you have PLLs, you may want to 
consider upgrading to V5.0. In this release, we introduce "Clock Latency" 
and for PLLs, we automatically create this clock latency based on the PLL's 
compensation delay. The advantage of using Clock Latency is that you avoid 
having to define Multicycle assignments in some cases, so it is a lot easier 
to use. You have to enable the feature from the "Timing Settings" Dialog 
box. Click on the "More Settings" and then turn on "Enable Clock Latency" 
(Tcl/Qsf: "set_global_assignment -name ENABLE_CLOCK_LATENCY ON").



For more on these features, search for "input_max_delay", "output_max_delay" 
or "clock latency".



Hope this helps,

Subroto Datta

Altera Corp.


"Subroto Datta" <sdatta@altera.com> wrote in message 
news:Qpche.2253$j17.947@newssvr33.news.prodigy.com...
> Click on the Assignment Editor->Timing button which is in the upper right 
> corner. This will show only timing related assignment names in the 
> Assignment Name field in the table below. You will have to fill in the 
> From and To fields and the value needed.
>
> You can also use the All button in the upper right corner of the 
> Assignment Editor to obtain a list of every Assignment Name possible which 
> will include these Timing Assignment names also.
>
> Hope this helps.
> - Subroto Datta
> Altera Corp.
>
> <ALuPin@web.de> wrote in message 
> news:1115965745.611489.161920@g44g2000cwa.googlegroups.com...
> Where can I find this assignment type "Input max delay / input min
> delay"
> in the Assignment Editor?
>
> Rgds
> André
>
>
>
> 



Article: 84235
Subject: Re: Virtex4 running at 360Mhz DDR
From: "Brian Davis" <brimdavis@aol.com>
Date: 15 May 2005 19:28:11 -0700
Links: << >>  << T >>  << A >>
Austin,

 Which of the following posts regarding Cin is more helpful
for both Xilinx and its' customers:

Austin [1]:
>
> Use the internal one, and the capacitance does not matter
> (do the sim yourself if you do not believe me).
>

Brian [2]:
>
>    At no point have I claimed that the V2 inputs are unusable,
>  but only that, in the presence of high speed drivers, extra
>  engineering effort needs to be expended to both understand the
>  impact of the V2 input capacitance on the interconnect, and
>  find a work-around that is appropriate for the design at hand.
>

Austin wrote:
>
>When folks wave their arms and state 12.5pF is the LVDS load,
>they are miss-stating it.
>
 The only I/O capacitance number published in your datasheet is a
single-ended parameter called Cin (or if you prefer, C_comp from
the IBIS files).

Quoting this published datasheet Cin value is perfectly valid,
and does not require "correction".

 Comparing that number against the single ended Cin's of other
devices, or against a single ended spec, is also perfectly valid.

 I have never said the differential load is 12.5 pf; it is clear
from my posts that I understand this, and also understand that
the assumption of Cdiff_effective = 1/2 Cin_single_ended applies
only for the differential components of the signals on the Tline.

 I find it rather inconsistent that in past discussions of
Xilinx's newly onerous SSO limits for the current mode output
drivers, you've been quite insistent that real world paths are
NOT perfectly balanced-

 Yet when discussing the effects of high Cin, you posit that
everything is perfectly balanced back to a perfect source
termination, so that a 50-60% voltage reflection off of your
input pins is never a problem.

 If only all FPGA input buffers could live happily ever after
there in Austin's world, where all connections are ideal
differential point-point links, all drivers have perfect back
terminations, and no probing or multidrops are ever allowed.

>
>In communications theory, excess bandwidth in the channel only adds
>to the error rate (due to noise).  Some band limiting is a good thing.
>
 And massive, coherent input reflections do not fit the AWGN
assumptions of most channel models, now do they?

Brian

p.s. As for your other post, I'll reply once I finish recovering
from a hard drive crash at home and can find my old files again.

[1]
http://groups-beta.google.com/group/comp.arch.fpga/msg/57bbb3ea78e194ed?hl=en
[2]
http://groups-beta.google.com/group/comp.arch.fpga/msg/a044806f313848e6?hl=en


Article: 84236
Subject: Re: Update Picoblaze Code in Bitstream
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 16 May 2005 12:49:37 +1000
Links: << >>  << T >>  << A >>
Hi Jim,

Jim Granville wrote:
> John Williams wrote:
> 
>> Michael Dreschmann wrote:
>>
>>> in my actual design im using a few picoblazes. Now I wonder if it is
>>> possible to update the code in the bitstream without a new
>>> implementation run like it is possible with the microcblaze. I checked
>>> data2bram but it allows only an update of 16 Bit wide Brams, not the
>>> necessary 18 Bit.
>>
>>
>>
>> The following may be of interest to you (full-text PDF available from 
>> the link):
>>
>> http://eprint.uq.edu.au/archive/00002080/
>>
>> Programmable Parallel Coprocessor Architectures for Reconfigurable 
>> System-on-Chip.
> 
> <snip>
> 
> Impressive.
> Did you look at data links between the PicoBlaze units ? - that would
> further off-load the main CPU, and ease situations where a single
> task proved too much for one Picoblaze ?

No I didn't, however PicoBlaze interfacing is so simple that adding 
either direct-wired or buffered (FIFO) links between multiple Picos 
should be pretty straight forward.

We since have expanded the concepts in that paper to multi-microblaze 
systems - their native FSL interfaces make it trivial to connect them up 
to each other in arbitrary topologies, and also makes it easy to drop a 
bit of custom hardware in place of a CPU if you decide you need more 
performance or smaller logic utilisation.

BTW, the device driver developed for that work is in the public uClinux 
source tree, it's a generic uClinux driver for FSL peripherals.  So, you 
can interact with pretty much any FSL core from within uClinux, using 
intuitive open/read/write system calls, just like any other file/device.

Regards,

John

Article: 84237
Subject: Microblaze interrupt problem
From: fpga00@gmail.com
Date: 15 May 2005 20:57:24 -0700
Links: << >>  << T >>  << A >>
hello,

  I have a microblaze system with a uart and a timer (both produce
interrupt).The interrupts are handled by intc.Uart interrupt is the
highest priority followed by timer interrupt.
1. can microblaze read only the required data from the uart at a
time.like say i want to get a frame from uart i.e data from one flag to
another flag and then stop reading the bytes fro uart.When i tried
doing this i realised that I have to read the whole file that i am
transferring from the hyperterminal to the uart.but i dont want this to
happen.any suggestions?
2. if the above behavior is not possible then i can send just one frame
at a time to uart from the hyperterminal.if i do this the what happens
is that my timer is also running at the same time.when it expires it
interrupts the microblaze.But now if i send a frame to uart,it
interrupts microblaze and then i stop getting interrupts from the
timer.if i send another file (data) from hyperterminal to uart,it
interrupts the microblaze properly but the timer has stopped
working or otherwise its interrupt is not getting recognised.
I thought that probably when i am in the uart_int_handler probably my
timer interrupt was genearted and it was missed since i was in int.
routine.Is this a possibility.?is yes ,how can i avoid this?I want to
service the timer interrupt after i return fro the uart handler.my intc
driver does not have XIN_SVC_ALL_ISRS_OPTION defined.so it does not
allow me to use it in the code.
Please share some information regarding this problem.
Thank you all.


Article: 84238
Subject: wide ROM
From: "bxbxb3" <bxbxb3@yahoo.com>
Date: Mon, 16 May 2005 00:22:42 -0400
Links: << >>  << T >>  << A >>
Hi,
I want a ROM in FPGA which is 85 bits wide, is it possible to have one?
Thanks


Article: 84239
Subject: Re: DDR speed of the XUPV2P Board from Digilent
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 16 May 2005 15:33:33 +1000
Links: << >>  << T >>  << A >>
Hi Benjamin,

Benjamin Menküc wrote:

> I am looking too for reference designs. The guy from Digilent told me on 
> the phone, that they are waiting to receive the promised reference 
> designs from Xilinx, to put them on their homepage.
> 
> Maybe someone from Xilinx knows when they will be available.

I now have a preliminary version of a MicroBlaze-uClinux capable 
reference design, including EDK 7.1 project, bitstreams and kernel 
images, hosted on the MicroBlaze uClinux home page

http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

I call it preliminary because there is still a bit of tweaking to be 
done, however it should provide a good starting point for you to work 
with this excellent board.

Note the design was provided to on an "as-is" basis, so please do not 
contact Xilinx for support.  Actually I see that the Digilent site now 
has a lot more resources, including this same reference design:

http://www.digilentinc.com/info/XUPV2P.cfm

Regards,

John

Article: 84240
Subject: SPI interface cpol & cpha
From: praveen.kantharajapura@gmail.com
Date: 15 May 2005 22:41:52 -0700
Links: << >>  << T >>  << A >>
Hi all,

In SPI interface if i see there are two signals cpol and cpha, which
are used for differnet data transfer formats.
What i wanted to know is why 4 different data transfer formats have
been defined???
If both the master and slave  agreed  upon one format that shoud be
fine right.

Any suggestions are appreciated.

Thanks in advance,
Praveen


Article: 84241
Subject: Re: wide ROM
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 15 May 2005 23:01:23 -0700
Links: << >>  << T >>  << A >>
It depends. If you want 16-address depth, you can use 85 LUTs.
With Xilinx 18K BlockRAMs, you can get 256x72 bits wide in one
BlockRAM. For more, you need two BlockRAMs in parallel.
Peter Alfke, Xilinx (from home)


Article: 84242
Subject: Xilinx : Clock Swallowing
From: "Luke Darnell" <luke.darnell@g2microsystems.com>
Date: Mon, 16 May 2005 01:08:50 -0700
Links: << >>  << T >>  << A >>
Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example:

I input a 44MHz clock.

I generate a 22MHz clock with 25/75 duty cycle by gating every second 44MHz pulse.

How can I maintain the phase relationship between the new 22Mhz clock and the origianl 44MHz clock ??

All the clock divide options of the DCM's and PMCD's will have 50/50 duty cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock?

regards, Luke darnell

Article: 84243
Subject: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
From: "Geogle" <georgevarughese@indiatimes.com>
Date: 16 May 2005 01:09:06 -0700
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> Geogle <georgevarughese@indiatimes.com> wrote:
> > Uwe Bonnes wrote:
> > > Geogle <georgevarughese@indiatimes.com> wrote:
> > > > Hi,
> > >
> > > >   Does this "Free ISE WebPACK 7.1i" for linux work
> > > > with any distribution other than Red Hat Enterprise Linux 3 ?
> > > > I tried to install this under Fedora Core 3 / Debian and
> > > > installation didn't succeed. Looks like the installer is
> > > > linked against libwiclient.so, libcommdlg50.so ....
> > > > libodbc50.so etc, which are not there on the system.
> > >
> > > > Does anyone know which package provides these ?
> > >
> > > The webpac installer is in charge to install them. They are found
in
> > > ../bin/lin
>
> > Thanks, they are in the BIN area!
>
> > When I tried to install the software, I got the following message:
> > (  running setup from the extracted files/
> > and
> > sh Webpack*..sh yielded the same
> > result. )
> > Wind/U X-toolkit Error: ", 24Wind/U X-toolkit Error:
> > wuDisplay: Can\'t open display\n", 30wuDisplay: Can't open display
>
> Normally $DISPLAY is ":0.0" on the local host.
> Zillions of applications work with that setting. The "WINDU" library,
that
> Xilinx  uses for implementing a Win32 Library layer on *NIX however
doesn't
> understand it.
>
> Set it to ":0" and xilinx should start up.

I also found that gdmsetup (under security tab) could be used
to enable port 6000 (X) tcp/ip access.  It is disabled by
default when X is started from gdm.
When  enabled, default DISPLAY setup was acceptable to Xilinx.

Thanks for the help,
George


Article: 84244
Subject: Re: Xilinx : Clock Swallowing
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 16 May 2005 09:46:56 +0100
Links: << >>  << T >>  << A >>
As the saying goes there is more than one way to skin the cat. The DCM's 
will allow phase shift and multiplication. One way, and not the only way, is 
multiply your origional 44 MHz. If you then generate clock enables from a 
state machine / counter you can choose effectively different widths and 
phases that you want.

As a suggestion multiply the 44Mhz by 2 to 88MHz and that will give 4 phases 
of 22MHz to turn on, or off, as you like. The clock enable can be synched to 
the input using a sample of the 44MHz clock. If you want real clock signals 
you can use the state machine / counter outputs, or derived functions, but 
be careful of routing timing skews. However this technique does work well if 
it is external clocks you are generating and you use the I/O cell flip-flop 
to generate the final output.

John Adair
Enterpoint Ltd. - Home of MINI-CAN. Low Cost Spartan-3 PCI Development 
Boards.
http://www.enterpoint.co.uk


"Luke Darnell" <luke.darnell@g2microsystems.com> wrote in message 
news:ee8e47d.-1@webx.sUN8CHnE...
> Our current design uses clock swallowing to obtain lower frequency clocks. 
> I'd like to implement this clocking behaviour (while still maintaining the 
> phase relationahip between the clocks) inside a VIRTEX4 but don't know if 
> this is possible. For example:
>
> I input a 44MHz clock.
>
> I generate a 22MHz clock with 25/75 duty cycle by gating every second 
> 44MHz pulse.
>
> How can I maintain the phase relationship between the new 22Mhz clock and 
> the origianl 44MHz clock ??
>
> All the clock divide options of the DCM's and PMCD's will have 50/50 duty 
> cycle outputs. Is there no method of obtaining a divided phase aligned non 
> 50/50 duty cycle clock?
>
> regards, Luke darnell 



Article: 84245
Subject: Re: floorplanning
From: "Neo" <zingafriend@yahoo.com>
Date: 16 May 2005 02:40:31 -0700
Links: << >>  << T >>  << A >>
In same line though slightly off topic. are there still schematic based
design being done (other than FSMs) and what tools do they use?


Article: 84246
Subject: Re: Universal logic modules vs NAND-like modules
From: "JJ" <johnjakson@yahoo.com>
Date: 16 May 2005 02:46:50 -0700
Links: << >>  << T >>  << A >>
Question doesn't make sense to me.

Try again or pick up a logic book.

Maybe you refer to fixed logic v tablelogic?

So what brings someone in your esteemed field down into the hw
trenches.

johnjakson at usa dot com


Article: 84247
Subject: Re: Universal logic modules vs NAND-like modules
From: "Candida Ferreira" <cferreira@seehomepage.com>
Date: Mon, 16 May 2005 10:03:10 GMT
Links: << >>  << T >>  << A >>
NAND and NOR functions by themselves can be used to describe any other
function, including NOT, ZERO and ONE. But, for instance, the 3-multiplexer,
which is also by definition an ULM, can not by itself describe a NAND gate
as it is unable to create a NOT gate. But there are other functions that
behave exactly like NAND or NOR gates in the sense that, by themselves, they
can also describe any other function. Do such functions have a name? I think
there is something special about them and I would like to distinguish them
from the ordinary ULMs.

Candida
---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp

GEP: Mathematical Modeling by an Artificial Intelligence
http://www.gene-expression-programming.com/gep/Books/index.asp
Modeling Software
http://www.gepsoft.com/gepsoft/
                          Get APS 3.0 Std free with the book!


"JJ" <johnjakson@yahoo.com> wrote in message
news:1116236810.947060.102680@o13g2000cwo.googlegroups.com...
> Question doesn't make sense to me.
>
> Try again or pick up a logic book.
>
> Maybe you refer to fixed logic v tablelogic?
>
> So what brings someone in your esteemed field down into the hw
> trenches.
>
> johnjakson at usa dot com
>



Article: 84248
Subject: Re: SPI interface cpol & cpha
From: "Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org>
Date: Mon, 16 May 2005 20:57:45 +1000
Links: << >>  << T >>  << A >>

<praveen.kantharajapura@gmail.com> wrote in message
news:1116222112.170736.96770@g43g2000cwa.googlegroups.com...
> Hi all,
>
> In SPI interface if i see there are two signals cpol and cpha, which
> are used for differnet data transfer formats.
> What i wanted to know is why 4 different data transfer formats have
> been defined???
> If both the master and slave  agreed  upon one format that shoud be
> fine right.
>
> Any suggestions are appreciated.
>
> Thanks in advance,
> Praveen
>
Hi Praveen,

Right, if you control both the master and the slave you need only one
format, I'd suggest the default cpol = cpha = 0.  However some of us are not
so lucky and must interface with pre-existing real world devices which,
through the perversity of history, can be hard-wired for any of the four
formats.  No use saying it doesn't need to be so, it simply is so.  The fun
begins when you have a mixture of devices using different cpol & cpha
values.

hth,
Alf



Article: 84249
Subject: Re: SPI interface cpol & cpha
From: praveen.kantharajapura@gmail.com
Date: 16 May 2005 04:33:00 -0700
Links: << >>  << T >>  << A >>
Hi,

Any particular reason for suggesting cpol=cpha= '0'.

In some of the docs i have read that cpha='1' is generally suited for
single master single slave applications , i am not able to figure out
why??
Any comments on this!!

Thanks in advance,
Praveen




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