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Messages from 85500

Article: 85500
Subject: Re: Building a MicroBlaze from scratch, unable to run.
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Fri, 10 Jun 2005 13:21:29 +0100
Links: << >>  << T >>  << A >>
Check if your reset is active high of low (design against the board) and 
consistent for all the BUSes (cores)
Aurash
Raymond Bakken wrote:

>Hi
>
>I am using a spartan3 development board and trying to learn about
>MicroBlaze.
>
>My application is simple, I want the bitpattern at the slideswitches
>to appear on the leds (The board has 8 slideswitches and 8 leds).
>
>If I use the BSB to create my MicroBlaze it works fine.
>the modules (in Add/Edit cores) the BSB create/use is:
>microblaze         4.00.a    microblaze_0
>opb_mdm            2.00.a    debug_module
>lmb_bram_if_cntrl  1.00.b    dlmb_cntlr
>lmb_bram_if_cntrl  1.00.b    ilmb_cntlr
>bram_block         1.00.a    lmb_bram
>opb_gpio           3.01.b    LEDs_8Bit
>opb_gpio           3.01.b    DIP_Switches_8Bit
>dcm_module         1.00.a    dcm_0
>
>If I make one from scratch it doesn't work.
>the module (in Add/Edit cores) I create/use is:
>lmb_bram_if_cntrl  1.00.b    i_bram
>lmb_bram_if_cntrl  1.00.b    d_bram
>bram_block         1.00.a    bram
>opb_gpio           3.01.b    Switch
>microblaze         4.00.a    MyProsessor
>opb_gpio           3.01.b    Leds
>dcm_module         1.00.a    dcm_0
>
>and my c-code is simple (used on both):
>#include "xparameters.h"
>#include "xgpio_l.h"
>
>
>
>int main()
>{
>	unsigned char ucData;	
>	while(1)
>	{
>                // read from slide switches.
>		ucData = XGpio_mGetDataReg(SWITCH BASEADDR, 1);
>                // put value in LEDs
>		XGpio_mSetDataReg(LEDS BASEADDR, 1, ucData);
>	}	
>	return 0;
>}
>
>The BASEADDR are from the headers xparameters.h in the respective
>projects.
>
>BSBs ucf file look like this:
>Net sys_clk_pin LOC=T9;
>Net sys_rst_pin LOC=l14;
>## System level constraints
>Net sys_clk_pin TNM_NET = sys_clk_pin;
>TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
>Net sys_rst_pin TIG;
>
>## FPGA pin constraints
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC=k12;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC=p14;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC=l12;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC=n14;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC=p13;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC=n12;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC=p12;
>Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC=p11;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<0> LOC=k13;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<1> LOC=k14;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<2> LOC=j13;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<3> LOC=j14;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<4> LOC=h13;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<5> LOC=h14;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<6> LOC=g12;
>Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<7> LOC=f12;
>
>My ucf file look like this:
>NET "sys_reset"  LOC = "L14"  ; 
>NET "sys_clock"  LOC = "T9"  ; 
>NET "Leds_GPIO_d_out<0>"  LOC = "K12"  ; 
>NET "Leds_GPIO_d_out<1>"  LOC = "P14"  ; 
>NET "Leds_GPIO_d_out<2>"  LOC = "L12"  ; 
>NET "Leds_GPIO_d_out<3>"  LOC = "N14"  ; 
>NET "Leds_GPIO_d_out<4>"  LOC = "P13"  ; 
>NET "Leds_GPIO_d_out<5>"  LOC = "N12"  ; 
>NET "Leds_GPIO_d_out<6>"  LOC = "P12"  ; 
>NET "Leds_GPIO_d_out<7>"  LOC = "P11"  ; 
>NET "Switch_GPIO_in<0>"  LOC = "F12"  ; 
>NET "Switch_GPIO_in<1>"  LOC = "G12"  ; 
>NET "Switch_GPIO_in<2>"  LOC = "H14"  ; 
>NET "Switch_GPIO_in<3>"  LOC = "H13"  ; 
>NET "Switch_GPIO_in<4>"  LOC = "J14"  ; 
>NET "Switch_GPIO_in<5>"  LOC = "J13"  ; 
>NET "Switch_GPIO_in<6>"  LOC = "K14"  ; 
>NET "Switch_GPIO_in<7>"  LOC = "K13"  ; 
>
>This problem is realy getting annoying, there must be something
>essential I have been overlooked.
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     


Article: 85501
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 10 Jun 2005 12:24:34 GMT
Links: << >>  << T >>  << A >>
On Fri, 10 Jun 2005 12:07:31 +0100, "John Adair"
<removethisthenleavejea@replacewithcompanyname.co.uk> wrote:

>If you just need synthesis, p&r, then ISE Webpack can be used as a stop gap 
>for Spartan-3 devices up to XC3S1500.

That's what I'm using, but I'm told that BlockRam is difficult to use if you don't have the CoreGen
part which doesn't come with Webpack - not looked into this yet though. 


Article: 85502
Subject: Re: execute ppc code from external ram
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Fri, 10 Jun 2005 14:30:22 +0200
Links: << >>  << T >>  << A >>
I can not totally explain the facts, but it's working now. There was 
something wrong with the startup procedure (the way I built the code was not 
correct). After using a linker file it worked.

Frank

"Frank van Eijkelenburg" <someone@work.com> wrote in message 
news:346fc$42a869eb$3e3aa7a5$12115@news.versatel.net...
> We have made a memory controller which handles accesses from/to ddr sdram. 
> A bootloader is running in bram and we download an application into 
> external ram. The code in the external ram is exactly what we downloaded. 
> If we jump to it, the powerpc starts executing from it and for some reason 
> it comes in bram again (it's running the bootloader code). AFAIK there is 
> no jump in the application and there was no reset.
>
> If we use the debugger to download the application to external ram (with 
> dow <file> <address>) and run the code, everything is working fine. When I 
> built the application, I use the following makefile:
>
> =======================
> #################################################################
> # Makefile
> #################################################################
>
> CC      = powerpc-eabi-gcc
> AR      = powerpc-eabi-ar
> OBJCOPY = powerpc-eabi-objcopy
> OBJDUMP = powerpc-eabi-objdump
>
>
> CFLAGS  = -O2 -g
>
> SRC  = ./src
> INC  = ./include
>
> C_INC = ../include
>
> OBJS = appl.o tl_debug.o uart.o
>
> TOPDIR = ../ppc405_0/code
> SYSTEMDIR = ../../ppc_system/ppc405_0
> INCLUDEDIR = $(SYSTEMDIR)/include
> LIBDIR = $(SYSTEMDIR)/lib
> INCLUDES = -I$(INCLUDEDIR) -I$(INC) -I$(C_INC)
> LIBS = -L$(LIBDIR) -L$(TOPDIR)
>
> LIBRARIES =
>
> # Linker options for the elf file
> LFLAGS = -Wl,-defsym -Wl,_START_ADDR=0x00000000
>
> VPATH = $(SRC)
>
> appl.o   : appl.c
> tl_debug.o  : tl_debug.c
> uart.o   : uart.c
>
> all:
> @echo "Makefile to build application which runs on DDR SDRAM"
> @echo "   - RAM base address: 0x00000000"
> @echo "   - application is placed in DDR SDRAM by bootloader"
> @echo ""
> @echo "Usage: make appl"
>
> appl: $(INCLUDEDIR)/xparameters.h $(OBJS) makefile
> $(CC) $(CFLAGS) -o appl.elf $(OBJS) $(LFLAGS) $(LIBS) $(LIBRARIES)
> @echo "appl.elf created at location 0x00000000"
> @echo ""
> $(OBJDUMP) -D -b elf32-powerpc appl.elf > appl.txt
> $(OBJCOPY) -I elf32-powerpc -R .boot -R .boot0 -O binary -S appl.elf 
> appl.bin
>
> %.o:%.c
> $(CC) $(CFLAGS) -c $< -o $@ $(INCLUDES)
>
> %.o:%.s
> $(CC) $(CFLAGS) -c $< -o $@
>
> clean:
> rm -f $(OBJS) appl.elf appl.bin appl.txt
>
> $(INCLUDEDIR)/xparameters.h:
> $(error Make sure you have built the libraries for the bootloader)
>
> =======================
>
> Do I have to use a linker file for locating different sections at the 
> right place? What could be the reason for working in the debugger (gdb) 
> and not working without debugger?
>
> TIA,
> Frank
>
>
> 



Article: 85503
Subject: Re: Building a MicroBlaze from scratch, unable to run.
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Fri, 10 Jun 2005 14:34:52 +0200
Links: << >>  << T >>  << A >>
Did you already compared your mhs and mss files with the original one? I 
think the answer for your problems can be found in these files.

Frank

"Raymond Bakken" <raybakk@yahoo.no> wrote in message 
news:bd3b4b86.0506100415.1d05485c@posting.google.com...
> Hi
>
> I am using a spartan3 development board and trying to learn about
> MicroBlaze.
>
> My application is simple, I want the bitpattern at the slideswitches
> to appear on the leds (The board has 8 slideswitches and 8 leds).
>
> If I use the BSB to create my MicroBlaze it works fine.
> the modules (in Add/Edit cores) the BSB create/use is:
> microblaze         4.00.a    microblaze_0
> opb_mdm            2.00.a    debug_module
> lmb_bram_if_cntrl  1.00.b    dlmb_cntlr
> lmb_bram_if_cntrl  1.00.b    ilmb_cntlr
> bram_block         1.00.a    lmb_bram
> opb_gpio           3.01.b    LEDs_8Bit
> opb_gpio           3.01.b    DIP_Switches_8Bit
> dcm_module         1.00.a    dcm_0
>
> If I make one from scratch it doesn't work.
> the module (in Add/Edit cores) I create/use is:
> lmb_bram_if_cntrl  1.00.b    i_bram
> lmb_bram_if_cntrl  1.00.b    d_bram
> bram_block         1.00.a    bram
> opb_gpio           3.01.b    Switch
> microblaze         4.00.a    MyProsessor
> opb_gpio           3.01.b    Leds
> dcm_module         1.00.a    dcm_0
>
> and my c-code is simple (used on both):
> #include "xparameters.h"
> #include "xgpio_l.h"
>
>
>
> int main()
> {
> unsigned char ucData;
> while(1)
> {
>                // read from slide switches.
> ucData = XGpio_mGetDataReg(SWITCH BASEADDR, 1);
>                // put value in LEDs
> XGpio_mSetDataReg(LEDS BASEADDR, 1, ucData);
> }
> return 0;
> }
>
> The BASEADDR are from the headers xparameters.h in the respective
> projects.
>
> BSBs ucf file look like this:
> Net sys_clk_pin LOC=T9;
> Net sys_rst_pin LOC=l14;
> ## System level constraints
> Net sys_clk_pin TNM_NET = sys_clk_pin;
> TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
> Net sys_rst_pin TIG;
>
> ## FPGA pin constraints
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC=k12;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC=p14;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC=l12;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC=n14;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC=p13;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC=n12;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC=p12;
> Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC=p11;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<0> LOC=k13;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<1> LOC=k14;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<2> LOC=j13;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<3> LOC=j14;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<4> LOC=h13;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<5> LOC=h14;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<6> LOC=g12;
> Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin<7> LOC=f12;
>
> My ucf file look like this:
> NET "sys_reset"  LOC = "L14"  ;
> NET "sys_clock"  LOC = "T9"  ;
> NET "Leds_GPIO_d_out<0>"  LOC = "K12"  ;
> NET "Leds_GPIO_d_out<1>"  LOC = "P14"  ;
> NET "Leds_GPIO_d_out<2>"  LOC = "L12"  ;
> NET "Leds_GPIO_d_out<3>"  LOC = "N14"  ;
> NET "Leds_GPIO_d_out<4>"  LOC = "P13"  ;
> NET "Leds_GPIO_d_out<5>"  LOC = "N12"  ;
> NET "Leds_GPIO_d_out<6>"  LOC = "P12"  ;
> NET "Leds_GPIO_d_out<7>"  LOC = "P11"  ;
> NET "Switch_GPIO_in<0>"  LOC = "F12"  ;
> NET "Switch_GPIO_in<1>"  LOC = "G12"  ;
> NET "Switch_GPIO_in<2>"  LOC = "H14"  ;
> NET "Switch_GPIO_in<3>"  LOC = "H13"  ;
> NET "Switch_GPIO_in<4>"  LOC = "J14"  ;
> NET "Switch_GPIO_in<5>"  LOC = "J13"  ;
> NET "Switch_GPIO_in<6>"  LOC = "K14"  ;
> NET "Switch_GPIO_in<7>"  LOC = "K13"  ;
>
> This problem is realy getting annoying, there must be something
> essential I have been overlooked. 



Article: 85504
Subject: Re: I2C clock stretching(XILINX reference design)
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Fri, 10 Jun 2005 12:49:12 GMT
Links: << >>  << T >>  << A >>
Hi Praveen (again).

If the Xilinx app not does not support clock stretching, it has not met the 
I2C spec and has no right to claim it is I2C. Clock stretching is an 
essential part of I2C, it was put in there to allow proper operation with 
slower I2C slaves.

I2C slaves _and_ masters have to wait for SCL to go high after they release 
it.

> if I want Clock stretching the slave also will
> be driving the SCL low when required to keep the master on hold.

Correct.

> In this case SCL will be an INOUT for my module.

Correct.

> My question is how to go about this implementation(tristate buffers on
> SCL!!!).
> What I am planning to do is, I will pull the SCL line low whenever I
> want to stop the clock transition on SCL from master else I will drive
> a "Z" on SCL.

Correct.

> please comment on this implementation.

This is all in the I2C spec.

I'm staggered at how many people have difficulty understanding it.
Arizona Microchip application notes are/were really bad implementations.

I'm surprised if Xilinx have written similar half-assed examples.





Article: 85505
Subject: Re: Building a MicroBlaze from scratch, unable to run.
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Fri, 10 Jun 2005 13:52:38 +0100
Links: << >>  << T >>  << A >>
Hi Raymond,

> My application is simple, I want the bitpattern at the slideswitches
> to appear on the leds (The board has 8 slideswitches and 8 leds).
> If I use the BSB to create my MicroBlaze it works fine.
> If I make one from scratch it doesn't work.
> and my c-code is simple (used on both)

Something I ran into once while doing something similar: remember that the
GPIO component is bi-directional by default. You can statically configure a
particular GPIO block to be always-input or always-output, but otherwise
it's configurable by software (on a per-bit basis). The BSB may have
defaulted the LED and Switch GPIOs to be outputs and inputs respectively,
because it knows what they are.

If you haven't already thought of this, try adding the following lines
before your while loop:

XGpio_mSetDataDirection(LEDS_BASEADDR, 1, 0x00); /* all outputs */
XGpio_mSetDataDirection(SWITCH_BASEADDR, 1, 0xff); /* all inputs */

Alternatively, you could fix it in hardware. Or, of course, it could be
something else entirely... :-) Hope this helps.

Cheers,

        -Ben-



Article: 85506
Subject: Re: I2C clock stretching(XILINX reference design)
From: John_H <johnhandwork@mail.com>
Date: Fri, 10 Jun 2005 13:23:42 GMT
Links: << >>  << T >>  << A >>
Kryten wrote:
> Hi Praveen (again).
> 
> If the Xilinx app not does not support clock stretching, it has not met the 
> I2C spec and has no right to claim it is I2C. Clock stretching is an 
> essential part of I2C, it was put in there to allow proper operation with 
> slower I2C slaves.

<snip>

A master has to support clock stretching to be I2C compliant.
Clock stretching is used by slaves that need time to process data.
If a slave doesn't need the extra time, it doesn't need to stretch the 
clock and can maintain I2C compliance without clock stretching.

Article: 85507
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 10 Jun 2005 14:29:17 +0100
Links: << >>  << T >>  << A >>
Depends what config you want. If it is just a single blockram, or a single 
depth of blockram, then that is simple to instantiate. The Xilinx libraries 
guide is a good place to start for info. Look for RAMB16 as a root name. 
There are also some templates listed in ISE for instantiation which you can 
adapt to fit any particular RAMB16 variant listed in the libraries guide if 
not directly listed in the templates.

If you need less than 16K address locations then you should get away with a 
single depth of block ram, e.g. a 16 KByte ram would be 16 block rams on a 
x1 organisation supplying one data bit each. Don't need data muxing this way 
or any modifications on address.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Mike Harrison" <mike@whitewing.co.uk> wrote in message 
news:kg1ja11katq3ojaud6kuqfjtr1atvbdqp4@4ax.com...
> On Fri, 10 Jun 2005 12:07:31 +0100, "John Adair"
> <removethisthenleavejea@replacewithcompanyname.co.uk> wrote:
>
>>If you just need synthesis, p&r, then ISE Webpack can be used as a stop 
>>gap
>>for Spartan-3 devices up to XC3S1500.
>
> That's what I'm using, but I'm told that BlockRam is difficult to use if 
> you don't have the CoreGen
> part which doesn't come with Webpack - not looked into this yet though.
> 



Article: 85508
Subject: A lot of trouble when trying to debug c code on MicroBlaze
From: raybakk@yahoo.no (Raymond Bakken)
Date: 10 Jun 2005 06:37:50 -0700
Links: << >>  << T >>  << A >>
If I use XMD - Software debugger or debugging by SDK the debugger
seams to go out of scope when I am about to enter a function, but this
happends quite randomly. It is not at a particular function.

An other problem I have is with the UartLite drivers.
I have tried to make myself some higher level drivers on my own.
My driver:
typedef struct
{
	Xuint32 RegBaseAddress;     // Base address of registers //
	Xuint16 DeviceID;	    // Unique ID  of device //
	Xuint32 *StatusReg;	    // pointer to the statusregister //	
	Xuint32 *ControlReg;	    // pointer to the controlregister //
} RUartLite;
And one of the functions to the driver:
void RUartLite_Recv(RUartLite *Ptr, Xuint8 *DataBufferPtr,
                            unsigned int NumBytes)
{
	Xuint8 Temp; // remove when driver works.
	unsigned int i;
	for(i=0; i<NumBytes; i++)
	{
		Temp = XUartLite_RecvByte(Ptr->RegBaseAddress);		
		DataBufferPtr[i] = Temp;
	}	
} 


In the function main()
{
    RUartLite Uart;	// Creating driver for a device.
    Uart.RegBaseAddress = XPAR_RS232_BASEADDR;// Setting the
baseadress
    Uart.DeviceID = XPAR_RS232_DEVICE_ID;	  // Filling in the
deviceID.
    ... code ...

    // Using the driver waiting for a 'g' on the uart //
    if(GOTDATA)
    {
        Xuint8 RXData;

        // 2 different ways of reseiving data //
        RUartLite_Recv(&Uart, &RXData, 1);                // DOES NOT
WORK
        RXData = XUartLite_RecvByte(Uart.RegBaseAddress); // WORK

        ... code ...
    }

When I use my driver the variable Temp gets the value 1 (desimalvalue)
When I'm not RXData get the right value ('g').

What can be wrong with my debugger and c-code?

Raymond

Article: 85509
Subject: set seed in 6.2i or 6.3i -timing?
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Fri, 10 Jun 2005 13:40:45 +0000 (UTC)
Links: << >>  << T >>  << A >>
Is there any way to set the seed (par -t) when using -timing in map?  When
-timing is used, map runs the placer, but there is no option to set the
seed.  -t still effects the router in par, but not by very much.

(Yes, I know this is fixed in the 7.1 tools).

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 85510
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 10 Jun 2005 13:54:47 GMT
Links: << >>  << T >>  << A >>
On Fri, 10 Jun 2005 14:29:17 +0100, "John Adair"
<removethisthenleavejea@replacewithcompanyname.co.uk> wrote:

>Depends what config you want. If it is just a single blockram, or a single 
>depth of blockram, then that is simple to instantiate. The Xilinx libraries 
>guide is a good place to start for info. Look for RAMB16 as a root name. 
>There are also some templates listed in ISE for instantiation which you can 
>adapt to fit any particular RAMB16 variant listed in the libraries guide if 
>not directly listed in the templates.
>
>If you need less than 16K address locations then you should get away with a 
>single depth of block ram, e.g. a 16 KByte ram would be 16 block rams on a 
>x1 organisation supplying one data bit each. Don't need data muxing this way 
>or any modifications on address.

thanks - I'll take a look at that when I get a chance - I'll probably end up needing 4 or 5 seperate
small blocks in different configurations but I'm still starting on the learning curve so there's
probably enough to get started at least.
 I also noticed that the S3 kit CD has a 60 day eval of Foundation so I imagine I can install that
to generate the parts I need if necessary. 
 


Article: 85511
Subject: Re: DDR desing with FPGA
From: "Teo" <themarenas@comcast.net>
Date: 10 Jun 2005 07:08:42 -0700
Links: << >>  << T >>  << A >>
We are using the IP core from Lattice that imports to the IP manager.
My consultant has it running in an EC20.


Article: 85512
Subject: Re: re:How to add a lib to the core used
From: "Joey" <johnsons@kaiserslautern.de>
Date: Fri, 10 Jun 2005 16:32:19 +0200
Links: << >>  << T >>  << A >>

No, I used the .pao file (Peripheral Analysis Order)
I edited the user_logic.vhd file using ModelSim and simulated it. It all
went fine. Then I imported the the device/peripheral using the same .pao
file and added the new files in the wizard. This had updated the .pao file
and I have cross checked it. But when I "Generate Netlist" in XPS, its not
finding the function.

"digi" <digitreaco@yahoo-dot-de.no-spam.invalid> schrieb im Newsbeitrag
news:SfOdnUmCl8oD9jXfRVn_vg@giganews.com...
> Do you have choose .prj file in Wizard?
>



Article: 85513
Subject: Re: General gripe session ....
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 10 Jun 2005 07:50:30 -0700
Links: << >>  << T >>  << A >>
Erik,

How is USB hot plug to the FPGA?  USB may be hot plug to itself, but the 
FPGA isn't involved.

And, if you pull the USB plug, you disconenct the link, and it stops. 
If you plug it in, it starts to work.  This is not considered hot plug 
in the industry.  Hot plug is when you plug into something already 
working, and try not to disturb it (generally).

What you are talking about is better called "live insertion" where you 
are concerned about something breaking if you attach something while the 
power is on, or detach it when it was powered.

I can't see any issues here with any of our parts, past or present.

If you are attempting to power the FPGA from the USB 5V @ 500 mA, that 
will be an issue with any part that has a startup current requirement.

We made a USB pcb with a switching regulator (from 5Vdc to 1.5V) for a 
2VP4.  That is 2.5 W total power available from the USB, and at 1.5V, 
that is 2.5/1.5 ~ 1.5 amps (derating for efficiency).  At 1.8V it is 
less, and at 2.5V, less than an ampere.  This might be an issue for the 
old parts (see the data sheet).

The USB pcb is the "Logic Vault" board for security experimentation 
(with 3DES key, 20+ year life lithium coin cell, and a true random 
number generator IP that runs when you plug it in).

We have passed these out to people who promised to hack and tell us the 
key, or the bitstream.  No one has been able to crack them (yet). 
Evidently 3DES in V2 and V2P is still quite secure....

Austin

Erik Walthinsen wrote:

> Austin Lesea wrote:
> 
>> Very few people in your situation are designing boards that are going 
>> to be hot-plugged, and even fewer care what happens when you do.  For 
>> those who do care, we have a full range of documented proven solutions.
> 
> The design I have in mind right now is hot-plugged, but only on the USB 
> side.  The FPGA will be glue between the USB chip, DRAM and flash.  I'm 
> hoping that the power-up requirements of an XC2S50E or -100E won't 
> require any significant control circuitry.  Eventually I hope to reduce 
> the logic requirements to a lot fewer pins and gates, into CPLD realm, 
> but for experimentation I want to have every pin of every device routed 
> through the FPGA, even if half the logic is just crosspointing.
> 
>> I am sure that must be tough going, but most hobbiests realize that 
>> buying exiting development boards (like the Spartan 3 student Digilent 
>> pcb for $99) is a better choice than trying to etch your own pcb's in 
>> the sink.
> 
> I have this board, and am going to try to do my initial development by 
> building boards to plug into the 40pin connectors, but among other 
> things that limits me afaict to an x8 DRAM instead of x16, due to lack 
> of pins.  A x16 JEDEC pinout for 256 or 512Mb has 16 data lines, 13 addr 
> lines, BA0, BA1, RAS#, CAS#, WE#, CLK, CKE, DQML, and DQMH.  Total of 
> 39.  I'm still figuring out how SDRAM works, but I'm only sure I can tie 
> CKE, DQML, and DQML.  That gets me to 36, but there are only 34 I/O's on 
> connectors A2 and B1 of the Spartan3 board...
> 
> Flash is easier, only 15 pins.  USB I've already done hand-wired using 
> the ELRAsoft EZ-USB FX2 board, and in a manner IMO far superior to the 
> board Digilent sells to do the same thing (I actually connect all the 
> pins... x16 data and control).  Already done a basic test design all the 
> way through to user-space software in Linux on that setup 
> (host-controlled PWM of the 8 LEDs).

Article: 85514
Subject: xmodem/kermit for edk/ppc
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 10 Jun 2005 16:52:22 +0200
Links: << >>  << T >>  << A >>

I want do download some date into my FPGA over a serial line. It would
be great to do so using xmodem or kermit. However, the source code
I've found (Omen and Columbia U) seem to be based upon a file system
or assume a POSIX OS.

Are there any simple public domain xmodem or kermit implementations
which will simply store the received data in a buffer out there?

Petter 
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 85515
Subject: Re: faster Spartan III adder
From: Paul Smith <ptsmith@nospam.indiana.edu>
Date: Fri, 10 Jun 2005 09:54:48 -0500
Links: << >>  << T >>  << A >>
Sylvain Munaut wrote:

> 
> No, if the timing meets at these conditions, it is safe to run it at 
> 85C and 1.14V ...
> 

How much "margin" is built in to the timing specs?  If the Xilinx timing 
analyzer tells me the design meets a 3.999 ns cycle time should I worry 
about running it at 4 ns?  If not, how much margin should I allow for 
(as a rule of thumb)?

Paul

Article: 85516
Subject: Re: not clear about doing power estimation using xpower
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 10 Jun 2005 07:57:03 -0700
Links: << >>  << T >>  << A >>
Ray,

You are correct, Ray.  We may disagree about who makes the "best" part, 
but it is the customer who ultimately decides.

Austin

Article: 85517
Subject: XPS : Body of function not found
From: "Joey" <johnsons@kaiserslautern.de>
Date: Fri, 10 Jun 2005 16:59:44 +0200
Links: << >>  << T >>  << A >>
Hi,

Recently I was trying to implement a plb peripheral. I made a plb peripheral
device using the "Create/Import Peripheral" utility and edited the
user_logic.vhd file according to what I needed. I didn't forget to Import
the peripheral after editing.
Now here is the problem. When I used this peripheral in XPS and generated
the netlist, it gave me the following error and exited.


XST synthesis
plb_decoder_0_wrapper (plb_decoder_0) -
E:\Test\xps_decoder\try01\system.mhs:63
- Running XST synthesis
ERROR:Xst:813 -
E:/Test/xps_decoder/try01/pcores/plb_decoder_v1_00_a/hdl/vhdl/user_logic.vhd
line 53: Body of function UNSIGNED_NUM_BITS not found.
ERROR:MDT - HDL synthesis failed!
INFO:MDT - Refer to
   E:\Test\xps_decoder\try01\synthesis\plb_decoder_0_wrapper_xst.srp for
details
ERROR:MDT - platgen failed with errors!
make: *** [implementation/reset_block_wrapper.ngc] Error 2
Done.

The plb_decoder_0_wrapper_xst.srp fiel doesn't say much either. It just
exits where it enters the user_logic.vhd file after the library
declarations. I am also giving a part of the .pao file where all my files
listed can be seen:

lib plb_decoder_v1_00_a support_4M_pk
lib plb_decoder_v1_00_a parameter_4M_pk
lib plb_decoder_v1_00_a derived_param_4M_pk
lib plb_decoder_v1_00_a types_4M_pk
lib plb_decoder_v1_00_a Bit_Node      <== UNSIGNED_NUM_BITS is in this file
lib plb_decoder_v1_00_a Shuffle_controller
lib plb_decoder_v1_00_a barrel_shift
lib plb_decoder_v1_00_a decoder_4M_top
lib plb_decoder_v1_00_a generic_dual_port_ram
lib plb_decoder_v1_00_a serialnode
lib plb_decoder_v1_00_a top_interface
lib plb_decoder_v1_00_a user_logic
lib plb_decoder_v1_00_a plb_decoder

I have the above mentioned function in my Bit_Node (.vhd) file which also
accesses all those 4 packages already mentioned in the first 4 lines. Can
anybody help me ?

Joey




Article: 85518
Subject: Re: Microblaze 4.0 with uClinux is ok or not?
From: "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at>
Date: Fri, 10 Jun 2005 17:13:27 +0200
Links: << >>  << T >>  << A >>
>
> Antti
> PS after downgrading the microblaze to 3.0 www.hydraxc.com started to work
> fully with networking support!!
>
Antti,

the features of hydraxc look good, but when will it be available?
What about pricing info?

One more point: Are you aware of the name clash of your product
with an FPGA based chess engine. Probably the strongest chess machine
at the time: http://www.hydrachess.com/

Martin 



Article: 85519
Subject: Re: ISE/EDK 6.3 vs 7.1...
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 10 Jun 2005 17:21:02 +0200
Links: << >>  << T >>  << A >>
"Klaus Falser" <kfalser@durst.it> schrieb im Newsbeitrag
news:MPG.1d13652b202295e698968a@news.inet.it...
> In article <ee8ec82.1@webx.sUN8CHnE>, vadimv@ieee.org says...
> > I also noticed that the fitter for ISE 7.1 isn't as efficient.
> > I had a legacy design for an XC9500, and I called Xilinx tech
> > support on an unrelated issue. I was using 6.3, the tech support
> > guy used 7.1, and he couldn't fit my design to the chip.
> > He had to install 6.3 to be able to work on it. It really does
> > seem that the new fitter isn't as efficient.
> >
>
> IMHO, for XC9500 CPLD's it is best to stick with
> Webpack 5.2.
> Only yesterday I had a case where I needed to modify an
> old design slightly and in this occasion I thought
> to migrate the design to the lastest ISE version.
> The design failed to work, but in a way that only
> some signals were wrong. So the failure was not
> noticed immediately, since some parts of the
> design worked, but an important function did not.
> Simply compiling the design with 5.2 brought
> the design to work.
>
> Since this was not the first time I got burned with
> 7.1 (remember the inverted outputs bug ?),
> I hope I will learn the lession this time.
>
> The story however confirms my opinion that
> the XC9500 family is a unloved child in Xilinx.
>
> Regards
> Klaus

XC9500 is not Xilinx child, they did buy the technology in...
same as they did buy CoolRunner,
to my knowledge Xilinx has no own PLD technology at all.

Antti





Article: 85520
Subject: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 10 Jun 2005 11:28:53 -0400
Links: << >>  << T >>  << A >>
I am getting the following warning on a Virtex-II design:

WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1
NON-CLK pins failed to route using a CLK template.

My question is how can I find the problematic pin?

A similar question was asked here in the past, but the discussion slipped
into design practices. My design is pretty big and the biggest part of it is
third party core, for which I don't have source code. So, I need to figure
out what exactly causes this warning...

Thanks,
/Mikhail



Article: 85521
Subject: Re: faster Spartan III adder
From: Ray Andraka <ray@andraka.com>
Date: Fri, 10 Jun 2005 11:33:26 -0400
Links: << >>  << T >>  << A >>

That'll work, but it occupies an awful lot of area for not a lot of 
speed gain when you consider that you need skew and deskew registers on 
the inputs and output. You'll use up less area by running two (or more) 
adders in parallel and distributing the inputs in a round-robin 
fashion.  If you only count the input registers and adders, this doesn't 
sound like much of an area savings over the fully pipelined adder (you 
save the deskew register, but that's about it). HOwever, you also have 
to consider that when you use the carry chain, you essentially get two 
luts for the price of one.  Each bit of the adder requires a sum 
function and a carry function, which without the carry chain occupies 
two LUTs or a complete slice.  By using the carry chain logic, you get 
the carry function for each bit for free so it only occupies one LUT 
(half a slice) per bit.  The long and short of it is that with the 
Xilinx CLB structure, you'll get a more efficient result by using 
parallel adders than by pipelining a single adder.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 85522
Subject: Re: I2C clock stretching(XILINX reference design)
From: "Gabor" <gabor@alacron.com>
Date: 10 Jun 2005 08:33:33 -0700
Links: << >>  << T >>  << A >>


John_H wrote:
> Kryten wrote:
> > Hi Praveen (again).
> >
> > If the Xilinx app not does not support clock stretching, it has not met the
> > I2C spec and has no right to claim it is I2C. Clock stretching is an
> > essential part of I2C, it was put in there to allow proper operation with
> > slower I2C slaves.
>
> <snip>
>
> A master has to support clock stretching to be I2C compliant.
> Clock stretching is used by slaves that need time to process data.
> If a slave doesn't need the extra time, it doesn't need to stretch the
> clock and can maintain I2C compliance without clock stretching.

Good point.  A lot of IC's with I2C slaves show the SCL pin as
an input-only.  The Xilinx app assumes you're getting data from
inside the FPGA which should never require stretching even at
the fastest bit rates.

A clock stretcher usually only asserts SCL during the ACK cycle of
the access requiring more time.  This is not a requirement, but it
keeps a slave from stretching SCL cycles that are not intended for
that slave, as might happen if the address is still being sent.

Also make sure that the decision to stretch or not stretch does not
come more than Tlow (min) after the falling edge of SCL or you may
have a race condition allowing the SCL to "double pulse".  It's
probably best to syncronize the start of the stretch pulse to the
falling edge of SCL.


Article: 85523
Subject: Re: faster Spartan III adder
From: Ray Andraka <ray@andraka.com>
Date: Fri, 10 Jun 2005 11:35:44 -0400
Links: << >>  << T >>  << A >>
Paul Smith wrote:

> How much "margin" is built in to the timing specs?  If the Xilinx 
> timing analyzer tells me the design meets a 3.999 ns cycle time should 
> I worry about running it at 4 ns?  If not, how much margin should I 
> allow for (as a rule of thumb)?
>
> Paul

You'll be fine as long as your input clock does not have any jitter on 
it.  You need to add a jitter allowance to your cycle time.  The static 
analyzer is the worst case timing over process, voltage and 
temperature.  It takes into account the logic delays and clock network skew.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 85524
Subject: Re: not clear about doing power estimation using xpower
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 17:37:52 +0200
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
news:d8c9nv$k9v1@cliff.xsj.xilinx.com...
> Ray,
>
> You are correct, Ray.  We may disagree about who makes the "best" part,
> but it is the customer who ultimately decides.

what to buy. But this doesnt neccessarily mean he buys the better part. The
market leader isnt always the technology leader. But who cares about
technology when your paycheck is top? But this is getting a little bit too
philosophic, isnt it ? ;-)

Regards
Falk








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