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Summary: Should high-speed shift registers (purely DFFs) flow left->right, top->bottom, or does it matter? Doing a Virtex4 (LX100). I wound up with high-speed inputs (clocks and serial data) on the IOBs that run vertically down the center of the die. OK for clocks, since the DCMs and BUFGs are also in that center column. Regarding data: I deserialize the inputs, and pass parallel data to some large datapath blocks that start on the left edge of the die. I constrain all my deserializer logic to use sites near the center column to minimize clock skew. (Sorry, I can't use the on-chip deserializers; they max out at 10 bits, and I need 12.) Kind of annoying to take my inputs from the center over to the left, and then start flowing left-to-right, but that's just how the layout wound up... Anyway, older Xilinx docs say you should flow left->right, and numerical operations should have their MSB flowing downward (?) to make best use of carry chains. Is that still the case? Back to my deserializers: I'm using 20 of them, so that's 40 6-bit shift registers (6 bits on rising edge, 6 bits on falling edge), which I plan to do manual placement on. I don't want to use the SRL16's (yet; long story...), but just DFFs. I thought left->right flow was perfect for shift registers, but ISE seems to place all the DFFs for a downward flow. Actually, since my inputs are all down the center column (20 serial data streams) and need to go left, horizontal alignment flowing right-to-left makes for best placement. Not sure about routing though... Any suggestions? The data is coming in close to 1Gbps, so the shift regs run close to 500 MHz... Thanks again for all the help; I'll appreciate your input as I work another weekend...Article: 90226
Hey, I have been dealing with this situation as well. When you compile the design, look in the project folder under modelsim sub folder, you should be able to find a .vo or .vho file depending upon your settings for verilog or vhdl in quartus II. Create a project in Modelsim and add the .vo or .vho file along with the stratix GX atoms file, u should be able to get it from altera website. For gate delay simulation, get the .sdo file from the design's project folder. When simulating in Modelsim, choose the SDO tab and add this .sdo file there and then simulate...its MAGIC!!! later MORPHEUSArticle: 90227
I wonder if there is a posibility to do Xilinx fpga synthesis and implementation from command line on WindowsXP platform to speed up the process. Xilinx web site mentioned something, that it's only availabe for CPLDs. XESS have an app note on how to use Make file to script and automate build process. It needs fe_shell utility, but I don't think it comes with WebPack edition.Article: 90228
I learnt at uni that two flip-flops is generally sufficient for synchronising an asynchronous signal. But what if the phase of the sampled signal isn't uniformly random? In particular, how would I deal with synchronising two different clock domains where one clock is the reference of a PLL, and the second clock is the output of that PLL, say 8 times faster. Also, the frequency of the input clock, and consequently the output clock is FM modulated - although the frequency variation is slight. The frequency of the fast clock is on the order of GHz. I figure that since the two clocks are related, the chance of metastability is drastically higher. How should one deal with such a scenario? Thanks in advance, Michael.Article: 90229
On Thu, 06 Oct 2005 11:16:15 -0500, mvetromille@gmail-dot-com.no-spam.invalid (Melissa Vetromille) wrote: >> Zarawrote: >On Wed, 05 Oct 2005 19:16:02 -0500, >> mvetromille@gmail-dot-com.no-spam.invalid (Melissa Vetromille) >wrote: >> >> >> You must create a new chipscope icon with Disable Boundary Scan >> Component Instance. hta will give you an Icon with more ports than >> usual, these ports must be connected to the corresponding ports of >the >> opb_mdm component (use Show ports with default connections when >> connecting ports) > >I don't know how to disable the boundary scan component instance. I >tryied to do this, but it was unsuccessfull. Could you help me >again? > >Thank you! Open Chipscoper Core generator. Select ICON, press Next>. Write name of file, select device family and in ICON parameters select Number of Control Ports and Check Disable Boundary Component Instance, press Next>. Slect you preferred settings, and press generate Core. There you are.Article: 90230
This is a synchronoeus design. Note that the phase of input clock and feedback of a PLL is approximately zero and the uncertainty can be well defined, as well as the setup and hold times of the clock divider (3 ffs for 8 times faster output). So you can statically analyze your design, with a static timing analyzer or manually and insert appropriate delay gates to fulfill your setup/hold time requirements so that no metastability occurs at all. Hubble.Article: 90231
On Thu, 06 Oct 2005 15:07:20 -0400, Francis <NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM> wrote: >Adding a new microblaze in a EDK project is ok, I already now this but.. >For me it is easier to have two different EDK included in ISE. >I want to instantiate multiple EDK (as component) connected to my IP >made in ISE. Will be easier in ISE because I have a lot of pins. >Is it still possible? > If I try to add a second XPS project to an ISE project, it is not allowed. I suppose that with some hacking it should be possible to do that, but I think it will be really difficult to maintain and debug. I f you use various microblazes within the same EPS project, it will be easier to track resource usage (BRAM..) and to connect all of them through the same opb_mdmArticle: 90232
<jjohnson@cs.ucf.edu> schrieb im Newsbeitrag news:1128647278.987068.51970@o13g2000cwo.googlegroups.com... > > Summary: Should high-speed shift registers (purely DFFs) flow > left->right, top->bottom, or does it matter? > > Doing a Virtex4 (LX100). I wound up with high-speed inputs (clocks and > serial data) on the IOBs that run vertically down the center of the > die. OK for clocks, since the DCMs and BUFGs are also in that center > column. > > Regarding data: I deserialize the inputs, and pass parallel data to > some large datapath blocks that start on the left edge of the die. I > constrain all my deserializer logic to use sites near the center column > to minimize clock skew. (Sorry, I can't use the on-chip deserializers; > they max out at 10 bits, and I need 12.) > 6 bit shift register places nicely into single CLB cluster with ALL routing being implemente in the switchbox, eg with no local routing involved at all. So there is no top to bottom or left to right issue at all as its so compact. So as of shift register there is no issue. but at 500MHz clock, sure careful design is required. so for your deserializer 1) use idelay so you can fine adjust the routing delay/diff from iob to the shift dff 'cluster' 1a) use DDR input flops in IOB for the first stage 2) place the parallel holding register 'around' the serializer cluster, this could be possible with short local routing 2a) implement a 2 bit serial parallel cluster (that uses only swithcbox routing) and place the 2 bit clusters so that they reach each by local routing you only need some RLOCs in your macros and all the thing is done. sounds like fun thing todo - I was amazed myself when I measured actual real clock speeds of 970MHz in slowest speed grade V4 :) AnttiArticle: 90233
In article <newscache$tz0zni$bj6$1@lbox.itee.uq.edu.au>, mchan@itee.uq.edu.au says... > I learnt at uni that two flip-flops is generally sufficient for > synchronising an asynchronous signal. But what if the phase of the sampled > signal isn't uniformly random? In particular, how would I deal with > synchronising two different clock domains where one clock is the reference > of a PLL, and the second clock is the output of that PLL, say 8 times > faster. Also, the frequency of the input clock, and consequently the output > clock is FM modulated - although the frequency variation is slight. The > frequency of the fast clock is on the order of GHz. I figure that since the > two clocks are related, the chance of metastability is drastically higher. > > How should one deal with such a scenario? > > Thanks in advance, > > Michael. > > > If the two clock domains are related and the two rising edges matches, you could clock one domain with a rising clock and the next with a falling clock. This way (depends on the frequency and the margin on the setup/hold times) you are always sampling when output of the first domain is stable and you can avoid synchronisation at all. Regards KlausArticle: 90234
OK, I just assumed that you were using a dcf file since that is what the error message reffered to. You could try reimporting your source files into designer, but ensure the little tick box for keep exisiting timing constraints is unticked. Then if it compiles you can then set up your timing constraints again.Article: 90235
> I am reaching upper limit of FPGA resource but still I can fit in all > the logic cores. Is the timing analysis still good ? Rgds Andr=E9Article: 90236
<jjohnson@cs.ucf.edu> schrieb im Newsbeitrag news:1128646162.783940.272640@o13g2000cwo.googlegroups.com... > > HELP! > How to constrain source-synchronous DDR inputs in Xilinx? > In Synplify Pro? just an advice (maybe you did it already) if you are planning to use DCM at 500MHz you need speed grade -12 check out that the LX100 is available in that speedgrade in the timeframe you need it. Maybe it is, just sounds like a good idea to check out now (to avoid surprises). I would be very careful with any design that depends on the DCM output of 500MHz. 2cent advice. well you probably could get away without using DCM also (and using slower speed grade) and as of contrains if you make proper (R)LOCed macros then you can keep most of the design uncontstrained as the timing is guaranteed by the LOC of the primitives. sure if the router makes hassle you may even need to end up using dedicated rotuing constraints, but again thats not timing constraints AnttiArticle: 90237
"Hubble" <reiner@huober.de> wrote in message news:1128665043.630658.249210@g47g2000cwa.googlegroups.com... > This is a synchronoeus design. Note that the phase of input clock and > feedback of a PLL is approximately zero and the uncertainty can be well > defined, as well as the setup and hold times of the clock divider (3 > ffs for 8 times faster output). So you can statically analyze your > design, with a static timing analyzer or manually and insert > appropriate delay gates to fulfill your setup/hold time requirements so > that no metastability occurs at all. > > Hubble. > Actually, ignore the 8 times multiplication, as that makes the problem trivial to solve. In the problem I was trying to solve, I couldn't treat the two clock domains as synchronised, since one clock sometimes led, and sometimes lagged the other clock. This resulted in data changing just as it was being sampled. I was told to add some flipflops to fix up the problems, but it didn't seem like a very good solution. As it was, I sampled data on the falling edge of the clock, but I wonder what I could have done if there wasn't sufficient timing margin for that to work (taking into account the jitter between the two domains). Actually, thinking about it now I think it would have been sufficient to simply sample the output of the negative edge triggered flip-flop with a positive edge triggered flip-flop.Article: 90238
<kkumar@northernpower.com> schrieb im Newsbeitrag news:1128646945.462597.311650@f14g2000cwb.googlegroups.com... > Hi, > We are using Xilinx Spartan2E in our platform and so far functioning of > every logical cores was looking good. Today, I saw some weird behaviour > after addng additional logic, all of sudden I was missing some signals > coming out of FPGA and some signals looks different. This additional > logic does not interfer with the exisitng logic cores. > I am reaching upper limit of FPGA resource but still I can fit in all > the logic cores. > > So my question is, by utilizing the FPGA resource around 90%, does the > behaviour of FPGA logics becomes unpredictible ? > > Any pointers or suggestions in this regard is much appreciated. > > Thank you in advance. > > -Kiran > the logic utilization numer is somewhat magic/bogus, but reaching the limit makes the probability of unexplained behaviour larger, yes. at the very basics a rock solid design should work. should work no matter what, if it runs the toolflow it should work (no matter the utilization). but its hardly ever so in real life. so adding unrelated logic (even when total utilization is not nearly at the max) may introduce unexpected failures. there is no direct advice for you, lots of troubleshooting may be required. the extra logic may iterfere to the way the rest of the logic can be placed what makes the timing different and that can cause problems that did happen before AnttiArticle: 90239
Once Again: Thanks a lot guys! Best regards, Simon "Simon Heinzle" <sheinzle@student.ethz.ch> wrote in message news:4344d45b@news1.ethz.ch... > Hi everybody, > > With ASICs, there are standard cell libraries in .lib file format for the > target process -- is there a comparable .lib file for the Xilinx FPGAs? > > Best regards, > Simon >Article: 90240
On 6 Oct 2005 18:02:25 -0700, kkumar@northernpower.com wrote: >Hi, >We are using Xilinx Spartan2E in our platform and so far functioning of >every logical cores was looking good. Today, I saw some weird behaviour >after addng additional logic, all of sudden I was missing some signals >coming out of FPGA and some signals looks different. This additional >logic does not interfer with the exisitng logic cores. >I am reaching upper limit of FPGA resource but still I can fit in all >the logic cores. > >So my question is, by utilizing the FPGA resource around 90%, does the >behaviour of FPGA logics becomes unpredictible ? > >Any pointers or suggestions in this regard is much appreciated. > >Thank you in advance. > >-Kiran Look at possible timing constraints violation. If neccessary, make constraints stricter, by increasing the frequency and/or adding jitter to the clocksArticle: 90241
"Symon" <symon_brewer@hotmail.com> wrote in message news:434584b2$0$49022$14726298@news.sunsite.dk... > "Marco" <marcotoschi@nospam.it> wrote in message > news:di2she$iji$1@news.ngi.it... >> Hallo, >> I have made a clock divider (1 MHz) with a counter connected to system >> clock (50 MHz). >> This counter has a threshold which goes high on the last count. >> This pulse drives some blocks as a clock enable (the clock input of these >> blocks is connected to system clock). >> Every block is falling edge sensitive. >> > Why are you using the falling edge? Your 50MHz clock should come from a > BUFG and only use one edge (either rising or falling) in all the places it > goes. So, the counter and the 'blocks' you mention should all use the same > edge. Is that what you are doing? There are an ADC and a DAC connected to FPGA pins, and they are falling edge sensitive. >> >> The pulse drives also a FSM where every state send high/low 4 signals. >> >> In this way there is no gating clock, but now pulse signal has high load. >> >> I can't use DCM because of the too low out frequency. >> >> What could I do to reduce load and skew? >> > The enable signal will be automatically buffered by the Xilinx routing. As > long as you've told the timing analyser that your main clock is going at > 50MHz, you don't have to worry about 'load' (or fanout as it's often > called) or skew. To send a 1MHz signal out of the FPGA, as you mentioned > in your other thread, you might like to consider also generating a 2MHz > enable from your 50 MHz counter, as well as the 1MHz one, to toggle the > IOB flip-flop. This morning I have verified that XST generates a fanout at least of 3 on the signal used as clock for FSM indipendentely from the number of signal to drive into FSM. So if the clock is the system clock buffered automatically by XST, the load and skew aren't a trouble and they aren't "visible". Even if I reproduce the clock signal and the state machines, every clock signal has a load of 3. It takes a skew of 1ns and a delay of 2ns. In my case I can't use the system clock. At this point I think the only way is to use a BUFG. So I have placed a BUFG and the trouble seems to be solved, but the DAC reacts in different ways depending on the level of optimizazion of mapping and post-placing. I send a clock signal of 1 MHz, a Chip Select, and 16 serial data bits. I have thought that depending on the level of optimization, the delay between clock and chip select could be different, so the DAC don't go into power on state. In what way may I solve this trouble? Many Thanks MarcoArticle: 90242
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:hidak117pd0s9icqp9ohofgjgcs8vq1ks4@4ax.com... > The problem with your approach is that the second flip-flop, the one > clocked with the 24 MHz falling edge, has less than half as much time > to settle (thanks to the AND gate delay) before being applied to the > circuit. If the first flip-flop says HIGH and the second flip-flop > says "I dunno," what happens to your circuit? (first a modification) lets change this: > process(clk_24M) > begin > if rising_edge(clk_24M) then > if a = b then > q <= a; > end if; > end if; > end process; to this instead: > process(clk_24M) > begin > if rising_edge(clk_24M) then > q <= a or b; > end if; > end process; 1.) At least one of the flip-flops are always correct. 2.) If one of the flip-flop outputs are metastable then the OR-gate says 1 or 0 (if one of it's inputs is metastabel). And remember this can only happen around the rising or falling edge of the 1.8 MHz signal, so by doing this OR-thing we can get the correct bit-value the first sample time or at the following sample time. For my design it doesn't matter if I get the right bit-value shifted 1 more clk in the 24 MHz clock domain. I presume that the OR-gate always deliver a valid 0 (Vout<= VOL) or 1 (Vout=>VOH) when one of it's inputs is a valid 0 or 1 and the other is undefined (between VIH and VIL). But i'm not sure of this behavior maybe some one can reply on this?Article: 90243
"Bill" <billbill@telia.se> wrote in message news:4346337d$0$49011$14726298@news.sunsite.dk... > I presume that the OR-gate always deliver a valid 0 (Vout<= VOL) or 1 > (Vout=>VOH) when one of it's inputs is a valid 0 or 1 and the other is > undefined (between VIH and VIL). But i'm not sure of this behavior maybe > some one can reply on this? What I mean is that I want to be sure that the OR-gate in the FPGA has the following truth table: A B | Q ----+--- 0 X | 0 or 1 X 0 | 0 or 1 X 1 | 1 1 X | 1 1 1 | 1 (Where X means metastable, logical 0 or a logical 1) Then my circuit will work.Article: 90244
"Marco" <marcotoschi@nospam.it> wrote in message
news:di58qu$eof$1@news.ngi.it...
>
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:434584b2$0$49022$14726298@news.sunsite.dk...
>> Why are you using the falling edge? Your 50MHz clock should come from a
>> BUFG and only use one edge (either rising or falling) in all the places
>> it goes. So, the counter and the 'blocks' you mention should all use the
>> same edge. Is that what you are doing?
>
> There are an ADC and a DAC connected to FPGA pins, and they are falling
> edge sensitive.
>
OK Marco, let me see if I understand your design. You have an FPGA. It has a
50 MHz clock available. Let's call this the 'masterclock'. Attached to the
FPGA are a DAC and a ADC. These parts are designed to be clocked at 1MHz,
let's call these the DAC_clock and the ADC_clock. Here's some VHDL.
--snippet to generate clock enables
if res_n = '0' then
--add async resets here
elsif rising_edge(masterclock) then
count <= (count + 1) mod 50; --may not synthesise, but you get the idea
if (count = 25) then
DAC_clock <= '0';
ADC_clock <= '0';
elsif (count = 0) then
DAC_clock <= '1';
ADC_clock <= '1';
end if;
if (count = 49) then
enable_1MHz <= '1'; --this is our 1MHz enable signal
else
enable_1MHz <= '0';
end if;
end if;
--snippet to demonstrate clock enable
if res_n = '0' then
--add async resets here
elsif rising_edge(masterclock) then
if (enable_1MHz = '1') then --Here's the clock enable
--add your 1 MHz state machine stuff here e.g.
DAC_data <= new_DAC_data_value;
ADC_data <= data_from_ADC_device;
end if;
end if;
So, you see that every FF is clocked by the rising edge of the 50MHz clock.
Some are only enabled one every microsecond, but their clock input is still
our masterclock. This masterclock should come from a BUFG. No nasty 'falling
edges' needed. Draw a timing diagram; it'll help you see what's happening!
>
>>>
>>> The pulse drives also a FSM where every state send high/low 4 signals.
>>>
>>> In this way there is no gating clock, but now pulse signal has high
>>> load.
>>>
>>> I can't use DCM because of the too low out frequency.
>>>
>>> What could I do to reduce load and skew?
>>>
>> The enable signal will be automatically buffered by the Xilinx routing.
>> As long as you've told the timing analyser that your main clock is going
>> at 50MHz, you don't have to worry about 'load' (or fanout as it's often
>> called) or skew. To send a 1MHz signal out of the FPGA, as you mentioned
>> in your other thread, you might like to consider also generating a 2MHz
>> enable from your 50 MHz counter, as well as the 1MHz one, to toggle the
>> IOB flip-flop.
>
>
> This morning I have verified that XST generates a fanout at least of 3 on
> the signal used as clock for FSM indipendentely from the number of signal
> to drive into FSM. So if the clock is the system clock buffered
> automatically by XST, the load and skew aren't a trouble and they aren't
> "visible".
>
> Even if I reproduce the clock signal and the state machines, every clock
> signal has a load of 3. It takes a skew of 1ns and a delay of 2ns.
>
> In my case I can't use the system clock. At this point I think the only
> way is to use a BUFG.
>
> So I have placed a BUFG and the trouble seems to be solved, but the DAC
> reacts in different ways depending on the level of optimizazion of mapping
> and post-placing.
>
> I send a clock signal of 1 MHz, a Chip Select, and 16 serial data bits.
>
> I have thought that depending on the level of optimization, the delay
> between clock and chip select could be different, so the DAC don't go into
> power on state.
>
> In what way may I solve this trouble?
>
> Many Thanks
> Marco
>
Sorry Marco, this last part of your post is a mystery to me. You only need
one 'clock' signal, the masterclock. It should have a fanout of more than 3!
The 1MHz enable signal should go to all the FFs in your FSM, I think this
signal should have a lot more than 3 loads as well. A delay of 2ns and a
skew of 1ns is fine for this clock. Do you want to post some code?
Anyway, if this makes any sense to you, post back, and we can talk about the
timing constraints you need to set!
HTH, Syms.
Article: 90245some parallel cable III have the wrong logic to use with low voltage parts... mine wont work below 3.3V.. what is your Jtag? Simon "Klaus Bickertt" <kfb@mpe.mpg.de> wrote in message news:ee90993.5@webx.sUN8CHnE... > My ISE7.1 says parallel cable drivers installed, but refuses to recognize my old cable III and tries using anon-existent multilink. Seems to be reading Prom & Virtex Id's, but can't start them after program. How do I get IMPACT to accept a Cable III ?Article: 90246
> So, you see that every FF is clocked by the rising edge of the 50MHz > clock. Some are only enabled one every microsecond, but their clock input > is still our masterclock. This masterclock should come from a BUFG. No > nasty 'falling edges' needed. Draw a timing diagram; it'll help you see > what's happening! > My code is similar to that you posted, the idea is the same. The only difference is I have used core generator to create the components. I will try drawing a timing diagram. > >> >>>> >>>> The pulse drives also a FSM where every state send high/low 4 signals. >>>> >>>> In this way there is no gating clock, but now pulse signal has high >>>> load. >>>> >>>> I can't use DCM because of the too low out frequency. >>>> >>>> What could I do to reduce load and skew? >>>> >>> The enable signal will be automatically buffered by the Xilinx routing. >>> As long as you've told the timing analyser that your main clock is going >>> at 50MHz, you don't have to worry about 'load' (or fanout as it's often >>> called) or skew. To send a 1MHz signal out of the FPGA, as you mentioned >>> in your other thread, you might like to consider also generating a 2MHz >>> enable from your 50 MHz counter, as well as the 1MHz one, to toggle the >>> IOB flip-flop. >> >> >> This morning I have verified that XST generates a fanout at least of 3 on >> the signal used as clock for FSM indipendentely from the number of signal >> to drive into FSM. So if the clock is the system clock buffered >> automatically by XST, the load and skew aren't a trouble and they aren't >> "visible". >> >> Even if I reproduce the clock signal and the state machines, every clock >> signal has a load of 3. It takes a skew of 1ns and a delay of 2ns. >> >> In my case I can't use the system clock. At this point I think the only >> way is to use a BUFG. >> >> So I have placed a BUFG and the trouble seems to be solved, but the DAC >> reacts in different ways depending on the level of optimizazion of >> mapping and post-placing. >> >> I send a clock signal of 1 MHz, a Chip Select, and 16 serial data bits. >> >> I have thought that depending on the level of optimization, the delay >> between clock and chip select could be different, so the DAC don't go >> into power on state. >> >> In what way may I solve this trouble? >> >> Many Thanks >> Marco >> > Sorry Marco, this last part of your post is a mystery to me. You only need > one 'clock' signal, the masterclock. It should have a fanout of more than > 3! The 1MHz enable signal should go to all the FFs in your FSM, I think > this signal should have a lot more than 3 loads as well. A delay of 2ns > and a skew of 1ns is fine for this clock. Do you want to post some code? > Anyway, if this makes any sense to you, post back, and we can talk about > the timing constraints you need to set! > HTH, Syms. Masterclock has a high fanout, about 100. I have replicated 2 times the clock pulse at 1MHz and the state machines to verify if it could low the fanout. I have obtained that every replicated clock (the pulse at 1 MHz) used to drive a state machine has a load equal to 3. I have tried now avoiding replication hardware and BUFG connected to clock pulse. In this way clock pulse at 1MHz hs a load of 7. There are skew 1ns and delay 2,5ns. I have made lots of experiments because I thought the main trouble could come from that. If I want update every channel, I should send 4 words of 16 bits and 4 ChipSelect. (I have made lots of post-place simulations and everything is ok). I have sent them and not every channel is updated. Which channel depends on level of optimization. If I try to update the out of only one channel (sending 500-1000 16-bit datas sequentially to DAC) the system works well. It seems doesn't accept a sequential update of different channels. I'm sure to wait the time needed to update a single channel. I have verified it. Could be a trouble depending on DAC and not from my logic? In example the control unit which read what channel to update and configure the nultiplexer? Many and many thanks for your precious answer MarcoArticle: 90247
Hi Bill,
Sorry, but your circuit is not good. In fact it wastes some FFs and logic to
make the metastability performance worse by many orders of magnitude. The
time from b to q in your circuit is half a 24MHz clock period. The OR gate
eats up some of this time. This is much better:-
process(clk_24M)
begin
if rising_edge(clk_24M) then
a <= d;
q <= a;
end if;
end process;
The signal 'a' has a whole 24 MHz period to settle. In your UCF file, do
this:-
NET "a" MAXDELAY = 1ns;
This is just to make sure the router doesn't screw up.
Have you taken Philip's advice and read
http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm ?
Also, re-read Bob's post. He's explained very well why your circuit isn't
good, and your latest modification doesn't address the concerns he
expresses.
HTH, Syms.
Article: 90248"Marco" <marcotoschi@nospam.it> wrote in message news:di5hbd$i0i$1@news.ngi.it... > > > Masterclock has a high fanout, about 100. > I have replicated 2 times the clock pulse at 1MHz and the state machines > to verify if it could low the fanout. Why do you want to lower the fanout? Have you connected the clock pulse at 1MHz to the clock input of any FFs? If you have, this is your mistake. It should only connect to the CE pins. The clock pins of *ALL* your FFs should connect to the 50MHz masterclock. Cheers, Syms.Article: 90249
Bill wrote: > 2.) If one of the flip-flop outputs are metastable then the OR-gate says > 1 or 0 (if one of it's inputs is metastabel). This problem is that an OR gate which could do this absolutely reliably would require either infinite gain or infinite propogation delay. Using real components without infinite gain, the OR gate will have an small analog range of input voltages where the gain won't be enough to drive the output load to either a "1" or "0" in only a few nanoseconds. In fact, since an OR gate does not have internal positive feedback as does the preceeding flip-flop, it may actually slow down the resolution of any metastable transition states. It's usually better to omit the OR gate and thus provide more settling time into the next register. I wouldn't doubt that if you could build a fast infinite gain OR gate, you could also use it, not only to design synchronizers, but to design perpetual motion machines. IMHO. YMMV. -- rhn A.T nicholson d.O.t C-o-M
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