Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thanks Tim..appreciate your help...but I am having problems coding the SR latch in VHDL. You think you can help me out with that.. Thanks againArticle: 92026
A pure RS latch (of the NOR variety) follows (Verilog) module RS (A,B,Q,nQ); input A; input B; output Q; output nQ; wire Qinternal; wire nQinternal; assign Q = Qinternal; assign nQ = nQinternal; assign nQinternal = !(A | Qinternal); assign Qinternal = !(B | nQinternal); endmodule The truth table is: A B Q nQ 0 0 P nP 1 0 1 0 0 1 0 1 1 1 0 0 (F) Where P is the Previous state (no change) F is forbidden (you should catch it somehow) Note that this is a direct model of a NOR gate RS latch. Cheers PeteSArticle: 92027
and here's the functional model
module RSfunctional (A,B,Q,nQ, RST);
input A;
input B;
output Q;
output nQ;
always @ (A or B or RST)
begin
if(RST)
begin
Q = 0;
nQ = 1;
end
else if(A & !B & !RST)
begin
Q = 1;
nQ = 0;
end
else if(!A & B & !RST)
begin
Q = 0;
nQ = 1;
end
end
endmodule
with the advantage of ignoring the forbidden state and the no change
state. You could set a constraint (or code) to force nQ to start high
instead of using a reset signal.
I have included the !RST statements for clarity only.
Cheers
PeteS
Article: 92028Chintan One simple way of encoding this is to use one of the signals as clock the other as an asynchronous reset as follows if STB = '0' then INTR <= '1'; STATUS_REG(2) <= '1'; elsif RD'event and RD = '1' then INTR <= '0'; STATUS_REG(2) <= '0'; end if; You can can chop this about to suit yourself. Generally in old style logic like this the timing of the interfaces like these are so slow that there are not any issues but do check the timing of the signals to avoid glitch situations etc. There are other ways to do this including using an independent clock (taking care over metastability issues), or by generating a clock using a logic function of both signals. This later method I wouldn't recommend without a very full understanding the issues of gated clocks and how to lock down logic in a FPGA. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan-3 Development Board. http://www.enterpoint.co.uk "Chintan" <cvdagli@yahoo.com> wrote in message news:1132447600.956881.301650@g49g2000cwa.googlegroups.com... > Hi, > I am designing a peripheral interface IO chip which is also the Intel > i82C55 chip. THe problem I have is I want to change a interrupt signal > INTR to '1' at the rising edge of a strobe input (STB) and then later > change INTR to '0' when the read signal (RD) arrives (at the rising > edge of RD). My VHDL code is > > handshaking: process(STB, RD) is > begin > if rising_edge(STB) then > INTR <= '1'; > STATUS_REG(2) <= '1'; > end if; > > if rising_edge(RD) then > INTR <= '0'; > STATUS_REG(2) <= '0'; > end if; > > end process; > > It seems that this is a bad synchronous design. So, how can I change > my INTR signal to respond to STB and RD signals? > Any help is highly appreciated... > > THank you all >Article: 92029
Hi All!
I have a project that use Altera Stratix II 2S180 as ASIC prototype.
Because the ASIC
has too many interface therefor too many clk and some of the clk does
not route to
fpga's dedicated clk pin ,for eg, pci clk does route to an normal I/O
pin .
Because the fpga and the board expensive,the BOSS does not want to make
a new board.
After I read throught 2S180's datasheet and throught a lot ,I found
this is a very hard problem because :
1 ) Global buffer tree's delay is very long , about 5ns.
2 ) From PAD to core , normal I/O has about 1ns's delay,
3 ) I can't use PLL to compensate I/O delay or global buffer delay
since PLL's input must
be a clk input pin or a global buffer.
4) Inserting LCELL into datapath of input signal will make my Tco
bad.
How can I deal with this ? Is altera here ?
Article: 92030It sounds like you just hit the classic ASIC to FPGA conversion problem of too many clocks. We have done a lot of this kind of work and generally it is best to plan FPGA use into the the IP from the start to make the conversion path easy. One thing to do to try and do is obviously to try and reduce the numbers of clocks. Often ASIC designs will use gated clocks because it makes for smaller logic than having local clock enabled flip-flops. Often this does create designs with large numbers of clocks which does not sit well with most FPGA fabrics. Xilinx do have some tool support for locally routed clocks to cover this situation but I am not sure if Altera can offer this facility as yet. Consider if you can alter your IP to use clock enables instead of a generated gated clock/s. Alternative if you board has multiple FPGAs look at partitioning to minimise the numbers of clock or to improve the distribution against your FPGA resources available. Often using a multiple FPGA platform is superior to using a single large FPGA based platform for ASIC prototyping. John Adair Enterpoint Ltd. - Home of Broaddown1. The ASIC Prototyping Platform. http://www.enterpoint.co.uk "huangjie" <huangjielg@gmail.com> wrote in message news:1132486415.614548.139310@g49g2000cwa.googlegroups.com... > Hi All! > > I have a project that use Altera Stratix II 2S180 as ASIC prototype. > Because the ASIC > has too many interface therefor too many clk and some of the clk does > not route to > fpga's dedicated clk pin ,for eg, pci clk does route to an normal I/O > pin . > > Because the fpga and the board expensive,the BOSS does not want to make > a new board. > After I read throught 2S180's datasheet and throught a lot ,I found > this is a very hard problem because : > 1 ) Global buffer tree's delay is very long , about 5ns. > 2 ) From PAD to core , normal I/O has about 1ns's delay, > 3 ) I can't use PLL to compensate I/O delay or global buffer delay > since PLL's input must > be a clk input pin or a global buffer. > 4) Inserting LCELL into datapath of input signal will make my Tco > bad. > > How can I deal with this ? Is altera here ? >Article: 92031
Another way to do this (I've used it successfully) is to resync the signal for instance reg EXT_INT; // from the external interrupt pin reg INT_INT; // a synchronised version of that signal reg INT_RD; // Synchronised internal read signal .... always @ (posedge clk) begin EXT_INT <= INTR; // grab the external signal if(INTR & EXT_INT & ! INT_RD) begin INT_INT <= 1'b1; // raise internal interrupt if the external signal is still present end if (INT_RD) // on a read cycle... begin INT_INT <= 1'b0; // always reset the latch end end Note that an interrupt latch is inhibited during a read cycle to prevent a race condition. The sync above will a) get rid of runt pulses and b) ensure the internal signal is synchronised properly to the clock. There's a possibility of missing an interrupt only if it's present during a read cycle AND it disappears before the end of that cycle, but that would be unusual. This also changes the pin sensitivity to level sensitive rather than edge sensitive, in a strict sense of the term, although in practise you are getting edge sensitivity delayed by at least one clock. Cheers PeteSArticle: 92032
Thank you for your replay ! But the board is built before I enter the company and the BOSS does not want to make a new board. The ASIC has too many clock just because tt has too many interface but not gated clock.Article: 92033
huangjie wrote:
> Because the ASIC has too many interface therefor too many clk and some of
> the clk does not route to fpga's dedicated clk pin ,for eg, pci clk does route to an > normal I/O pin.
How fast are the clocks that are not on the dedicated clock pins? If
they are slow enough, you can sample them with a faster clock to
generate an enable signal on the edge you want, and run your internal
logic on the faster clock using that enable. The code would be
different for your FPGA vs. your ASIC though:
FPGA:
process (fastclk)
begin
if RISING_EDGE(fastclk) then
if enable = '1' then
...
ASIC:
process (pinclk)
begin
if RISING_EDGE(pinclk) then
...
(It's for situations like this that I wish VHDL had a pre-processor
like C)
It might be tricky at PCI speeds, but if this is a prototyping system,
you may be able to slow down your PCI clock.
Regards,
John
Article: 92034Unfortunatly,the clock does not slow enough,eg, one at 125M,pci at 33MHZ. Since they are interface to other device they can't slow down.Article: 92035
Can someone point me to a refernce on how to use the generated time specs generated by the Xilinx Translate progman. Example INFO:XdmHelpers:851 - TNM "GCLK1", used in period specification "TS_GCLK1", was traced into DCM instance "pci_clk_gen/DCM_inst". The following new TNM groups and period specifications were generated at the DCM output(s): <none> (no matching synchronous elements driven by DCM outputs) INFO:XdmHelpers:851 - TNM "GCLK1", used in period specification "TS_GCLK1", was traced into DCM instance "pci_clk_gen/DCM_inst2". The following new TNM groups and period specifications were generated at the DCM output(s): CLKDV: TS_pci_clk_gen_Clock40M=PERIOD pci_clk_gen_Clock40M TS_GCLK1*2.500000 HIGH 50.000000% CLKFX: TS_pci_clk_gen_Clock240M=PERIOD pci_clk_gen_Clock240M I want to use the timing spec "TS_pci_clk_gen_Clock40M" in my UCF file to group FFS in a FROM-TO statment. I'm sure this is covered somewhere, i'm just have a hard time finding usefull stuff.Article: 92036
Nevermind, i had missed a semicolon (;) at the end of the previous line, and i thought the error was due to "TS_pci_clk_gen_Clock40M" not being defined. If anyone is interested, here is an example UCF snippet NET "EMIF_inst/WBM_ACK_I" TNM=FFS wbm_inputs; NET "wbs_slave_ram_inst/wbs_control_ram_inst/wb_ack_o" TNM=FFS wbs_outputs; TIMESPEC "TS_pci_clk_gen_Clock40M" = FROM "wbs_outputs" TO "wbm_inputs" 25 ns;Article: 92037
So clock everything at 125 MHz and use clock enables. Then use FIFO's or the infamous double latch to transfer between the 33MHz and 125Mhz clock domains. Simon "huangjie" <huangjielg@gmail.com> wrote in message news:1132535246.171569.78800@f14g2000cwb.googlegroups.com... > Unfortunatly,the clock does not slow enough,eg, one at 125M,pci at > 33MHZ. > Since they are interface to other device they can't slow down. >Article: 92038
> What development tool platform are you working with and what is your > target device? > my target device is Spartan3, xc3s400. > This is unless your assignment is to hand synthesize the code as part > of an assignment in a VLSI or some other class. i'am an intern in a company and have developed many small projects and currently studying how to use synthesis. thought if i can get links wer the steps are mentioned in which i can learn how to synthesise my code. thanks ByeArticle: 92039
> I'm still looking for a Verilog editor that will match BEGIN
> and END blocks just as they do parenthesis and braces. :-(
FWIW the Zeus editor will do this :)
It's Verilog configuration comes with brace matching for these
pairs of matching keywords:
begin attribute case function module task
end endattribute endcase endfunction endmodule endtask
So for example if the cursor is on or at the end of the endattribute
keyword, the Edit, Find Matching Brace menu will find the matching
attribute keyword.
Note: The Zeus configuration assumes the file extension for a Verilog
file is V and like all most things in Zeus this can easily be
configured.
Jussi Jumppanen
Author: Zeus for Windows
http://www.zeusedit.com
Article: 92040Q: I'm making a FFT block in hardware (on an FPGA) and I need some advice on multipliers: 1. I have made a simple (Fixed point arithmetic) Radix-2 Decimation-in-time butterfly block which takes in two 16-bit complex inputs and another 16-bit input twiddle factor input and produces two complex outputs. Now with any standard multiplier circuit, multiplying N bits by N bits gives 2N bit products. However, as twiddle factor terms are actually Cos()/Sin() terms i.e. lesser than or equal to 1, one should expect the same no. of bits in the output as in the input. So what I've done is that I've made a multiplier circuit which simply neglects (or masks off) N bits from the 2N bit result. This way I can make a single butterfly which can be cascaded to give 2^n sized (larger) FFTs. I just wanted to confirm if I'm on the right track... Am I forgetting something in my implementation or is this sufficient ? 2. Newer FPGAs have multipliers/arithmetic-circuits built into them. Is there anyway to exploit these internal features without wastage, such as by masking the higher bits ? Thank you, Satpreet IndiaArticle: 92041
Thank you Austin. I have to try, but the application note depicts exactly my case. > Austin Leseawrote: http://www.xilinx.com/bvdocs/appnotes/xapp685.pdf > > See page 2. > > Austin > > seb_tech_fr wrote: > Hi Austin, > I use an V2P70, which is loaded at 76%. > I don't use any macro for DCM. Which one should I use? > > Concerning placement and routing, all constraints have been met. It's > possible that this part is not constraint enough... > > Additional information. When I use a lighter version of my design > (which is loaded at 20%), it works.. > > > Austin Leseawrote: > > 21127 would not cause what Sebastien is experiencing (on V4), > > That concerns itself with a lower than 500 MHz possible CLKIN if the > > > device has been baked at high Vdd AND high temperature (see the NBTI > > > white paper). > > In actual fact, we saw this effect in HTOL testing with the > > production > > tester, but have never seen it in actual fact either on the test > > bench, > > or in any testing done by any customers. > > There is a suspicion that the testing done is far too tough, and the > > > problem only appears on the production tester (which tests to > 700 MHz, > with a +/- 100 MHz sampling) in its tests to ensure that the DCM > > will > > operate over all corners of the process, voltage and temperatures). > > > For any device with a DCM: > > More likely is that the placement of the DCM affects the timing of > > the > > paths that are used. > > Check all the constraints, and check to see that the global clock > resources are bring routed properly by looking at the design in FPGA > > Editor. > > For V2 Pro there are clock macros which are used to minimize the > possible skew from different DCM locations. If this is V2 Pro, then > > I > > could see this happening if the macros were not being used. > > Austin > > > > Symon wrote: > > Cher Sebastien, > What part are you using? Virtex4? Have you seen answer 21127? > HTH, Syms. > > "seb_tech_fr" > > sebastien.coquet@techway-dot-fr.no-spam.invalid> wrote in > > message news:G-SdnWildOwnJ-HeRVn_vA@giganews.com... > > Hi, > Does somebody know DCM corner issues? My DCM is not running at > > very > > high clock rate (only 107MHz), so I don't think this issue is > connected with XAPP685 application notes > > > [/quote:2c5a58d0bc][/quote:2c5a58d0bc]Article: 92042
Thanks for your suggestion ! But first ,how to use "the infamous double latch" ? second, my asic does not have only one 125M clk, instead it have 5 more , and all of them are input from external chip and have no any frequency or phase relations. Simon Peacock =E5=86=99=E9=81=93=EF=BC=9A > So clock everything at 125 MHz and use clock enables. Then use FIFO's or > the infamous double latch to transfer between the 33MHz and 125Mhz clock > domains. > > Simon > > "huangjie" <huangjielg@gmail.com> wrote in message > news:1132535246.171569.78800@f14g2000cwb.googlegroups.com... > > Unfortunatly,the clock does not slow enough,eg, one at 125M,pci at > > 33MHZ. > > Since they are interface to other device they can't slow down. > >Article: 92043
I would like to monitor the functionality of a state machine I have designed using ISE 7.1. Is there a way to retain the state names (i.e. reset_state,idle_state,run_state)in the modelsim post place and route simulation? I find it more convienient to see the state names than the values of the chosen fsm encoding type.Article: 92044
I find it frustrating that there is no way or telling if a compilation has ended or not. I can't find any feature in ISE which makes a sound when it's finished. I am aware that some might find this an annoying feature but would save me periodically checking to see if it's finished or come to an end early due to a mistake. Any ideas?Article: 92045
I'm worried that you might not have fully considered the tradeoffs you're proposing to make. Dynamic range and precision are very different. What do you mean by: "one should expect the same no. of bits in the output as in the input"? If you're imagining that there are going to be 16bits that are all zeros that you can happily chop off, then you will be sorely disappointed by what you see in the hardware. Both multiplicands could well use all 16 bits for precision. As long as they're correctly aligned, you can multiply the 2 numbers, keeping only the top 16 bits of your result. The magnitudes will be fine, but you will have lost a lot of precision. You'll have to watch out for overflow when you're summing the results of your multiplications. Again, when you do the additions, you'll have to discard the bottom bits of your results, in order to have 16 bit outputs for your butterfly. This sacrifice of precision (which is perfectly reasonable) will mean that there is a fundamental limit to the number of stages (and therefore the largest FFT) you can have. The error will accumulate and will at some point cause the results to breakdown. You could work this out mathematically, but I'm sure someone on this board must have done a similar thing as you've done and will be able to tell us how large an FFT you can perform using such a technique. All the above is given with the following caveats: 1. I'm new to this sort of thing. 2. I'm a notorious idiot. so if anyone can yay or nay the above, it would be helpful :)Article: 92046
satpreetsingh@gmail.com wrote: First off, you can't discard the high bits out of the multiplier. The twiddle factors, as you observed, are sines and cosines with nominal values between -1 and 1, however they are represented by moving the position of the implied radix point to the left end of the 16 bit value. The product, therefore has it's radix point also moved to the left by 16 bits. If 16 bits precision is sufficient (it won't be for larger FFTs), then you need to round off the lsbs of the product. You'll need to round symmetrically to avoid introducing a bias, as the FFT is sensitive to rounding bias. 16 bits precision is going to limit the size of the FFT as well as the precision of the results. The amount of limiting depends in part on the nature of the input, but I wouldn't expect to get much larger than about 256 points without getting substantial artifacts from the limited precision. You should model your application with a bit-accurate model to verify the noise due to internal truncation is not going to be a problem for your application before expending a lot of effort in the design.Article: 92047
On Mon, 21 Nov 2005 12:48:13 -0000, "Fred" <fred@nowhere.com> wrote: >I find it frustrating that there is no way or telling if a compilation has >ended or not. I can't find any feature in ISE which makes a sound when it's >finished. I am aware that some might find this an annoying feature but >would save me periodically checking to see if it's finished or come to an >end early due to a mistake. > >Any ideas? > I would also find this very useful - I was wondering if there was maybe a way to insert an extra program to go 'ping' into the list of executables that are run as part of the build process. I'd also really like to see an option to download to device on successful compilation.Article: 92048
On a sunny day (Mon, 21 Nov 2005 12:48:13 -0000) it happened "Fred" <fred@nowhere.com> wrote in <4381c20e$0$23287$db0fefd9@news.zen.co.uk>: >I find it frustrating that there is no way or telling if a compilation has >ended or not. I can't find any feature in ISE which makes a sound when it's >finished. I am aware that some might find this an annoying feature but >would save me periodically checking to see if it's finished or come to an >end early due to a mistake. > >Any ideas? I'd think that hanging a themocouple with level detector on the processor, or heat exhaust, was a nice lunch 'time project ;-) In Linux you could use grep or awk on the output of 'top': CPU states: 0.5% user, 2.7% system, 15.4% nice, 81.1% idle look for > X percentage idle, and use keyboard beep: echo -e "\a" ....Article: 92049
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:dlskc7$610$1@news.datemas.de... > On a sunny day (Mon, 21 Nov 2005 12:48:13 -0000) it happened "Fred" > <fred@nowhere.com> wrote in <4381c20e$0$23287$db0fefd9@news.zen.co.uk>: > >>I find it frustrating that there is no way or telling if a compilation has >>ended or not. I can't find any feature in ISE which makes a sound when >>it's >>finished. I am aware that some might find this an annoying feature but >>would save me periodically checking to see if it's finished or come to an >>end early due to a mistake. >> >>Any ideas? > I'd think that hanging a themocouple with level detector on the processor, > or heat exhaust, was a nice lunch 'time project ;-) > > In Linux you could use grep or awk on the output of 'top': > > CPU states: 0.5% user, 2.7% system, 15.4% nice, 81.1% idle > > look for > X percentage idle, and use keyboard beep: > echo -e "\a" > > .... > A utility to see if a file had been modified would be a possible method.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z