Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 98175

Article: 98175
Subject: Re: why use an FPGA when a CPLD will do ??
From: lb.edc@telenet.be
Date: Mon, 06 Mar 2006 22:05:22 GMT
Links: << >>  << T >>  << A >>
Simon,

I admit that X&A are controlling the FPGA market, but stating that
Flash based FPGA's are de facto not field Programmable is a bit of a
strong statement.
Both Actel and Lattice have flash based FPGA's, and Lattice provides a
technique not seen from X&A before. They call it TFR or TransFR, but
it is actually a manner of reconfiguring the FPGA while the system
operates. I have not seen this from the big players.
Maybe you will agree that in the telecom's world of today where five
nines or six nines is the buzz word, both Altera and Xilinx are
struggling to find an answer...

A humble FPGA designer

Luc


On Mon, 6 Mar 2006 21:14:49 +1300, "Simon Peacock"
<simon$actrix.co.nz> wrote:

>OK.. I admit there are a few minor players who have flash based or fuse
>based FPGA's.. but then they aren't by definition field Programmable are
>they?
>They are in fact very large CPLD's as a FPGA is a Field Programmable Gate
>Array and Fuse devices aren't field programmable (or at least are only
>one-shot) FLASH devices could be considered field programmable... but some
>can't be used while a new program is getting uploaded.  So that excludes
>them from what I would call Field Programmable.
>
>Although some people might disagree.. I believe that A&X do hold the lions
>share of the market so RAM based rocks for now... until nano-tube becomes
>the fad.
>
>Simon
>
>"Thomas Stanka" <usenet_10@stanka-web.de> wrote in message
>news:1141631210.694896.38720@u72g2000cwu.googlegroups.com...
>> Hallo,
>>
>> Simon Peacock schrieb:
>>
>> > There is also the issue that FPGA's configuration data is stored in
>external
>> > FLASH where as CPLD's are programmed.
>> > It is actually quite easy to reprogram a FPGA on the fly and field
>update
>> > the external memory while the FPGA is still running.  No special
>hardware or
>> > algorithms are required.  Downloading a CPLD is usually done from a PC
>via a
>> > JTAG cable or via a External Chip Programmer
>>
>> This is wrong. At least if you accept other fpga vendors beside Xilinx
>> *g*
>>
>

Article: 98176
Subject: Re: Which CPU and Screen Rez for ISE 6.3i ?
From: Eric Smith <eric@brouhaha.com>
Date: 06 Mar 2006 14:09:56 -0800
Links: << >>  << T >>  << A >>
Hendra wrote:
> Subject: Which CPU and Screen Rez for ISE 6.3i ?

How long is a piece of string?  It's more a matter of what you're going
to use ISE for, rather than any innate requirements imposed by ISE.  You
could just as well ask which CPU and screen resolution you need for C++
or Java development; there's no meaningful one-size-fits-all answer.

> 1. What screen resolution is the ideal one for ISE?

They don't make one with high enough resolution.  Get the best you
can afford.

> 2. Which screen resolution that you usually use at work?

1600x1200 (Samsung Syncmaster 213T 21" LCD).  I'm thinking about adding
a second of the same, since two of those together only costs about half
the price of a 1920x1200.

> 3. What is the ideal CPU speed and RAM if I limited my self to an FPGA
> less than 1.5 M gates with little constraint in the design.

As fast as you can afford.  I'm making do with an Athlon XP 3500+, with
1G of RAM.  Usually that's OK, but one of my designs takes six hours to
build if I crank up the timing-directed-map effort and P&R effort levels
to reach my timing constraints.  (I haven't yet tried PlanAhead.)  Most
of the time I can debug my design without doing that, though, since I
can run the prototype hardware at a lower clock rate than the target.

Article: 98177
Subject: Asynchronous FIFO design question
From: m.adithya@gmail.com
Date: 6 Mar 2006 14:25:37 -0800
Links: << >>  << T >>  << A >>
Hi,

     I have some problem detecting the full and empty conditions in an
asynchronous FIFO design. Hope any of you can help.

       Assume wr_clk is slower than the rd_clk. The rd_ptr is
synchronized to the wr_clk domain to generate the full flag in wr_clk
(slow) domain while the wr_ptr is synchronized to the rd_clk domain to
generate the empty flag in rd_clk (fast) domain.

 Say, on every 8th wr_clk, I generate a "wr_enable" signal. I write to
the FIFO and increment the write pointer whenever the "wr_enable" is
true. Assume the depth of the FIFO to be 4. I have written 3 FIFO
locations and my write pointer points to the last FIFO location at the
same time the 3rd location is written. Now when I write to the last
available (4th) FIFO location, full flag should be asserted. But now
when should it be deasserted?

 1. Whenever the read and write pointers are equal (irrespective of
"wr_enable" signal) or
 2. when the read and write pointers are equal and "wr_enable" is
true??

     Please direct if any of you have any good information on
asynchronous FIFO design. Also is it possible to synchronize pointers
from a faster clk domain to slowr clk domain?

Thanks
Aditya


Article: 98178
Subject: Re: Asynchronous FIFO design question
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 6 Mar 2006 14:31:31 -0800
Links: << >>  << T >>  << A >>
It would be good to say what chip you are using since
there are primitives in Xilinx for asynchonous FIFOs. 



Article: 98179
Subject: Re: Asynchronous FIFO design question
From: "Peter Alfke" <peter@xilinx.com>
Date: 6 Mar 2006 14:38:09 -0800
Links: << >>  << T >>  << A >>
EMPTY goes active as a result of reading, so the leading edge of EMPTY
is inherently synchronous to the read clock. No problem there. The
trailing edge of EMPTY is caused by writing, so it's inherently
synchronous to the write clock and it must be moved over to the read
clock domain. Moving between clock domains must accomodate potential
metastability, which usually means sacrificing some clock periods. But
that is usually not a problem. It just means the EMPTY signal stays
longer than absolutely necessary.
FULl is symmetrical, just exchange read for write etc.
Metastability is the potential problem of any asynchronous interface.
Peter Alfke, Xilinx Applications


Article: 98180
Subject: Re: Simulation of Xilinx Rocket IO
From: "MM" <mbmsv@yahoo.com>
Date: Mon, 6 Mar 2006 18:14:07 -0500
Links: << >>  << T >>  << A >>
Do you have SWIFT model support in your simulator?

/Mikhail


<kedarpapte@gmail.com> wrote in message
news:1141642621.274944.74110@p10g2000cwp.googlegroups.com...
> Hello All,
>
> I want to use Xilinx v2p or v4 rocket IOs in one of my designs.
> right now I am using Xilinx webpack 8.1 and modelsim se/pe.
>
>
> can any body tell me that if I generate a rocket IO instance (without
> 8b10b and crc) as a simple serdes How do I simulate it...?
>
>
> Does the Rocket IO Instance has any output pins for PLL Locked
> signals...?
>
>
> I am trying to simulate a transmitter by a simple test bench as to
> provide reset, clock and 8-bit parallel data, but nothing is coming out
>
> on serial tx pin.
>
>
> Please guide me .
> Thanks in advance.
>
>
> Regards,
> Kedar
>



Article: 98181
Subject: Re: Question for the EDK ppc users ...
From: "MM" <mbmsv@yahoo.com>
Date: Mon, 6 Mar 2006 18:19:59 -0500
Links: << >>  << T >>  << A >>
To your first question:

If I understand correctly OCM runs at the CPU clock and thus anything you
put on that bus will affect the max achievable CPU speed, at least that's
the impression I got when I actually tried implementing some big OCM
memory...  I believe most of the designs use PLB_BRAM controllers...

/Mikhail



<me_2003@walla.co.il> wrote in message
news:1141549248.324091.136550@p10g2000cwp.googlegroups.com...
> Hi all, my question is as follows,
> I am now going through a ppc design that I would like to run as follows
> :
> I need to use a internal BRAM for boot sequence and a NAND FLASH to
> contain all the code. the code will be placed and run on external SRAM.
> My question are as follows:
> 1) what should I choose as internal BRAM IF OCM or PLB_CTLR ?
> 2) Are there any better ways to design such a system ?
> Thanks in advance, Mordehay?
>



Article: 98182
Subject: Re: Asynchronous FIFO design question
From: m.adithya@gmail.com
Date: 6 Mar 2006 15:43:31 -0800
Links: << >>  << T >>  << A >>
Thanks for the information. But the problem I have got is that the
wr_clk is not free running. On my last wr_clk, I load the 4th location
of the FIFO and assert FULL. Remember that my next wr_clk can be at any
time which we never know. But in the mean time, if a read happens in
the rd_clk domain the trailing edge of FULL needs to be synchronized to
the wr_clk domain which is not possible till we see the next wr_clk. If
this FULL flag has to be reflected in my status register (this works on
rd_clk), what should my status bit be? Still high - as I have not yet
synchronized the trailing edge of FULL to wr_clk or
                                                   low - as in reality
the FIFO is not full.

P.S. This is to be used in a microcontroller.

Thanks

Aditya


Article: 98183
Subject: Re: Which CPU and Screen Rez for ISE 6.3i ?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 6 Mar 2006 15:51:00 -0800
Links: << >>  << T >>  << A >>

Eric Smith wrote:
> Hendra wrote:
> > Subject: Which CPU and Screen Rez for ISE 6.3i ?
>
> How long is a piece of string?  It's more a matter of what you're going
> to use ISE for, rather than any innate requirements imposed by ISE.  You
> could just as well ask which CPU and screen resolution you need for C++
> or Java development; there's no meaningful one-size-fits-all answer.
>
> > 1. What screen resolution is the ideal one for ISE?
>
> They don't make one with high enough resolution.  Get the best you
> can afford.
>
> > 2. Which screen resolution that you usually use at work?
>
> 1600x1200 (Samsung Syncmaster 213T 21" LCD).  I'm thinking about adding
> a second of the same, since two of those together only costs about half
> the price of a 1920x1200.
>
> > 3. What is the ideal CPU speed and RAM if I limited my self to an FPGA
> > less than 1.5 M gates with little constraint in the design.
>
> As fast as you can afford.  I'm making do with an Athlon XP 3500+, with
> 1G of RAM.  Usually that's OK, but one of my designs takes six hours to
> build if I crank up the timing-directed-map effort and P&R effort levels
> to reach my timing constraints.  (I haven't yet tried PlanAhead.)  Most
> of the time I can debug my design without doing that, though, since I
> can run the prototype hardware at a lower clock rate than the target.

Wow, how big are your designs?!

I guess I havent needed that much power cause I am using an XC3S200
FPGA. I am guessing you are using at least an XC3S500 or larger,
depending on your design?


Article: 98184
Subject: Hitech Global
From: "RobJ" <rsefton@abc.net>
Date: Mon, 06 Mar 2006 23:57:41 GMT
Links: << >>  << T >>  << A >>
Someone posted here about a year ago asking if anyone had experience with 
Xilinx development boards from Hitech Global (www.hitechglobal.com). He 
didn't get any responses on-list, so I'm asking again. Anyone dealt with 
this company and have anything good or bad to say about them?

Thanks,
Rob 



Article: 98185
Subject: Retiming a datapath
From: Alderaan <giovannibusonera@yahoo.it>
Date: Tue, 07 Mar 2006 01:20:25 +0100
Links: << >>  << T >>  << A >>
Hi, i've a problem using xilinx xst synthesis tool. I need to do the 
retiming of a combinatorial datapath.
I followed these steps:
1) I've described the datapath with an assign
2) I've connected three register (connected like a shift register) at 
the output of the assign
3) I've disabled the shift register extraction for these signals in xst
4) I've set retiming by register_balancing option.
When I synthesize my module xst is right because doesn't extract the 
shift register, but doesn't move the registers across the datapath in 
order to reduce the critical path. So the circuit is the same with the 
three register connected sequentiallu at the output of the assign.
What do i have to do in order to see registers moving?
Thankyou in advance
Giovanni

Article: 98186
Subject: Re: Vccaux regulator
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 07 Mar 2006 11:34:06 +1100
Links: << >>  << T >>  << A >>
On 6 Mar 2006 08:27:19 -0800, "Marco" <marco@marylon.com> wrote:

>Hi, I need someone more experinced to confirm me if the TPS54610 I have
>choosen for the 2.5V voltage supply of my Spartan3 will handle reverse
>current (that arises from using 3.3V signals on 2.5V dedicated pins
>like CCLK, TDI, TMS...). One the schematic of a Spartan3 evaluation
>board I saw an LM3475MF for this supply and this also should work
>without the need of a shunt Rpar resistor to avoid reverse current from
>entering the regulator. Please advice me on the TSP54610.
>Thanks, Marco

Commonly, switching regulators described as "synchronous" will both
source and sink current at their outputs. 

The data sheet says (in reference to high output voltages):
"The TPS54610 is  capable of sinking current continuously until the
output reaches the regulation set-point."

I've never used a switcher for VCCAUX though, only VCCINT.

Note that linear (i.e. series pass) regulators won't be damaged by
output voltages higher than the setpoint, however the output voltage
will  not be controlled by the regulator.

Regards,
Allan

Article: 98187
Subject: Re: what do the following constraints mean?
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 07 Mar 2006 11:37:24 +1100
Links: << >>  << T >>  << A >>
On 6 Mar 2006 10:56:32 -0800, "Subhasri krishnan"
<subhasri.krishnan@gmail.com> wrote:

>Hi all,
>I am trying to modify some code and I came across these constraints.
>'clk_in' is the input clock and 'clk' is generated using a DCM (its is
>the Divide By 2 output).
>
>NET "clk_in" TNM_NET = "clk_in";
>TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %;
>
>TIMEGRP "rising_ffs" = RISING "clk";
>TIMEGRP "falling_ffs" = FALLING "clk";
>TIMESPEC "TS_pos_to_neg" = FROM "rising_ffs" TO "falling_ffs" 5 ns ;
>
>Is there something wrong with the last FROM : TO statement? Can the
>same condition be specified using the Period statement? I think its
>supposed to mean "delay between the rising and falling edge is to be
>kept to 5ns".

It means "delay between the flip flops triggered by the rising edge
and flip flops triggered by the falling edge is to be kept to 5ns"
(more or less).
"flip flops" in this case is probably any edge triggered device, e.g.
flip flops, rams, SRLs, etc.


Note that this is really a duty cycle specification for the clock.

Regards,
Allan

Article: 98188
Subject: Re: Asynchronous FIFO design question
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 6 Mar 2006 16:54:00 -0800
Links: << >>  << T >>  << A >>
Hi,
"Simulation and Synthesis Techniques for Asynchronous FIFO Design with
Asynchronous Pointer Comparisons" by Clifford E. Cummings and Peter
Alfke is very detailed in code and it teaches how to design a
sophisticated asynchronous FIFO with thorough details.
Clifford E. Cummings website address is: www.sunburst-design.com. You
may download the paper from the website. 

Weng


Article: 98189
Subject: Terminologie/knowledge issu
From: thomas.b36@gmail.com
Date: 6 Mar 2006 18:08:12 -0800
Links: << >>  << T >>  << A >>
Hi all,

What's that mean : "Low Level Verification of ASIC Soc"?. The SoC
should be tested on development board containing FPGA, CPU and so. In
this cas how would you proceed using C programming?. Do one need to be
proficient in C prog or just fonctional C will do?.

Thank for your precious time Gentlemans and Ladies.

Thomas.


Article: 98190
Subject: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
From: "Identity Hidden" <hidden@dragon.com>
Date: Tue, 7 Mar 2006 10:20:59 +0800
Links: << >>  << T >>  << A >>

"Steve Lass" <lass@xilinx.com> wrote in message
news:dugco2$83l1@cliff.xsj.xilinx.com...
> I am responsible for the partial reconfiguration software.  Let me try
> to answer all of the questions posted:
>
> Q: Does the released ISE software support partial reconfiguration?
> A: In some cases, yes.
>
> Q: Does anyone have a commercial product that successfully employed
> partial reconfig?
> A: Yes, there are a few.
>
> Q: Why did Xilinx say partial reconfig worked when most of the time, it
> doesn't?
> A: We released software for partial reconfig about 4 years ago.  At that
> time, there was a flow that worked if you did everything in the right
> way.  There were a couple of people in my group that were assigned to
> help customers through the mine field.  It was rare that our sales force
> told us about customers using partial reconfig, so we assumed that
> nobody was using it.  Because of other priorities, and the apparent lack
> of interest, the partial reconfig software languished.
>
> Q: Is there a killer app that will drive Xilinx to put the effort needed
> to make partial reconfig a workable flow?
> A: Yes.  There are software defined radio applications that are
> lucrative enough to get our attention.
>
> Q: Does Xilinx now have software that works for partial reconfig?
> A: Yes.  We have a team that has modified the current software, created
> a new flow, and tested the software with different applications.  In
> addition, PlanAhead makes it much easier to lay out your design and run
> DRCs to ensure that partial reconfig will work.
>
> Q: How do I get this software?
> A: Contact your local FAE.  If you're at a university, contact the
> university program.  Our Xilinx Labs research department is supporting
> the universities.
>
> Q: Why don't you release the software with ISE?
> A: The plan is to release it with ISE in version 9.1i.  For now, we have
> an efficient team assigned to refine the flows and fix bugs as soon as
> they are found.
>
> Q: Is frame reconfiguration really cool?
> A: Yes.  However, Virtex2 and Virtex2-Pro together with our new software
> let you do what could be considered a partial frame write.  Even though
> you are writing the entire frame (column), Virtex devices don't glitch
> when you write exactly the same config bits.  This allows you to have
> static logic above or below a reconfig region.  We reconfigure the
> static region, but it continues to work.  This also allows us to have
> static routes that pass through a reconfig region.  The software
> reserves these routes when routing the reconfig region.
>
> Q: The software license fees are $3k - $5k.  How can we use this for
> reconfigurable computing?
> A; I'm not sure where these prices came from.  If you are creating a
> reconfigurable computer, contact me and we can discuss an OEM deal for
> much less money.
>
> Q: Should I feel comfortable adding partial reconfig to my current
> application?
> A: Personally, I would wait a couple of months.  We are currently
> rolling out the software to our SDR customers and will be spending our
> effort supporting them.  In addition, many of the FAEs have not been
> trained on the new partial reconfig flow.  And they are the first line
> of support.
>
> Steve
>

That's nice, I guess I will give our discontinued SDR project another
chance.
What is the estimated time of ISE 9.1i release?




Article: 98191
Subject: Re: Which CPU and Screen Rez for ISE 6.3i ?
From: Eric Smith <eric@brouhaha.com>
Date: 06 Mar 2006 18:52:29 -0800
Links: << >>  << T >>  << A >>
I wrote:
> As fast as you can afford.  I'm making do with an Athlon XP 3500+, with
> 1G of RAM.  Usually that's OK, but one of my designs takes six hours to
> build if I crank up the timing-directed-map effort and P&R effort levels
> to reach my timing constraints.

Isaac Bosompem wrote:
> Wow, how big are your designs?!
> 
> I guess I havent needed that much power cause I am using an XC3S200
> FPGA. I am guessing you are using at least an XC3S500 or larger,
> depending on your design?

Yes, I'm using an XC3S500.  That particular design currently uses about
half of the resources of the part.  Normally a design that small doesn't
take that long to compile, but this particular one has some very large
combinatorial functions (the PLA I brought up in another thread).

Article: 98192
Subject: Re: Asynchronous FIFO design question
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 6 Mar 2006 19:42:42 -0800
Links: << >>  << T >>  << A >>
This is a tricky problem. That's why all my designs require
free-running clocks.
How deep is your FIFO, and how fast is your design ( clock-to-clock
delay) and what FPGA device type or family are you targetting?
Also remember, a properly-designed FIFO should never go FULL. When it
is full, it has lost its fundamental function, to act as an elastic
buffer, or shock absorber. A FIFO should always be deeper than
necessary.
If it ever goes FULL, you can perhaps treat that as an emergency
situation. But it still requires some design finesse.
Please give more information.

Peter Alfke, Xilinx Applications (from home)


Article: 98193
Subject: A few questions about FPGAs
From: mahurshi@gmail.com
Date: 6 Mar 2006 19:59:55 -0800
Links: << >>  << T >>  << A >>
I had two basic questions about FPGAs and I wanted to know what you
guys thought about those:

1.  Are FPGAs mostly PALs and PLAs ?

2.  For large designs, how is the timing analysis done on FPGAs?  Is it
done using the libraries for the standard cells used or is it done only
after the code is synthesized "for" the FPGA (which makes more sense)


Mahurshi Akilla


Article: 98194
Subject: Re: DMA and PCI in SoPC Builder
From: brendan.rankin@gmail.com
Date: 6 Mar 2006 20:01:13 -0800
Links: << >>  << T >>  << A >>
Martin,

While it is true that the PCI Compiler can generate PCI interrupts, it
cannot manage Avalon (SOPC Builder) interrupts.  So, while the PCI
Compiler can generate PCI interrupts, I don't believe there is a way to
associate this to Avalon/SOPC Builder IRQs.  I think that you can
generate PCI interrupts on other Avalon/SOPC Builder "events", just not
interrupts.

It's a simple oversight, with a pretty simple workaround.  If you need
help with it, please contact me directly (via e-mail).

What do you plan to connect via PCI?  Just curious.

Cheers,

- Brendan


Article: 98195
Subject: Microblaze multiplier Virtex2pro vs. Spartan3e
From: "Alan Nishioka" <alan@nishioka.com>
Date: 6 Mar 2006 20:29:06 -0800
Links: << >>  << T >>  << A >>
If I compile my Microblaze project for Virtex2pro, the compiler uses
the mul instruction (hw multiplier) as expected.
If I only change to Spartan3e and recompile, the compiler uses __mulsi3
(sw multiplier).

Why won't it use the hw multiplier in Spartan3e?

I am using ISE 7.1sp4, EDK 7.1.2, xc2vp4, xc3s250e

Alan Nishjioka
alan@nishioka.com


Article: 98196
Subject: Re: Microblaze multiplier Virtex2pro vs. Spartan3e
From: "Alan Nishioka" <alan@nishioka.com>
Date: 6 Mar 2006 20:41:52 -0800
Links: << >>  << T >>  << A >>
Alan Nishioka wrote:
> If I compile my Microblaze project for Virtex2pro, the compiler uses
> the mul instruction (hw multiplier) as expected.
> If I only change to Spartan3e and recompile, the compiler uses __mulsi3
> (sw multiplier).
>
> Why won't it use the hw multiplier in Spartan3e?

Never mind.  I just noticed a missing -mno-xl-soft-mul flag from the
Spartan3e compile.
I think it is a bug in EDK that it is missing from the EDK generated
command, however.

Alan Nishioka


Article: 98197
Subject: Re: Simulation of Xilinx Rocket IO
From: kedarpapte@gmail.com
Date: 6 Mar 2006 21:14:24 -0800
Links: << >>  << T >>  << A >>
yes Modelsim SE has the swift model support, I am using that

but I am not able to get how  do I get this smart or swift models....?
I tried everything which is listed on xilinx web site.
but couldn't get it worked.

Please give me some info if you have it...

Thanks & Regards,
Kedar


Article: 98198
Subject: Internal Signals in OPB EMC In XIlinx PLatform studio
From: sachink321@gmail.com
Date: 6 Mar 2006 21:24:29 -0800
Links: << >>  << T >>  << A >>
HI
how would i use internal signals in XPS for microblaze on spartan 3
fpga board.

let me explain my project
in opb_emc
im using 2 memory banks
so im having two Output enable signals
but i have only one external pin
so i need to AND these two output signals and produce a single output
this output will be given to the external signal.

but i cant understand how can we produce a logic
for these internal signals?

any ideaz


Article: 98199
Subject: Re: Question for the EDK ppc users ...
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Mon, 06 Mar 2006 21:52:54 -0800
Links: << >>  << T >>  << A >>
OCM runs at an N:1 ratio of the CPU clock where N={1,2,3,..[see OCM docs 
for max. divider]} and, with that, does not affect the maximum CPU 
frequency.

- Peter


MM wrote:

> To your first question:
> 
> If I understand correctly OCM runs at the CPU clock and thus anything you
> put on that bus will affect the max achievable CPU speed, at least that's
> the impression I got when I actually tried implementing some big OCM
> memory...  I believe most of the designs use PLB_BRAM controllers...
> 
> /Mikhail
> 
> 
> 
> <me_2003@walla.co.il> wrote in message
> news:1141549248.324091.136550@p10g2000cwp.googlegroups.com...
> 
>>Hi all, my question is as follows,
>>I am now going through a ppc design that I would like to run as follows
>>:
>>I need to use a internal BRAM for boot sequence and a NAND FLASH to
>>contain all the code. the code will be placed and run on external SRAM.
>>My question are as follows:
>>1) what should I choose as internal BRAM IF OCM or PLB_CTLR ?
>>2) Are there any better ways to design such a system ?
>>Thanks in advance, Mordehay?
>>
> 
> 
> 




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search