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Hi everyone,
I am newcomer of the FPGA business and I am doing some investigation on
the Cadence DFWII package that run on the Sparcstation along with Xilinx
stuff. I am very inexperience in this area and would be grateful for
someone to comment the setup here and it performance and it stability. It
would be useful if someone outline the general purpose process in
converting VHDL to codes before programming a Xilinx chip via programmer.
Could someone comment on what kind of extension modules that can be put
together along the DFWII system?.
Thank you
,,, ||| \|/
)(- -)( )(* *)( )(o o)(
___________ooO_(_)_Ooo_____IoO_(_)_OoI_____ooO_(_)_Ooo____________
|_______ ______|
|_____ Richard Payne A electronic/computer nerd with Big Ear! ____|
|____ E-mail only rgpayne@albert.hep.ph.ic.ac.uk ___|
| Imperial College, Dept of Physic, London SW7 2BZ |
|__________________________________________________________________|
_() ()_ _() ()_ _() ()_
(__) (__) (__) (__) (__) (__)
Article: 901In article <3kr34e$ja4@src-news.pa.dec.com> murray@src.dec.com (Hal Murray) writes: > >What sort of chips do people use to implement old fashioned uCode machines? I'm >thinking about the type of thing you build with a wide ROM, a register to hold the >instruction, another register to hold the PC, and a PAL or such for the branch logic >in the bottom bits of the PC. > >The main reason that I say "uCode" is that I'm interested in a large number of >states rather than the relatively simple state machines that you build out of >gates and FFs. I want to "write the code" as though it were a software problem >rather than drawing circles and arrows. > >The Altera EPS448 is an interesting chip for that sort of machine. It combines >the ROM and registers and branch logic in a single chip. You get 8 branch bits in >and 16 instruction bit out in a PLCC28. (You are SOL if you need more uCode >space.) The PC (ROM address) is burried inside the chip. > >Anybody know any modern chips like it? Any FPGAs good at that sort of thing? Another family to look at is the AMD 29CPL14x and 29CPL15x parts. They have control store on chip like the EPS448, but have a somewhat more sophisticated sequencer. Waferscale also has a product in this area called the PAC1000. It includes a register file and ALU, so is more like a CPU. Recently I needed to design a state machine for one of my clients, that needed hundreds of states, and depending on operation mode of the system, the state machine would need to be changed between litteraly hundreds of different possible sequences. My solution was a uCode style state machine built entirely within a Xilinx XC4010, with a write port into the uCode RAM, that was controlled by a host processor (80486 PC). The host would calculate the modifications needed to a baseline uCode, and then write (or for speed, 'patch') the uCode RAM in the FPGA. It would then run the uCode. I also included some control bits that the host could use to halt and single step the uCode engine. The host is also able to read back the current contents of the pipeline register, as well as preloading the PC. The preloading of the PC allows me to load several different sequences into the memory at one time, and rapidly select them. The write/patch only happens when there is a major change in the operation mode. The uCode memory is 16 bits wide by 256 words deep. This uses about a quarter of the 4010. All the Best Philip Freidin, fliptron@netcom.comArticle: 902
I recently posted notice that I was starting an AT&T FPGA Mailing List for the UK only. However due to popular demand this is now being opened up to anyone. It will carry infrequent mailings predominantly based around the ORCA architecture but possibly 3000 series as well, they will include engineering & some commercial messages hence the list rather than postings to Newsgroups. If you want to be on it let me know. Regards, Ian Packer. Bytech Electronics Ltd.Article: 903
I'm a student working on building a PCI device using FPGAs for control logic and multiplexing. We need to operate at 100 MHz and we also don't have much power to budget for the FPGAs. What architecture is best suited for this situation? We've got some Actel data books that describe the power consumption using an equation with a lot of variables that we don't know, since we haven't actually written any code yet. I'm looking for ballpark figures for this kind of application that someone might have gleaned from experience. I was also told by a guy at TI that the Actel stuff is too slow for 100 MHz and that we should probably look at QuickLogic products. However, he also admitted that he was basing that statement on his experience of an old Actel architecture that TI licensed a few years ago. Thanks for any help, Ajit -- Ajit George gajit@rice.eduArticle: 904
In article <206@bloggs.win-uk.net> ipacker@bloggs.win-uk.net writes: "I recently posted notice that I was starting an AT&T FPGA Mailing "List for the UK only. " "However due to popular demand this is now being opened up to "anyone. "It will carry infrequent mailings predominantly based around the "ORCA architecture but possibly 3000 series as well, they will "include engineering & some commercial messages hence the list "rather than postings to Newsgroups. " "If you want to be on it let me know. " "Regards, "Ian Packer. "Bytech Electronics Ltd. " " Good idea, Ian. One comment, though. Why not post it all to this group as well? Given the topic of the group, surely knowing what FPGA vendors are doing is useful (vital?) info, rather than unwelcome advertising. It's a misconception that Usenet does not like to see commercial information when the group topic is a commercial product. I'd like to see all the vendors placing short, informative messages about new products and technical issues. If I've got this wrong, please let me know! :-) David Pashley Direct Insight Ltd.Article: 905
Hi, I am looking for internet data sites with information on ASICS of Analog Devices, TI, Intel etc. Both digital and analog. REAL information that I can use for designs. Can anybody tell me if there are such sites and where are they ? Please EMAIL me to s2929116@t2.technion.ac.il THANK YOU VERY MUCH! Lidor.Article: 906
> Subject: Need 100 MHz, relatively low power FPGAs > > I'm a student working on building a PCI device using FPGAs for control > logic and multiplexing. We need to operate at 100 MHz and we also > don't have much power to budget for the FPGAs. What architecture is > best suited for this situation? > > I was also told by a guy at TI that the Actel stuff is too slow for > 100 MHz and that we should probably look at QuickLogic products. > However, he also admitted that he was basing that statement on his > experience of an old Actel architecture that TI licensed a few years > ago. I am currently using TI/Actel 1240As and so far, I have found their true operating speed to be about 1/2 of the advertized top speed. Since my data rate is a mere 20 MHz, I thought I would have a lot of margin. But I find I do have to take pains to keep strick control over my loading and the I/O delays are a major consideration. For safety's sake, I will be using the higher speed grades in my actual implementation. Part of the problem may be due to the fact that I use the ALS router from TI/Actel; this is a fully automatic system which does not allow the user to see the routing, let alone manually tweak it. I have also discovered (and confirmed with TI) a horrible fact about the ALS: in fixed incremental mode, only the placement is fixed: the routing does get completely redone each time. (So much for predictability of delays!) I have been wondering if results would be better using Neocad. Can someone provide feedback on this issue? Which routing system are YOU considering using? For these reasons, I am stunned to hear that anyone is planning to use Actel parts for a 100 MHz design. Are you planning to use ACT2 XL parts or ACT3 parts? What is their availability status? My databook is dated 1994 and it lists ACT3 familly timing information as preliminary. Have you taken a good look at those I/O timing specs? It seems to me they will be your stumbling block. I have not used Quicklogic parts but from what I saw in their databook, it is also speed restricted by the I/O to rather less than 100 MHz! If you find a family which truly functions at 100 MHz, I would be VERY interested to learn which one. Please share the information! Good luck! Catherine Gyselinck ---------------------------- MPB Technologies | Speak softly but carry | gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | tel: (514) 683-1490 ---------------------------- fax: (514) 683-1727Article: 907
In article <GAJIT.95Mar26222616@little-star.rice.edu> gajit@owlnet.rice.edu (Ajit Kurian George) writes: >From: gajit@owlnet.rice.edu (Ajit Kurian George) >Subject: Need 100 MHz, relatively low power FPGAs >Date: 27 Mar 1995 04:26:15 GMT >I'm a student working on building a PCI device using FPGAs for control >logic and multiplexing. We need to operate at 100 MHz and we also >don't have much power to budget for the FPGAs. What architecture is >best suited for this situation? >We've got some Actel data books that describe the power consumption >using an equation with a lot of variables that we don't know, since we >haven't actually written any code yet. I'm looking for ballpark >figures for this kind of application that someone might have gleaned >from experience. >I was also told by a guy at TI that the Actel stuff is too slow for >100 MHz and that we should probably look at QuickLogic products. >However, he also admitted that he was basing that statement on his >experience of an old Actel architecture that TI licensed a few years >ago. Altera has a series of PCI compliant products. Wassail, MjodalfRArticle: 908
Some of the mails could be a bit long to post on the Newsgroup but maybe the short stuff would be OK if everyone is happy. So how does short messages posted even if commercial-ish & longer stuff direct mailed sound? Regards, Ian Packer. Bytech Electronics Ltd. >Good idea, Ian. > >One comment, though. Why not post it all to this group as well? >Given the topic of the group, surely knowing what FPGA vendors are >doing is useful (vital?) info, rather than unwelcome advertising. > >It's a misconception that Usenet does not like to see commercial >information when the group topic is a commercial product. > >I'd like to see all the vendors placing short, informative >messages about new products and technical issues. > >If I've got this wrong, please let me know! :-) > >David Pashley >Direct Insight Ltd.Article: 909
We are setting up a brand new laboratory for hardware development (mainly FPGA based designs, maybe VLSI designs in the future) and are selecting a workstation for running CAD software (Viewlogic and Xilinx tools at present). In this phase we are considering the IBM PowerPC worstations running AIX. These machine will be networked with a bunch of Suns, and we'd like to have all the machines in a NIS domain. I'd like to hear impressions from people using these machines in a similar design environment, as well as any advice on possible problems that we could have with these boxes. I also have some specific questions: 1) The 40P model has two PCI slots. Does this mean that I can put into it any off-the-shelf PCI card ? 2) Is it possible to attach to the SCSI adapter any SCSI disk? I'm asking this because I heard that the HP Gecko complains if one attempts to put a non HP disk in the SCSI chain. 3) Is it possible to compile and run plain MIT X in addition to AIXwindows ? 4) Has anyone had serious problems compiling popular free software like gcc, Emacs, ghostscript, TeX, etc. ? Thanks in advance, I will post a summary if there is enough interest. -- Arrigo Benedetti e-mail:benedett@caliban.dsi.unimo.it University of Modena graduate student bndm13k1@bologna.nettuno.it address: Via S. Agata 11 41100 MODENA - ITALY phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727 -- Arrigo Benedetti e-mail:benedett@caliban.dsi.unimo.it University of Modena graduate student bndm13k1@bologna.nettuno.it address: Via S. Agata 11 41100 MODENA - ITALY phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727Article: 910
Hi,
I have been trying to synthesize memory elements in the Xilinx
4000 series CLBs, without much success. I do know that it is possible
to configure each of the XC4000 CLBs either as a 32x1 RAM or a 16x2
RAM, however I could not get synopsys to generate the required
circuit. Can anyone who has had some experience in this particular
subject help me?.
Following is a small description I used to describe memory,
driving tristate buffers.
module memory (data,rd_wr, address, clock, enable);
input [4:0] address;
input rd_wr;
inout [1:0] data;
input clock,
enable;
reg [1:0] mema [0:31];
assign data = ((rd_wr)&& (enable))? mema[address]: 2'bz;
always @(posedge clock)
begin
if ((!rd_wr)&&(enable)) mema[address] <= data;
end
endmodule
The libraries I used as target and link libraries are:
link_library = { xprim_4005-4.db xprim_4000-4.db xgen_4000.db xio_4000-4.db xfpga_4000-4.db}
target_library = { xprim_4005-4.db xprim_4000-4.db xgen_4000.db xio_4000-4.db xfpga_4000-4.db}
symbol_library = { xc4000.sdb }
Thanx..
-Jatan
Article: 911I (or, rather, my company) just paid nearly $3K for Abel 6.0 for Windows and a fitter for Lattice PLDs. Now the Lattice devices look very nice - in-circuit programmable, good internal connectivety, and some other nice things. I couldn't find anything besides Abel in the $3K price range that would allow me to do equation/state-machine entry and target Lattice isp (if anyone knows of anything that fits this description, please let me know ASAP - note that I'm not really interested in schematic entry). Now I've only been using the software for a few days, so maybe I just haven't figured everything out yet, but I think I've been badly ripped off and I would strongly urge anyone else considering Abel to exhaust all other options first. My first problem has been with the hardware lock. It works ok on my laptop (which is a relatively slow 486SX/33 with 8MB RAM) but isn't recognized on my desktop (a 486/100 clone w/ 24MB RAM). My printer port is configured as a normal LPT port (no ECP or anything), and other keys work ok, but not this one. The place in Canada that sells the key-removal software said they couldn't help with Abel 6.0. It would be REALLY nice to be able to do things on my fast machine, since the software is Win32s and is SLOW. Ok, so I start using it on my laptop. Equation and state-machine entry is adequate. Hierarchy support is ok. Note all steps are slow, although this might improve dramatically with more memory. Simulation is the 'base' $3000 version is limitted to what they call Equation and JEDEC simulation. Basically you give it test vectors and it simulates the design to tell you if there's a match. As near as I can tell, though, there's no ability to do looping or any conditional stuff in the test vector section which would greatly simplify testing things like video waveform generators that have long (around 1000) clock periods. Even the ability to start the thing somewhere and just let it go for a while and view the output would be great, but I think that is considered 'Functional Simulation' and is thus only available via the very expensive Verilog simulator option. It looks like I could probably do something equivalent if I enter in a zillion vectors with lots of 'don't cares' on the outputs (although I haven't tried this yet), but I don't relish the thought of generating files of 1000 test vectors. If I'm way off base here, please let me know and I might take some of this back. I guess what I'm really pissed about is that my old freebie Intel PLDShell (still available on Intel's anonymous FTP) was both more capable (in terms of simulation abilities) and much faster (ran under DOS). And it was/is $3000 less!! Or look at Cypress' Warp2 that they're selling now for $99. Full VHDL along with a very nice FUNCTIONAL (but not detailed timing) waveform simulator for $99!! (Ok, so it also uses Win32s and is full of bugs.) So Data I/O has this incredible attitude when you call them like they're selling this fantastic product and you should be happy to pay list price. Call them about programmers and they just keep calling back and telling you how they'll cut you all these great deals (although they still weren't able to touch BP Micro - Data I/O was offering me a refurbished unit that was still more expensive than BP and then you pay all kinds of money for yearly algorithm updates - BP's are free). But ask them to move a little on the software and they act like you should ane happy to be able to buy it at all. (I've been told that the software and hardware groups are pretty much separate within the company. Either Synario is fantastic or they better keep craking out the programmers.) In closing: STAY AWAY FROM DATA I/O, ESPECIALLY ABEL!!! Jay Kubicky jkubicky@cco.caltech.edu PS: These experiences may very well push me over to the Altera MAX8000 camp. I think their software may be much better for around the same price. Lattice take note - get some decent entry-level tools. PPS: I almost forgot. They've also broken everything into pieces so it's like buying a car where you pay $20K base or $25K if you want it with tires. The base package is $2K. Then they charge you $300 for ONE YEAR of tech support. I guess they just dump your voice mail if you didn't pay up. Then you pay $500-$1K for a typical fitter (I got my Lattice fitter for $600 on sale). THEN you pay a few hundered MORE for some kind of funky thing that goes between Abel and the fitter. I'm not exactly sure what this is, because I don't have it yet, and I think it only applies to the Windows version of Abel (that is, Abel 6.0), but I know it's an extra thing, separate from the fitter, that you have to pay for. Data I/O really bites.Article: 912
In article o1j@gap.cco.caltech.edu, jkubicky@cco.caltech.edu (Joseph J. Kubicky) writes: > > Now I've only been using the software for a few days, so maybe I > just haven't figured everything out yet, but I think I've been > badly ripped off and I would strongly urge anyone else considering > Abel to exhaust all other options first. ALTHOUGH I'M THE FIRST TO ADMIT THE ABEL PRODUCT HAS IT'S FLAWS (SUCH AS POOR HANDLING OF X'S DURING SIMULATION - AND THERE IS A REASON FOR THAT), I HAVE BEEN A SATISFIED USER FOR MANY YEARS. I ROUTINELY USE IT FOR ALL PROGRAMMABLE LOGIC (AND FPGA) DESIGNS, SIMPLY BECAUSE IT IS MUCH MORE POWERFUL (AND YOU CAN PROGRAM AT A HIGHER LEVEL OF ABSTRACTION) THAT "COMPETING" PRODUCTS. ALTHOUGH I USE ABEL 5.0 ON A SUN WORKSTATION, SO AM NOT FAMILIAR WITH THE PC PRODUCT, I'D SUGGEST A DETAILED PERUSAL OF THE MANUAL MIGHT BE IN ORDER FOR JAY. > > Simulation is the 'base' $3000 version is limitted to what they > call Equation and JEDEC simulation. Basically you give it test > vectors and it simulates the design to tell you if there's a match. > As near as I can tell, though, there's no ability to do looping or > any conditional stuff in the test vector section which would > greatly simplify testing things like video waveform generators that > have long (around 1000) clock periods. BY USING MACROS, YOU CAN PERFORM ALL SORTS OF SIMULATION LOOPS. READ THE MANUAL AND LOOK AT THEIR EXAMPLE SOURCES. > > In closing: STAY AWAY FROM DATA I/O, ESPECIALLY ABEL!!! > I CAN'T CONDONE THIS ATTITUDE. ANY OTHERS WITH OPINIONS? > > Jay Kubicky > jkubicky@cco.caltech.edu > --- Paul Hunter phunter@mcc.com MCC / Austin, TXArticle: 913
Hi Arrigo, ... stuff deleted ... > > I'd like to hear impressions from people using these machines in a > similar design environment, as well as any advice on possible > problems that we could have with these boxes. > we are doing databases here, no CAD :-( > 1) The 40P model has two PCI slots. Does this mean that I can put into > it any off-the-shelf PCI card ? > I don't believe this, even if the card is electrically OK, you need the driver for AIX. Our RS6000 have Microchannel and i don't know of a PC-Card which runs. (Maybe i am not well informed about this subject). > 2) Is it possible to attach to the SCSI adapter any SCSI disk? I'm asking > this because I heard that the HP Gecko complains if one attempts to put > a non HP disk in the SCSI chain. We are using many non IBM Disks, they are relatively easy to install. Check before buying ! > > 3) Is it possible to compile and run plain MIT X in addition to AIXwindows ? > I am not shure but i think yes. > 4) Has anyone had serious problems compiling popular free software like gcc, Emacs, > ghostscript, TeX, etc. ? If you have problems, you can instruct xlc via xlc.cfg to behave more like BSD. The IBM-C compiler performes better than gcc (for me). Hope this helps, best regards, Toni +--------------------------------------------------------------------+ | Anton Dischner, DBA and system-programmer Phone: +49 89 70953202| | Institut fuer Klinische Chemie Fax : +49 89 70958888| | Klinikum Grosshadern Home : +49 89 6254060 | | Ludwig Maximilians Universitaet Muenchen Handy: +49 172 8388880| | 81366 Muenchen | | Marchioninistr. 15 | | Germany Mail: dischner@med.uni-muenchen.de| +--------------------------------------------------------------------+Article: 914
> Subject: Need 100 MHz, relatively low power FPGAs
>
> I'm a student working on building a PCI device using FPGAs for control
> logic and multiplexing. We need to operate at 100 MHz and we also
^^^^^^^
> don't have much power to budget for the FPGAs. What architecture is
^^^^^^^^^^^^^^^^^^^^^
OOOPS! You can cycle CMOS fast (i.e. high cycle rates), or you can get
low power, but not both at the same time! I hope you aren't counting on
using very many gates! (Assuming the FPGA can really do useful stuff
at 100 MHz, in the first place).
Do you ever wonder why 100+ MHz Pentia and Alphas CPUs burn 10-25 watts?
CMOS power is basically 0.5 * C * VCC^2 * MHz.
> best suited for this situation?
>
> I was also told by a guy at TI that the Actel stuff is too slow for
> 100 MHz and that we should probably look at QuickLogic products.
> However, he also admitted that he was basing that statement on his
> experience of an old Actel architecture that TI licensed a few years
> ago.
Don't forget to consider power consumption, the delays resulting from
intra-chip interconnect, package thermal characteristics, and in-system
device cooling. Make sure your "technology vendor" is providing you
with the information you need to verify that your application can work
in consideration of each of these factor. If you can't get the info
you need, pick another vendor! Some vendors require the designer to
take the approach of "if you have to ask, you can't afford it!"
Unless you're building a one-up circuit where you only
need to get one item working for a short time, in which case you *may*
be able to get away with just about anything!
Bob Elkind, Tektronix Tv Products
I don't speak for Tek in this case, just my own personal opinions.
Article: 915
AT&T FPGA #6 Application Notes
==============================
Having just received a new AT&T Literature Guide it seems like a good
time to pass on the list of available Application Notes. As per usual
if you're based in the UK and would like any of them let me know,
otherwise contact your local supplier.
As this is a fairly short it will also be posted on comp.arch.fpga as
suggested by one of the subscribers.
Lit No.
1) Designing High Speed >100MHz Counters AP94-001FPGA
using Linear Feedback Shift Registers
2) Designing a datapath circuit AP94-005FPGA
3) Implementing and optimising multipliers AP94-035FPGA
in ORCA FPGAs
4) ORCA FPGAs integrate Datacom's path AP94-042FPGA
5) ORCA FPGAs as DSP Coprocessors AP94-041FPGA
6) ORCA FPGAs in Multiplexing and on chip SRAM AP94-044FPGA
7) FPGA Maximums AP94-045FPGA
8) ISA Bus Plug & Play in an FPGA AP94-046FPGA
9) Implementing FIFOs in ORCA AP94-051FPGA
10) ATT3000 Test Methodology AP91-020CMOS
11) FPGA Migration (to Gate Array) AP92-004FPGA
PS: My apologies for my spelling in some previous mails, I don't have
a spell checker & type badly!
Article: 916My department where I work had also experienced poor customer service for Abel. We finally dumped it because of this and bought Minc. We've been much happier ever since. -- Bill McFadden Tektronix, Inc. P.O. Box 500 MS 58-639 Beaverton, OR 97077 bill@tv.tv.tek.com, ...!tektronix!tv.tv.tek.com!bill Phone: (503) 627-6920 How can I prove I am not crazy to people who are?Article: 917
In article <3kr34e$ja4@src-news.pa.dec.com>, murray@src.dec.com (Hal Murray) wrote: >This isn't a mainline FPGA problem, but somebody might have a good suggestion. > >What sort of chips do people use to implement old fashioned uCode machines? I'm >thinking about the type of thing you build with a wide ROM, a register to hold >the >instruction, another register to hold the PC, and a PAL or such for the branch >logic >in the bottom bits of the PC. > >The main reason that I say "uCode" is that I'm interested in a large number of >states rather than the relatively simple state machines that you build out of >gates and FFs. I want to "write the code" as though it were a software problem >rather than drawing circles and arrows. > >The Altera EPS448 is an interesting chip for that sort of machine. It combines >the ROM and registers and branch logic in a single chip. You get 8 branch bits >in >and 16 instruction bit out in a PLCC28. (You are SOL if you need more uCode >space.) The PC (ROM address) is burried inside the chip. > >Anybody know any modern chips like it? Any FPGAs good at that sort of thing? State Mahine PROMs may be used for storing a lot of states, although I have not yet used these proms. These proms are offered by Cypress Semiconductor Corporation as their codes of CY7C258/9. For more info, please call Cypress hotline below: 1-800-858-1810. Ask for Dept. CA15. -- Akinori Sugiura | Computer Hardware Engineering E-mail: sugiura@tcp-ip.or.jp | 4-8-19 Fujimidai Toyohashi Aichi Voice & Fax: +81-532-25-8374 | 441-32 JapanArticle: 918
has anyone dealt with, or have any information on, meta-systems of paris, france, who apparently have ASIC emulation technology based on a proprietary fpga ? any contact numbers, or email, would be useful. thanks, stephen smith sjsmith@ix.netcom.comArticle: 919
I dumped anything that even looked remotely like Data I/O several years ago. The constant need to upgrade and the ridiculous prices finally drove me away. Of all the hardware/software development tools I've ever bought, their's were the poorest value. I don't mind paying for upgrades, I just don't want to have to do it every time I want to use the tools. So far I've been able to find better, cheaper tools (hardware and software) so I haven't regretted it. Doug Hall doughall@nando.netArticle: 920
It is now confirmed from reliable sources that Xilinx has taken over Neocad this week to put an end to the competition for Xilinx P&R tools. -ASM.Article: 921
Joseph J. Kubicky <jkubicky@cco.caltech.edu> wrote: > (laments) >In closing: STAY AWAY FROM DATA I/O, ESPECIALLY ABEL!!! I haven't been working with PLDs lately, but I'm doing a lot of microcontroller work. I'll absolutely back you up on your DATA I/O opinions any time you like. I've used 'em, don't like 'em. I've got an EP-1140 from BP; no complaints. Last week I got a sample of the Atmel 89C2051; the EP1140 didn't support it. Called BP's 800 number and they patched it into the 1140 driver THE SAME DAY, called me to tell me I could get it from their BBS (also told me how to build the simple adapter socket it needs), _and_ followed up a couple of hours later to make sure it was working. And this is their FREE tech support! -- ------------------------------------------------------------- Gordon S. Hlavenka cgordon@vpnet.chi.il.us Warning! This post may contain a "stealth" .sig virus!Article: 922
I am interested in building an emulator for a microchip PIC16Cxx with a FPGA as a hobby project. I work at Carnegie Mellon University. Perhaps there is a staff/departmental starter deal? Is there an FAQ and/or archive for this list? Thanks, Aaron Wohl / ham callsign N3LIW / 412-731-3691 / 412-268-5032Article: 923
In article <3ldf7p$4cg@hustle.rahul.net>, ASM <someone@somewhere.com> wrote: > >It is now confirmed from reliable sources that Xilinx has taken >over Neocad this week to put an end to the competition for Xilinx >P&R tools. > >-ASM. Isn't NeoCAD supposed to be the sole source for the tools for both ATT and Motorola? I wonder how those development efforts are going to go now ... -- Steve -- 3/30/95Article: 924
ASM <someone@somewhere.com> writes: >It is now confirmed from reliable sources that Xilinx has taken >over Neocad this week to put an end to the competition for Xilinx >P&R tools. > >-ASM. April Fools? Please tell me this is a joke.
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