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Messages from 1275

Article: 1275
Subject: Re: Flex780 programming errors
From: Paul Walker <paul@walker.demon.co.uk>
Date: 25 May 1995 09:07:47 +0100
Links: << >>  << T >>  << A >>
In article <robc.801332006@appliedmicro.ns.ca>
           robc@appliedmicro.ns.ca "Rob Christopher" writes:

>I'm trying to program an Altera/Intel Flex780 through the JTAG port and
>most times get an error message from PLDShell's PENGN program.  I'm
>using version 3.5 on a PC.  The error code is 7041 and sometimes 7045 and
>my documentation (from version 3.1) only has the codes up to 7037.
>Anyone have a list of error codes above 7037?

The V5 book that arrived this week still only has codes listed up to 7037.

-- 
Paul Walker                 4Links for technical help
+44 1908 566253             P O Box 816, Two Mile Ash
paul@walker.demon.co.uk     Milton Keynes MK8 8NS, UK


Article: 1276
Subject: Re: altera vs xilinx ???
From: Lazarus@dl.ac.uk (Ian Lazarus)
Date: Thu, 25 May 1995 13:36:47 +0000
Links: << >>  << T >>  << A >>
In article <3pukf7$810@rc1.vub.ac.be>, tw38966@vub.ac.be (SH.RYU KIM
HOFMANS) wrote:

> A few weeks ago I've seen a posting about 
> 'altera vs xilinx' but i just missed that one.
> Could the sender repost that one ?
> 
(I'm not the sender but I saved a copy; I'll email it)

Can anyone give us an update on the latest news?

Should we expect Altera to withdraw their FLEX from sale or 
will it just be more expensive to cover Xilinx's royalty?

Ian.

-- 
Ian Lazarus 
Nuclear Physics Support Group, CCL, Daresbury Laboratory
email: Lazarus@dl.ac.uk


Article: 1277
Subject: Re: Altera Contacts ...
From: Paul Walker <paul@walker.demon.co.uk>
Date: 25 May 1995 16:05:01 +0100
Links: << >>  << T >>  << A >>
In article <3q09gb$ok2@aimnet1.aimnet.com>
           sjsmith@aimnet.com "Stephen J Smith" writes:

>altera does have these type of macrofunctions (PCI, ATM, ...) but
>currently they are only available from the bbs.
>these macrofunctions will be mirrored to the ftp site in the next few weeks.
                                                       ^^^^^^^^^^^^^^^^^^^^^
T'would be nice. That's what the Readme on the ftp server said, I think 
it was November last year. Meanwhile the sales blurbs imply it's already 
there.

Nevertheless, many thanks for the info.

-- 
Paul Walker                 4Links for technical help
+44 1908 566253             P O Box 816, Two Mile Ash
paul@walker.demon.co.uk     Milton Keynes MK8 8NS, UK


Article: 1278
Subject: Re: Altera Flex Logic & Other Problems
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 25 May 1995 15:36:46 GMT
Links: << >>  << T >>  << A >>
In article <TefuvYMQzvkY083yn@io.org> Ryan Raz, morph@io.org writes:
>I have been trying to use the Intel download software (PENGN) to
>configure these parts without any success. The software is unable
>to read the proper ID from these parts.

Typically it does this if the TDI/TDO loop is not complete. Check you
have not misinterpreted TDI-PORT and TDO-PORT on the cable - these are
not intuitive since TDO-PORT is the input to the board and TDO board the
output.
>
>Has anyone tried using the Intel cable and software with both
>Intel and Altera parts?

Yes

>
>_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 1279
Subject: Re: CUPL manual/info
From: holley@Data-IO.COM (Mike Holley)
Date: Thu, 25 May 1995 19:08:03 GMT
Links: << >>  << T >>  << A >>
In article <3pr73f$p1m@spock.asic.sc.ti.com> clyvb@asic.sc.ti.com writes:
> Does anyone know of a web site , or failing that a good book
>that can cover the essentials of CUPL. For programming PLD's
>Anything on ABEL (ABLE ??) would be good too. I am going to
>purchase/order some books this weekend.
>
>Thanks 
>Clive B.

ABEL (Advanced Boolean Expression Language)
ABEL was introduced by Data I/O in 1984 and is one
of the most widely used Hardware Description Languages.
While Verilog and VHDL were designed for system level
design and simulation, ABEL was designed specifically
for describing digital circuits for PLDs and FPGAs.

A book on Programmable Logic and ABEL is

  Digital Design Using ABEL
  David Pellerin and Michael Holley
  Prentice Hall  1994
  ISBN 0-13-605874-4
  Dark green hardback cover

This book covers HDL-based logic design and provides
many examples of how ABEL can be used for digital
applications. It has a complete ABEL language 
reference and includes a limited version of ABEL 5.0 
software.

Another book on Programmable Logic is

  Practical Design Using Programmable Logic
  David Pellerin and Michael Holley
  Prentice Hall  1991
  ISBN 0-13-723834-7
  Dark blue hardback cover

This book has more information on PLD and FPGA 
architectures and a chapter on the history of 
programmable logic. It also covers logic design 
and has many examples.

------------------------
I have no connection with the above products other
then being a co-author of the books and a developer
of the ABEL software.

Michael Holley
Data I/O




Article: 1280
Subject: Re: What's happening with NeoCAD?
From: Bond <bond@rahul.net>
Date: 26 May 1995 05:54:59 GMT
Links: << >>  << T >>  << A >>
Roland Welte <100070.3321@CompuServe.COM> wrote:
>

>   - What company bought NeoCAD (Xilinx, AT&T) ?

Xilinx

>   - Since NeoCAD was the only design system for FPGAs from
>     Motorola, what is happening with the support for these
>     devices, now that NeoCAD is not independent anymore.
>   - Will NeoCAD eventually disappear?

There will be no NeoCAD anymore. I guess erstwhile Neocad at CO 
will become the focal point of Xilinx Software Development.
Recently heard the AT&T has started an FPGA software development
facility at Boulder,CO ??

> 
> Half a year ago, I decided that NeoCAD is the tool of choice
> for our company's FPGA designs, mainly because of its
> device independent philosophy. But now it looks quite
> differently.

This is purely a matter of personal opinion. But why would anyone
want another company and another choice when there is Xilinx which
offers all possible technologies you can think of, SRAM or Antifuse
or EPLDs ... with best possible software :-)

-Bond





Article: 1281
Subject: ? FPGA library for ORCAD
From: Marek Skotnica <skotnica@ugn.cas.cz>
Date: 26 May 1995 09:41:46 GMT
Links: << >>  << T >>  << A >>
I am looking for orcad 4.04 sdt library with inside sw macros
of texas instruments FPGA tpc1010-tpc1460. Have anybody seen
it free in internet? Does anybody know if it exist?
Many thanks in advance.
Marek skotnica@ugn.cas.cz


Article: 1282
Subject: Re: FLEXlogic opinions?
From: uclyjrw@ucl.ac.uk (John Ragnvald Walliker)
Date: Fri, 26 May 1995 10:23:46 GMT
Links: << >>  << T >>  << A >>
roger@coelacanth.com (Roger Williams) writes:
>The SRAM option seems attractive, but this kind of architecture has
>the potential for routing problems...  It's also not clear if Altera
>regards these parts as orphans--I might end up designing the whole
                        ^^^^^^^

Intel recently stopped making the N85C508-7 programmable address decoder -
I believe shortly before selling the product line to ALtera.  Does anyone
know where I can find some to tide me over until I can redesign my
pcb to use an alternative device?

While I was talking to Altera about this, they mentioned that they will
integrate the Intel parts into their development software later this year.
They also said that the same fab is being used to make them as before.

John Walliker

PS please email me if you know where I can get some 85C508s!!!
j.walliker@ucl.ac.uk




Article: 1283
Subject: Re: Altera Contacts ...
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 26 May 1995 12:13:59 GMT
Links: << >>  << T >>  << A >>
Thanks for posting the simple listing of Altera contacts Stephen!

I hope all CPLD/FPGA vendors will take the time to post contact info.

What is the chance of storing contact info in a special place in the 
WWW archive?  Eg, somewhere up front, 1 file per vendor.  btw - many 
thanks to whomever maintains the archive.  It is most helpful.

   http://www.super.org:8000/FPGA/caf.html 
   COMP.ARCH.FPGA Archive

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1284
Subject: Re: CUPL manual/info
From: pngai@mv.us.adobe.com (Phil Ngai)
Date: Fri, 26 May 1995 16:39:51 GMT
Links: << >>  << T >>  << A >>
In article <D95EHF.n1M@maunakea.Data-IO.COM> holley@Data-IO.COM (Mike Holley) writes:
>In article <3pr73f$p1m@spock.asic.sc.ti.com> clyvb@asic.sc.ti.com writes:
>> Does anyone know of a web site , or failing that a good book
>>that can cover the essentials of CUPL. For programming PLD's
>>Anything on ABEL (ABLE ??) would be good too. I am going to

You want to watch out which version of ABEL you'll be working with.
For example, going from version 3 to version 4 was/is painful,
both to figure out the differences and every time you want to migrate
an old design, even when you know what to do, it's still tedious.

>ABEL (Advanced Boolean Expression Language)
>ABEL was introduced by Data I/O in 1984 and is one
>of the most widely used Hardware Description Languages.
>While Verilog and VHDL were designed for system level
>design and simulation, ABEL was designed specifically
>for describing digital circuits for PLDs and FPGAs.

If only it supported buses well.

-- 
 Should the 1st amendment apply to the Internet? Ask Senator Feinstein.



Article: 1285
Subject: ABEL optimization
From: miker@megatek.com (Mike Reeves)
Date: 27 May 1995 01:17:40 GMT
Links: << >>  << T >>  << A >>

Try compiling this simple little file. ABEL's unable to optimize
signals la4..la7 as 1. It does produce a working equation (cond1 & st2);
however, this failure to optimize between states can lead to some lengthy
equations for a complex state machine. (@DCSTATE/@DCSET doesn't change this)
As a result I'd recommend avoiding ABEL's "with" statement.

---cut here---
module JUNK

DECLARATIONS

  reset_n	pin;
  clock		pin;
  cond1		pin;

  la0		pin	istype	'reg';
  la1		pin	istype	'reg,dc';
  la2		pin	istype	'reg,pos';
  la3		pin	istype	'reg,neg';
  la4		pin	istype	'reg';
  la5		pin	istype	'reg,dc';
  la6		pin	istype	'reg,pos';
  la7		pin	istype	'reg,neg';

  STREG		state_register;
  st1,
  st2		state	istype 'dc';


LA = [la0..la7];

EQUATIONS

LA.clk		= clock;
LA.oe		= ^hFF;

STREG.clk	= clock;

state_diagram	STREG

  state st1:	goto st2;

  state st2:	if ( cond1 ) then
		  st2 with {
		    LA := ^h0F; }
		else
		  st1;

end JUNK

-- 
   Michael G. Reeves          email:     miker@megatek.com
   Megatek Corporation        voice:  (619) 675-4300 x2663
   16868 Via Del Campo Court  facsimile:    (619) 675-4341
   San Diego, CA  92127
	
--
   Michael G. Reeves          email:     miker@megatek.com
   Megatek Corporation        voice:  (619) 675-4300 x2663
   16868 Via Del Campo Court  facsimile:    (619) 675-4341
   San Diego, CA  92127
	


Article: 1286
Subject: Re: CUPL manual/info
From: trev@ss11.wg.icl.co.uk (Trevor Hall)
Date: Sat, 27 May 1995 07:53:24 GMT
Links: << >>  << T >>  << A >>
pngai@mv.us.adobe.com (Phil Ngai) write:-

Stuff about ABEL deleted

>If only it supported buses well.

Funny you should say that. MINCs PLDesigner supports busses, but it is very messy.

T.H.



Article: 1287
Subject: OrCAD HDL (OHDL) and Lattics pLSI devices
From: ssikdar@best.com (Som Sikdar)
Date: Sun, 28 May 1995 10:55:30
Links: << >>  << T >>  << A >>

I am using the OrCAD HDL compilers with Lattice pLSI devices (1016, 2032, 
1024, 1032). 

We bought it instead of ABEL/CUPL/MINC in order to evaluate yet another HDL 
and compiler. Frankly, we expected to find glitches that will make us go out 
and buy ABEL or CUPL. 

We were presently surprised by the compiler, after we got over the initial 
xenophobia of the new language structure and constructs. It is a nifty 
compiler and even though it does not support ESPRESSO or PRESTO reductions, the
MACBOOLE reductions it comes with have been fairly adequate so far.

I shall like to hear from others using OHDL with Lattice or other FPGAs. 

Som Sikdar
SHOMITI SYSTEMS
ssikdar@best.com




Article: 1288
Subject: Re: Altera Contacts ...
From: jma@gotham.super.org (Jeffrey M. Arnold)
Date: Sun, 28 May 1995 18:04:50 GMT
Links: << >>  << T >>  << A >>
William J. Wolf writes:
 > Thanks for posting the simple listing of Altera contacts Stephen!
 > 
 > I hope all CPLD/FPGA vendors will take the time to post contact info.
 > 
 > What is the chance of storing contact info in a special place in the 
 > WWW archive?  Eg, somewhere up front, 1 file per vendor.  btw - many 
 > thanks to whomever maintains the archive.  It is most helpful.

Thanks!  I have started to collect a list of vendors' pages, and will
probably add a separate page of links to the various vendors.  But I
think specific contact info should be provided (and maintained) by the
vendors themselves, rather than by us.

Please send me any links you feel should be added to the archive page.

-jeff

------
Jeffrey Arnold
IDA Center for Computing Sciences (formerly the Supercomputing Research Center)
17100 Science Dr.
Bowie, MD 20715
email: jma@super.org



Article: 1289
Subject: Any company for conversion FPGA to ASIC?
From: backfire@saturn.sst.co.kr (baik jong sung <4224>)
Date: 29 May 1995 02:14:17 GMT
Links: << >>  << T >>  << A >>
Hello Members in this news group,

I'm very pleased to post my first message to news group.

By the way, is there anybody who knows a company which
provides FPGA-to-ASIC conversion services ?
That is, I have some control logic designed by several
FPGA(5-Altera EPM7064QC100). But I have to convert these
chips to one-chip of ASIC, for example, LSI, Toshiba, etc.
I heard some companys in U.S could provide such kind of
services, but I'm not sure.

Please answer me about above question.

Thank you for reading.

 J.S. Baik

--

                  __|__                E-mail : backfire@saturn.sst.co.kr
           ------oo(_)oo------         Kids   : backfire



Article: 1290
Subject: Any company for conversion FPGA to ASIC?
From: backfire@saturn.sst.co.kr (baik jong sung <4224>)
Date: 29 May 1995 06:17:13 GMT
Links: << >>  << T >>  << A >>
Hello Members in this news group,

I'm very pleased to post my first message to news group.

By the way, is there anybody who knows a company which
provides FPGA-to-ASIC conversion services ?
That is, I have some control logic designed by several
EPLD(5-Altera EPM7064QC100). But I have to convert these
chips to one-chip of ASIC, for example, LSI, Toshiba, etc.
The source files are written in AHDL(*.tdf - Altera HDL),
so I could not retarget this design into other ASIC tech-
nology in Synopsys Design Compiler.

I heard some companys in U.S could provide such kind of
services, but I'm not sure.
If you know their name, please let me know.

Thank you for reading.

 J.S. Baik

--

                  __|__                E-mail : backfire@saturn.sst.co.kr
           ------oo(_)oo------         Kids   : backfire




Article: 1291
Subject: Design debug with Xilinx extra fine pitch parts
From: jbanks@hpqtdzo.sqf.hp.com (Jim Banks)
Date: Mon, 29 May 1995 09:54:07 GMT
Links: << >>  << T >>  << A >>
Does anyone have any recommendations or experiences of functionally
debugging pcb's containing Xilinx extra fine pitch (XFP) parts.

Due to the physical and functional constraints placed on our latest 
design, we chose to use XFP parts. We performed extensive simulations
prior to manufacture to remove the majority of functional errors and
used a variety of probes, wires and clips when the board was returned
to complete the debug.

The main problem we had was with the test clips which we found to be
expensive, have a very short life and could only be used reliably when
the board was flat on the bench. As we have a double sided board, this
proved a bit of a pain.

Has anyone seen similar problems with the XFP clips? If so, how did
you get round the problems? If not, what clip manufacturers would you
recommend?

What other experiences did you have debugging with XFP parts?

What recommendations do you have if you have to use these parts?

Any input greatly appreciated.

Jim Banks.


--
 *************** __  **************************************************
*************   / /    ************ Jim Banks                          *
***********    / /        ********* HP Queensferry Telecom Operation   *
*********     / /___ ______ ******* email:  jbanks@hpsqf.sqf.hp.com    *
********     / __  // __  /  ****** Mail:   Station Road               *
********    / / / // /_/ /   ******         South Queensferry          *
*********  /_/ /_// ____/   *******         West Lothian, EH30 9TG     *
**********       / /      *********         Scotland                   *
************    / /     *********** Telnet: 313-2949 (+44-131-331-7949)*
 ************* /_/ ****************************************************



Article: 1292
Subject: Re: Any company for conversion FPGA to ASIC?
From: jeff_cunningham@fostex.com (Jeff Cunningham)
Date: 29 May 1995 15:41:08 GMT
Links: << >>  << T >>  << A >>
In article <3qbot9$oge@noc.sait.samsung.co.kr>
backfire@saturn.sst.co.kr (baik jong sung <4224>) writes:

> By the way, is there anybody who knows a company which
> provides FPGA-to-ASIC conversion services ?
> That is, I have some control logic designed by several
> EPLD(5-Altera EPM7064QC100). But I have to convert these
> chips to one-chip of ASIC, for example, LSI, Toshiba, etc.

Orbit Semiconductor, ATS (Advanced Technical Solutions) & AMI all do
turnkey FPGA conversions. I would guess all three could convert the
chips you mention into a single ASIC. In the case of the first two, you
need to supply full production test vectors. In the case of AMI, you
can opt to just give them functional test vectors and they will (for a
fee) insert scan elements and generate production test vectors
themselves. AMI will also (for a fee) automatically add full JTAG
boundary scan.

-Jeff.


Article: 1293
Subject: Example/Benchmark circuits with Memory
From: wilton@eecg.toronto.edu (Steve Wilton)
Date: 29 May 95 15:52:09 GMT
Links: << >>  << T >>  << A >>

Hi,

We are performing research into memory architectures on FPGAs.  More
specifically, we are looking at how large (several Kbit) configurable
SRAM arrays can be included on an FPGA along with logic resources.  To 
evaluate some of our ideas, we need benchmark circuits.  Unfortunately,
all the "standard" benchmark suites (as far as we know) contain circuits
without memory.  

If anyone has circuit descriptions (with memory) that they are willing to
part with, we would be grateful.  We are looking at circuits with less than
(about) 30,000 gates of logic, and less than (about) 64Kbits of memory
(significantly smaller circuits are OK too).  The netlists can be in any
format (as long as we can understand it). 

If you can help us out, please send email to: wilton@eecg.toronto.edu
Thanks!


Article: 1294
Subject: Help on Programming FPGAs
From: esteves@di.uminho.pt (Antonio Esteves)
Date: 29 May 1995 16:45:48 GMT
Links: << >>  << T >>  << A >>

Dear Srs,

We are using an FPGA 3090 from XILINX and we stated some problems with
programming it.
Could someone please help us with useful information ?

Next we describe our design:

- The board we use consists on a transputer T425, memory and LCA3090 devices.

- The transputer programs the LCA in Peripheral Mode. The schematic used
  during configuration is the following:

    i) notCS1=GND, CS2=Vcc, notCS0 is activated on each byte we send to the LCA;
    ii) notWR (from T425) is connected to notWS (LCA) and is activated on each 
       byte we send to the LCA;
    iii) INIT (LCA) - is not used;
    iv) RDY/notBUSY (LCA) is read by T425, via bit 0 of Data Bus, using 
    a Tri-state buffer;
    v) DONE/notPROGRAM (LCA) is activated by T425 via an Open collector buffer.
 
- The transputer sends each byte of the configuration file (.BIT) to the LCA and
waits by the LcaReady signal (which arise successfully).

- At the end of the configuration file, LCA device should deactivate the
DONE/notPROGRAM signal, which stays at LOW LEVEL.
  Why the I/O pins of the LCA do not become active, when the signal RDY/notBUSY
seems to behave correctly on each configuration writing cycle?
  Is normal the DONE/notPROGRAM signal to be at LOW level during all the 
configuration process ? 

- The conditions used in XACT to generate the configuration file (.BIT) for a 
    simple system, were:
    TLL inputs, Pullup resistor in DONE/notPROGRAM, no Readback, 
    XtalOsc disabled, DONE/notPROGRAM and RESET signals activated  1 cicle after
    the end of the configuration. We didn't use Tie of unused logic, and 
    the logic outside the LCA is TTL.

Thanks a lot in advance.
Best regards.
-- 
+-----------------------+-----------------------------------------------------+
| Antonio J. A. Esteves |                                                     |
| Dep. Informatica      | esteves@di.uminho.pt                                |
| Universidade do Minho | Tel: +351 53 604479                                 |
| Largo do Pac,o        | Fax: +351 53 612954                                 | 
| 4719 Braga Codex      | PGP: finger -l esteves@shiva.di.uminho.pt           |
| Portugal              | WWW: http://www.di.uminho.pt/~esteves/index.html    |
+-----------------------+-----------------------------------------------------+






Article: 1295
Subject: Low cost FlexLogic programmer
From: robc@appliedmicro.ns.ca (Rob Christopher)
Date: 29 May 1995 15:56:07 -0300
Links: << >>  << T >>  << A >>
Hi all

Does anyone have any info on a low cost programmer that I can use on
Flex780 devices.  I've heard of a product called the PROTAG programmer
made by a company called Products in Motion but the number I have for them
has been disconnected (probably a bad sign).  I'm interested in hearing
from anyone with a lead for me.

Thanks

Rob Christopher                       robc@appliedmicro.ns.ca
Hardware Designer
Applied Microelectronics, Inc.        phone: (902)421-1250
1046 Barrington St.                   fax:   (902)429-9983
Halifax, N.S.
Canada


Article: 1296
Subject: Re: Help on Programming FPGAs
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 30 May 1995 11:04:18 GMT
Links: << >>  << T >>  << A >>
In article <3qctns$2b2@icaro.uminho.pt> esteves@di.uminho.pt writes:
>
>Dear Srs,

and Madams, 

>
>We are using an FPGA 3090 from XILINX and we stated some problems with
>programming it.
>Could someone please help us with useful information ?
>
>Next we describe our design:
>
>- The board we use consists on a transputer T425, memory and LCA3090 devices.
>
>- The transputer programs the LCA in Peripheral Mode. The schematic used
>  during configuration is the following:
>
>    i) notCS1=GND, CS2=Vcc, notCS0 is activated on each byte we send to the LCA;
>    ii) notWR (from T425) is connected to notWS (LCA) and is activated on each 
>       byte we send to the LCA;
>    iii) INIT (LCA) - is not used;
>    iv) RDY/notBUSY (LCA) is read by T425, via bit 0 of Data Bus, using 
>    a Tri-state buffer;
>    v) DONE/notPROGRAM (LCA) is activated by T425 via an Open collector buffer.
> 
>- The transputer sends each byte of the configuration file (.BIT) to the LCA and
>waits by the LcaReady signal (which arise successfully).

The .BIT file has a header that you DO NOT want to send to the chip.
About 64 to 70 bytes into the file you will find the sequence 'FF' '20'.
the 'FF' is where you need to start. Personally, I prefer using the .RBT
file and reformatting it to suit the application. That way I know exactly
what the data looks like. use 'makebits -b design.lca' to create design.rbt

If you look at page 2-120 of the 1994 data book, the 8 bits labeled dummybits
are the 'FF', and the '0010' is the '2' of the '20'. the '0' of the '20' is
the first 4 bits of the 24 bit length count.


>
>- At the end of the configuration file, LCA device should deactivate the
>DONE/notPROGRAM signal, which stays at LOW LEVEL.

Do you have a Pull up resistor on this signal? if you dont, then it can't
go high. 


>  Why the I/O pins of the LCA do not become active, when the signal RDY/notBUSY
>seems to behave correctly on each configuration writing cycle?

The I/O pins will only go active if the chip is done. 

>  Is normal the DONE/notPROGRAM signal to be at LOW level during all the 
>configuration process ? 

Yes, and so is LDC. HDC is high during configuration. 

>
>- The conditions used in XACT to generate the configuration file (.BIT) for a 
>    simple system, were:
>    TLL inputs, Pullup resistor in DONE/notPROGRAM, no Readback,

You still need an external pull-up resistor, I use 4.7k ohms. You also
need one on INIT.
 
>    XtalOsc disabled, DONE/notPROGRAM and RESET signals activated  1 cicle after
>    the end of the configuration. We didn't use Tie of unused logic, and 
>    the logic outside the LCA is TTL.
>

After the end of your data, you should probably send one extra byte of data,
and it should be an 'FF'. this is sometimes needed for the startup sequence
to complete, as the sequence takes 3 clocks, and if your data happens to have
its last byte end within this sequence, then the chip wont go done. The extra
byte will always supply sufficient clocks to do this, and the FF code just
looks like postamble (see 2-120 again)

Hope this gets you going,

All the best
		Philip Freidin.		Fliptron@netcom.com
			

>Thanks a lot in advance.
>Best regards.
>-- 
>+-----------------------+-----------------------------------------------------+
>| Antonio J. A. Esteves |                                                     |
>| Dep. Informatica      | esteves@di.uminho.pt                                |
>| Universidade do Minho | Tel: +351 53 604479                                 |
>| Largo do Pac,o        | Fax: +351 53 612954                                 | 
>| 4719 Braga Codex      | PGP: finger -l esteves@shiva.di.uminho.pt           |
>| Portugal              | WWW: http://www.di.uminho.pt/~esteves/index.html    |
>+-----------------------+-----------------------------------------------------+
>
>
>
>




Article: 1297
Subject: Display EDIF (EDIF -> ORCAD)
From: "C:COMMSDISWIN32KA9QSPOOLMAIL" <horste@rwattsa.demon.co.uk>
Date: 30 May 1995 13:16:18 +0100
Links: << >>  << T >>  << A >>
Hi,
we are doing some FPGA/ASIC design in VHDL. 
To see the output of the design it would be a nice thing to get the 
EDIF netlist displayed.Does anyone know about a EDIF display program, 
or a converter for ORCAD?

Any help would be appreciated.

Horst Eyermann

-- 
-------------------------------------------------------------------
| Evolution Electronics Ltd  EMail horste@evolution.co.uk          |
-------------------------------------------------------------------



Article: 1298
Subject: Re: ABEL optimization
From: kgold@watson.ibm.com (Ken Goldman)
Date: 30 May 1995 13:18:02 GMT
Links: << >>  << T >>  << A >>
I might be missing something here, since I don't have immediate access
to ABEL right now, but I'll comment anyway (in true Internet tradition).

I would not expect the reduced equation to be LA<4:7> = 1 but rather
LA<4:7> = (STREG==st2) & cond1.  Is this what ABEL did?

A big difference between ABEL and Verilog is that ABEL implies
"else 0" in state machines while Verilog implies "else keep the
previous state."


miker@megatek.com (Mike Reeves) writes:
> 
> Try compiling this simple little file. ABEL's unable to optimize
> signals la4..la7 as 1. It does produce a working equation (cond1 & st2);
> however, this failure to optimize between states can lead to some lengthy
> equations for a complex state machine. (@DCSTATE/@DCSET doesn't change this)
> As a result I'd recommend avoiding ABEL's "with" statement.
> 
> ---cut here---
> module JUNK
> 
> DECLARATIONS
> 
>   reset_n	pin;
>   clock		pin;
>   cond1		pin;
> 
>   la0		pin	istype	'reg';
>   la1		pin	istype	'reg,dc';
>   la2		pin	istype	'reg,pos';
>   la3		pin	istype	'reg,neg';
>   la4		pin	istype	'reg';
>   la5		pin	istype	'reg,dc';
>   la6		pin	istype	'reg,pos';
>   la7		pin	istype	'reg,neg';
> 
>   STREG		state_register;
>   st1,
>   st2		state	istype 'dc';
> 
> 
> LA = [la0..la7];
> 
> EQUATIONS
> 
> LA.clk		= clock;
> LA.oe		= ^hFF;
> 
> STREG.clk	= clock;
> 
> state_diagram	STREG
> 
>   state st1:	goto st2;
> 
>   state st2:	if ( cond1 ) then
> 		  st2 with {
> 		    LA := ^h0F; }
> 		else
> 		  st1;
> 
> end JUNK


Article: 1299
Subject: PCI ALTERA design
From: fmj@pe.dk (Finn M. Johansen)
Date: Tue, 30 May 1995 14:28:19 GMT
Links: << >>  << T >>  << A >>
Hi you FPGA designers!!!
I am  designing a data communication add-in card for the PCI bus. We have
ALTERA Max+Plus II software at your company so I have decided to use FLEX 8K
device(s) for the design. The add-in card has to operate in a master and
target configuration. However I have experienced that to drive the PCI
interface signals as master you need to use 6  I/O cell Output Enable
signals to keep witin the input-setup time and clock-to-output time
requirements in the spec. Unfortunately the Flex 8K devices only have 4
(except EPF81500, it has 10). What is the solution to this problem? Multiple
devices can be a solution where the master driver logic with my back-end
device specific logic could go in one device and PCI synchronous inputs and
target logic in another. But what about load problems??? Is it a better idea
to use PCI compliant MAX devices.
Please note folks that I have only worked with the FLEX devices and
unfortunately I am new in digital design. 

Please give me some ideas or solutions (if any) ASAP. My time schedule is
very tight.
----------------------------------------------------------------------------
-----------------------

Finn M. Johansen, M.Sc.E.E.
Hardware Design Engineer, R&D
------------------------------
PURUP PREPRESS A/S
5 Soenderskovvej
DK-8520 Lystrup
Denmark
Phone: +45 87 434 343
Fax: +45 87 434 445
E-mail: fmj@pe.dk
------------------------------
                                                                            
                                                     
----------------------------------------------------------------------------
---------------------





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