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Messages from 4675

Article: 4675
Subject: Xilinx Foundation
From: I.H.Lazarus@dl.ac.uk (Ian Lazarus)
Date: Thu, 28 Nov 1996 11:25:03 +0000
Links: << >>  << T >>  << A >>
I have an old (out of maintenance) Viewlogic schematic based 
Xilinx system, and I have the choice to either bring it back up
to date (I won't bother with Viewlogic VHDL after reading the
100% negative comments on this list!) or else switching to the
new Foundation stuff. 

I've been looking at the VHDL vs schematics thread and not seen
any comments on the Xilinx Foundation s/w in general and its VHDL
in particular. Maybe I missed it, but it seems that people use
either Viewlogic (schematic or VHDL) or Synopsis. Does anyone
use Foundation? Is it any good? Any advice would be welcome.
I definitely want to keep schematic entry, but I'd like to
add VHDL to try it (and maybe switch to VHDL for designs where
it has advantages) and it seems that I'd need Foundation to do it.

thanks for your posts (or emails).

Ian.

-- 
Ian Lazarus 
Nuclear Physics Support Group, CCLRC, Daresbury Laboratory
email: I.H.Lazarus@dl.ac.uk
Article: 4676
Subject: Free Evaluation VHDL Editor
From: John Maher <jmaher@vhdl.com.au>
Date: 28 Nov 1996 12:15:43 GMT
Links: << >>  << T >>  << A >>
A 45 day evaluation licence for SETANTA ED, a VHDL aware editor 
is available at :

http://www.vhdl.com.au

Features include:

+ Keyword colorising
+ no file length limit
+ Automatic Testbench Generation (Beta version)
+ Automatic model insertion
+ Dozens of free VHDL models including counters, adders
+ Support for C/C++, JAVA, Perl, and many more languages



Try it out, lets us know what you think.

-John Maher
 Technical Director
 VHDL System Solutions P/L
 
 email: jmaher@vhdl.com.au

Article: 4677
Subject: Reconfigurable FPGAs in Networking
From: mak@cromp.ernet.in
Date: 28 Nov 1996 07:24:03 -0800
Links: << >>  << T >>  << A >>
Hi all,
I have come across a lot of examples of processor architecture using
reconfigurable FPGAs. But has anyone heard of reconfigurable FPGAs
getting used in switching and routing applications? Links to stuff
on the web and other info is welcome.
Thanking in advance,
Makarand
Article: 4678
Subject: Please Help!!!
From: trythis@money.com
Date: Thu, 28 Nov 1996 18:11:35 GMT
Links: << >>  << T >>  << A >>
Thanks for taking the time to read this message! This is about a lady
that gave all she could to everyone, including me. Her name is Wendy.


	When I was young she became my foster mother after my real
mother had abandon me. Never having any kids of her own she became a
foster parent. That I got to be in her care was probably the best
thing that had ever happened to me. She had other foster children and
even ended up taking care of many of the neighborhood kids.  

	Wendy is a lady that just never gave up and always gave more
than anyone could imagine. I no longer think of my real mother as
mother but rather Wendy as my only true mother. I know that I'm not
the only one that thinks that way either. It wasn't just kids that she
helped it included the elderly, the disabled and the just down and
out.  What it takes to qualify for a saint is something I never found
out, but I know it can't be more than the things I saw this lady do
for anybody.  Even people that had wronged her could find themselves
looking up at her while she helped them when they were down.

	I'm 26 now and many of the things I'm telling you I never
really realized until now.  Since I was a kid she has helped me with
everything from recovering from my mistakes to just being there to say
"You can do it... It'll be okay."  I've never been able to make a good
attempt at trying to repay her for all she's done for me and I'm not
alone.  Many people just have taken for granted the things she's done
for them.  

	I know by now you're asking yourself why I've posted this
letter.  Well, to be honest and straight with you it's because I would
like your help. If there's one thing that I've learned from Wendy it's
that, "We are our neighbors keepers."  You know the golden rule, "Do
onto others as you would have them do onto you." Anyway now Wendy is
an older lady that is disabled and can't do as much as she used to.
With the disability sometimes expenses can be too much. I now live in
Arkansas and can't be of much help. With no real family I'd like to do
something to try to repay all she done for me and many others.

	 That's were you come in.  See if you can think back to
someone that helped you no matter how big or small.  Maybe it's
someone you can't even remember or have lost touch with.  For that
moment picture Wendy and say, "I'd like to repay that kindness."  I
wish you would sit down and write a small note saying "Thanks for
being the generous person that you have been!" If you could include
something to help out.  Maybe it's a five dollar bill, a book of
stamps, even a dollar.  Oh and would you also tell her the Steffin
sends his love.  Her birthday is next month on the 27th and I'm hoping
I can make this own a very memorable one.	

	Thanks for reading and if you choose to help God pless you.
Her address is

Wendy Mcghee 
9636 Elm
Taylor, Mi 48180

Article: 4679
Subject: Re: How to use Xilinx ?
From: vn5s-cng@asahi-net.or.jp
Date: Fri, 29 Nov 1996 15:54:35 +0900
Links: << >>  << T >>  << A >>
I found how to assign the pin number .


Here is a sample for how to assign pin number .

--
library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR ;
use METAMOR.attributes.all ;

entity uh6 is
   port (
	PXCLKN 	: in std_logic ;
	);

    attribute pinnum of PXCLKN 		: signal is "p160" ;

end uh6;
--


Cong
Article: 4680
Subject: Re: How to use Xilinx ?
From: Steve Wiseman <steve@sj.co.uk>
Date: Fri, 29 Nov 1996 07:26:12 +0000
Links: << >>  << T >>  << A >>
vn5s-cng@asahi-net.or.jp wrote:
> 
> I found how to assign the pin number .

Hi, 
  what synthesis tools are you using? I've seen this referred to before,
but are attributes supported at all under the Viewlogic tools?

  Cheers,
   Steve
Article: 4681
Subject: Cypress CPLD, pASIC380 Programmer
From: ees1ht@ee.surrey.ac.uk (Hans Tiggeler)
Date: 29 Nov 1996 09:30:24 GMT
Links: << >>  << T >>  << A >>

Can anybody tell me if there is a low-cost programmer for Cypress CPLD and 
pASIC380 family? 

Their VHDL synthesis software is amazingly cheap (32 Pounds for Warp2 
Version4.0 + VHDL synthesis book). The Cypress databook describes the Impulse 
3 programmer which is based on an OEM version of the DATA I/O ChipLab 
programmer. Those of you who know this programmer also know is far from 
low-cost.

Thanks for any comments,

Hans.
email: ees1ht@ee.surrey.ac.uk

Article: 4682
Subject: Addressbility.
From: TukryopKim <acsapark@public.bta.net.cn>
Date: Fri, 29 Nov 1996 18:48:59 +0800
Links: << >>  << T >>  << A >>
Hi,
I am having duty of to make a algorithm which is able to access the
abundant memory with minimum address pin lines. Perhaps that memory has
about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
boss require me it.
Probably it could be carried out with only new mathematical approach.
With group theory?

Any, any hints would be greatly appreciated.
Thanks in adavnce.
Article: 4683
Subject: Re: Free Evaluation VHDL Editor
From: Uwe Bonnes <bon@elektron.ikp.physik.th-darmstadt.de>
Date: 29 Nov 1996 11:33:53 GMT
Links: << >>  << T >>  << A >>
John Maher <jmaher@vhdl.com.au> wrote:
: A 45 day evaluation licence for SETANTA ED, a VHDL aware editor 
: is available at :

: http://www.vhdl.com.au

: Features include:

: + Keyword colorising
: + no file length limit
: + Automatic Testbench Generation (Beta version)
: + Automatic model insertion
: + Dozens of free VHDL models including counters, adders
: + Support for C/C++, JAVA, Perl, and many more languages



: Try it out, lets us know what you think.

Does it run on Unix/Linux?


-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 4684
Subject: Re: Addressbility.
From: mikeq@primenet.com (Michael Quinlan)
Date: 29 Nov 1996 09:57:01 -0700
Links: << >>  << T >>  << A >>
TukryopKim <acsapark@public.bta.net.cn> wrote:

>Hi,
>I am having duty of to make a algorithm which is able to access the
>abundant memory with minimum address pin lines. Perhaps that memory has
>about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
>boss require me it.
>Probably it could be carried out with only new mathematical approach.
>With group theory?

If you know in advance how much memory you can have, you should be able =
to
address it with a single pin by sending the address serially instead of =
in
parallel. If you don't know how much memory you have, you might have to =
use
something like a stop bit (a signal 1.5 or 2 times the length of your
normal signal) to mark the end of the address.

-------------------------------------
Michael A. Quinlan
mikeq@primenet.com
http://www.primenet.com/~mikeq
"If it doesn't fit, you must acquit!"
-------------------------------------
Article: 4685
Subject: Re: SRAM Programming on the Altera NFX780
From: rick@camden.algor.co.uk (Rick Filipkiewicz)
Date: 29 Nov 1996 17:20:23 GMT
Links: << >>  << T >>  << A >>
Kevin Horton (khorton@iquest.net) wrote:
: I've been doing a little project on the Altera EPX780LC84-15.  I have it
: working great (visit: http://www.iquest.net/~khorton/bankzill.htm for
: details) but I'm having problems finding the programming spec. for this part.
: The goal is to have a micro (80C85) program it on power-up so that changes 
: and additions are simple to do without replacing the FPGA.

: I've done several 'net searches and have come up empty-handed.  I visited the
: Altera web page, and it's like the part has never existed; there are only
: data sheets for their latest offerings.  

: So, if anyone can tell me the basics on how to get the data into the part's
: SRAM cells, I'd be appriciative.  BTW, I used the 'pengen' program to convert
: the JEDEC file into the bit-stream required by the part; I just need to know
: how to play with the TCK, TDI, TDO (output probably not required for 
: programming), and TMS lines.

I've been using this series of parts since they were made by Intel
(and the programming s/w was FREE - what an amazing idea to try and
make money by selling parts!). If you look in the Altera PLSshell data
book you will find that the binary output from PENGEN (or JED2JTAG)
interleaves the TMS and TDI bits. What we do is convert the binary to
an S3 file and blow it into an EPROM.

The board has a little state machine in a 22V10 that gets bytes from
the EPROM and serialises the bit pairs, even bits on TDI and odd bits
on TMS. After each bit pair is driven the state machine toggles TCLK
and every 4 pairs it increments the EPROM address.

Note that we don't use the Intel hex format output of JED2JTAG since
the first 4 bytes are size info.

It would be nice to use a serial EEPROM but I don't know of a cheap
one that has the 32KByte capacity needed for 4 daisychained devices.
 _________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 4686
Subject: Re: Reconfigurable FPGAs in Networking
From: Gareth Baron <EXTR.QBCGABA@mesmtpse.ericsson.se>
Date: Fri, 29 Nov 1996 09:34:28 -0800
Links: << >>  << T >>  << A >>
What are you doing?  There are some reconfigurable cross-point switches 
from I-CUBE which do routing of digital signals.  This may be what you 
need.  I do also know of someone who uses a XILINX as an address 
comparitor.  They download a different bit stream (which is dynamically 
calculated) to catch different addresses.  The had to reverse-engineer 
the XILINX device bitstream though.

-- 


Gareth Baron.

Email: gareth@trsys.demon.co.uk
Article: 4687
Subject: Re: Xilinx Foundation
From: Mike Forster <forstemd@perkin-elmer.com>
Date: Fri, 29 Nov 1996 17:39:46 GMT
Links: << >>  << T >>  << A >>
Ian Lazarus wrote:
> 
> I have an old (out of maintenance) Viewlogic schematic based
> Xilinx system, and I have the choice to either bring it back up
> to date (I won't bother with Viewlogic VHDL after reading the
> 100% negative comments on this list!) or else switching to the
> new Foundation stuff.
> 
> I've been looking at the VHDL vs schematics thread and not seen
> any comments on the Xilinx Foundation s/w in general and its VHDL
> in particular. Maybe I missed it, but it seems that people use
> either Viewlogic (schematic or VHDL) or Synopsis. Does anyone
> use Foundation? Is it any good? Any advice would be welcome.
> I definitely want to keep schematic entry, but I'd like to
> add VHDL to try it (and maybe switch to VHDL for designs where
> it has advantages) and it seems that I'd need Foundation to do it.
> 
> thanks for your posts (or emails).
> 
> Ian.
> 
> --
> Ian Lazarus
> Nuclear Physics Support Group, CCLRC, Daresbury Laboratory
> email: I.H.Lazarus@dl.ac.uk
Ian

I bought the top of the line Foundation series with VHDL, XABEL etc a
few weeks ago. I am surprised that a leading player in the fpga industry
is selling such poor software. The Xilinx written stuff seems to be ok
but they buy in the schematic tool and simulator from Aldec and the VHDL
sythesiser from Metamor.

I am only just getting into VHDL and so don't feel able to comment on
the quality of the tool although the editor is VHDL aware and so
highlights to code nicely.

The big problem is the schematic editor and simulator. There are so many
things wrong with it I don't know were to start. One immediate problem
you will have is with busses particulary if you use the XBLOX
parameterised modules. You seem unable to pass XBLOX busses through the
hierarchy, the must be converted to normal busses first, pass through
the symbol and then converted back to XBLOX at the next level. The XBLOX
bus will not pass correctly to the simulator. There are more problems
when you start to change the signals the signals that pass through the
hierarchy. The software tries (an often fails) to be clever in ensuring
that the signals passing from one level to the next match on the symbol.
This would be ok if it worked but I seem to keep loosing the changes I
just made.

I could go an and on but I am at work and am not being payed to moan
about a tool I bought. My recommendation, for what it is worth, is to go
for the cheapest tool without VHDL or XBLOX and see for yourself. If you
don't like it at least you haven't spent that much.

Mike Forster
Perkin Elmer Ltd
UK

These are my own views and not those of Perkin Elmer.
Article: 4688
Subject: Re: Addressbility.
From: lloyd@itres.com (Lloyd Miller)
Date: 29 Nov 1996 23:11:50 GMT
Links: << >>  << T >>  << A >>
TukryopKim <acsapark@public.bta.net.cn> wrote:

>I am having duty of to make a algorithm which is able to access the
>abundant memory with minimum address pin lines. Perhaps that memory has
>about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
>boss require me it.

Does your boss know anything about binary arithmetic?

>Probably it could be carried out with only new mathematical approach.
>With group theory?

Probably not.

>Any, any hints would be greatly appreciated.

Use big word sizes and wide busses. 256 bits or 1024 bits per word (or
more?). Disks call them "block addresses". Same idea.



Article: 4689
Subject: Re: Reconfigurable FPGAs in Networking
From: Ray Andraka <randraka@ids.net>
Date: Fri, 29 Nov 1996 16:59:34 -0800
Links: << >>  << T >>  << A >>
mak@cromp.ernet.in wrote:
> 
> Hi all,
> I have come across a lot of examples of processor architecture using
> reconfigurable FPGAs. But has anyone heard of reconfigurable FPGAs
> getting used in switching and routing applications? Links to stuff
> on the web and other info is welcome.
> Thanking in advance,
> Makarand

Talk to Bo Varga at Giga-Ops.  I believe they are working on a telecom 
application using reconfigurable computing.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 4690
Subject: Altera Max+Plus
From: Eric Holmberg <eholmber@vt.edu>
Date: Sat, 30 Nov 1996 03:03:31 -0500
Links: << >>  << T >>  << A >>
Is anybody out there using the LP6-MPU programmer under NT 4.0 (or any verision for that matter).  I 
installed the card and have tried all 16 :~(  IO Addresses to no avail.  The configuration menu 
refuses to accept my hardware...  HELP!!!

A direct email of *anything* would be appreciated.

Thanks, 

Eric    <ohms@vt.edu>
Article: 4691
Subject: Corel Draw 7.0! only costs US$40 ? Shopping Paradise
From: (DogZ Software Center)
Date: Sat, 30 Nov 1996 10:25:01 GMT
Links: << >>  << T >>  << A >>
Windows 95, Visual Foxpro, MS Office 7.0, Visual Basic, Visual C++,
Borland C++, Lotus cc:Mail Release 6,  Lotus SmartSuite 97, ......
only costs US$40 for all? 

CorelDraw 7.0! only costs US$40?

Hong Kong is the paradise in shopping.  You can buy anything you want
by  an reasonable price.


Today, by this chance, we would like to introduce to those who are
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In which, you can always find the most update warez includes all PC
Warez,  PC games, CD-Title, Shareware, Video-CD and Playstation game,
etc.


For Example, 
Inside a Installer (one CD only, Product No.: IN96112) , it contains
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Visual Foxpro 5.0, MS Windows 95 OEM Service Release, MS Money97, 
Lotus SmartSuite 97, Lotus cc:Mail Release 6, Symantec Cafe 1.5,
 Norton Your Eyes Only, Norton Smart Doctor 1.0, Quartdeck SpeedyROM
1.1,  KPT BrayceAlpha 2.0, Visual dBASE Professional 4.4a, 
MacroMedia Animator Designer, Solitaire Antics, Almost Reality, 
CakeWalk Express 3.01, ClockMan95, Demo-It!2.0, MicroLogic EMAGIC, 
EXTRA! Version 6.2, MacroMedia Icon Designer, Infinite Disk, InfoSpy
Pro, Fractal Deign Ray Dream Studio 4.1, Janna Conract Manager,
Kurzweil Voice release 2.0, PC Maclan verion 6.0, NetWizard Plus
Version 3.1, Organic Art, Microsoft Edition, PhotoWorks, RandoMedia,
Real Oschestra, Reflection 4, RichWin, SoundForge 4.0, SignLab Pro+,
Spectrum Pro CD Player,  Starfish Internet Sidekick, TeleMagic,
TurboCAD 3.0, MS-Visual SourceSafe 5.0, WinBye 32, Xing 3.02 Release,
Zydeco Management Desktop.

Good news to you today, that is, we would like to introduce all wares
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Article: 4692
Subject: In Search of Xilinx Routing Statistics
From: Lance Gin <c43lyg@dso.hac.com>
Date: Sat, 30 Nov 1996 19:24:26 -0800
Links: << >>  << T >>  << A >>
I've just finished a Xilinx 4025E design that PPR required 99% CLB's to
place/route. Utilization of CLB resources is a bit on the high side
(80%+ FG's, 50%+ DFF's). I've looked at the placed design with FPLAN
and PPR appears to have done an OK job given the speed requirements.
There are, however, many CLB's where only a few internal resources are
used. There are also many split nets (nets routed through CLB's) reported.

I'd like to make an informed assessment of how much more logic I can
*ADD* to the design. So far, I've got the following to work with:

(1) The standard CLB resource utilization stats from XACT.
(2) A view of the entire placed design from FPLAN.
(3) A grayscale view of routing congestion distribution from FPLAN.
(4) An idea of how much more logic I'd like to add.

Does anyone have any suggestions on other data I can use ?
How would you go about making such an assessment ?

Any feedback is greatly appreciated.


-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________

Article: 4693
Subject: Re: In Search of Xilinx Routing Statistics
From: timolmst@cyberramp.net
Date: Sun, 01 Dec 1996 15:06:00 GMT
Links: << >>  << T >>  << A >>
Lance Gin <c43lyg@dso.hac.com> wrote:

>I've just finished a Xilinx 4025E design that PPR required 99% CLB's to
>place/route. Utilization of CLB resources is a bit on the high side
>(80%+ FG's, 50%+ DFF's). I've looked at the placed design with FPLAN
>and PPR appears to have done an OK job given the speed requirements.
>There are, however, many CLB's where only a few internal resources are
>used. There are also many split nets (nets routed through CLB's) reported.

>I'd like to make an informed assessment of how much more logic I can
>*ADD* to the design. So far, I've got the following to work with:

>(1) The standard CLB resource utilization stats from XACT.
>(2) A view of the entire placed design from FPLAN.
>(3) A grayscale view of routing congestion distribution from FPLAN.
>(4) An idea of how much more logic I'd like to add.

>Does anyone have any suggestions on other data I can use ?
>How would you go about making such an assessment ?

>Any feedback is greatly appreciated.

I've been working with Xilinx FPGA's fro several years, though I don't
have the latest software (I run Xact v4.2 fro financial reasons). A
rule of thumb I have developed over the years that seems to serve me
well is to load a device to no more than 70% utilization when doing
the initila design. You will ALWAYS find something you need to
change/add as the design is brought up, and this will tend to fill the
device.

I would be scared to death of your device that was 99% utilized for
two reasons.

1. You have no room to move if you need to add something later.

2. As the device fill up, the most premium routing channels get
filled. Somewhere in that design is a signal (or more) that got routed
around Robin Hood's barn to get to a CLB next door. These can be the
ones that get you. I assume that you specified the max delays for some
critical signals from your post. The ones to watch are the ones you
DIDN'T specify. They probably aren't AS critical as the ines you did
specify, but if the delays get pushed waaaaay out, they may become
critical.

I know I didn;t give you any hard and fast answer, but I hope this
helps some.


Article: 4694
Subject: Re: Moore vs Mealy state machines
From: cburns@crl.com (Charlie Burns)
Date: 1 Dec 1996 16:55:07 -0800
Links: << >>  << T >>  << A >>
Mike Treseler (tres@tc.fluke.COM) wrote:

: [1] Treseler, Michael  "Designing State Machine Controllers Using 
: Programmable Logic" Prentice Hall, 1992, p89.
: [2] Ibid, p82-83.

This is a good book, by the way. I have it, I read it, I learn from it.

Charlie
Article: 4695
Subject: ISPD-97 CFP (Dec 20 Submission Deadline)
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Mon, 2 Dec 1996 05:00:28 GMT
Links: << >>  << T >>  << A >>
=============================================================================

                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

   The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems.  All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium.  Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
 
   The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop.  Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:

    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:

    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

General Chair:               A. B. Kahng (UCLA and Cadence)
Past Chair:                  G. Robins (Virginia)
Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
                             W. W.-M. Dai (UC Santa Cruz) 
                             J. Frankle (Xilinx) 
                             D. D. Hill (Synopsys) 
                             M. A. B. Jackson (Motorola) 
                             J. A. G. Jess (Eindhoven)  
                             Y.-L. Lin (Tsing Hua) 
                             C. L. Liu (Illinois)
                             M. Marek-Sadowska (UC Santa Barbara)
                             M. Sarrafzadeh (Northwestern)
                             C. Sechen (Washington) 
                             K. Takamizawa (NEC)
                             M. Wiesel (Intel) 
                             D. F. Wong (Texas-Austin) 
                             E. Yoffa (IBM)

=============================================================================
Article: 4696
Subject: Re: Addressbility.
From: Tony Griffiths <tonyg@OntheNet.com.au>
Date: Mon, 02 Dec 1996 16:47:10 +1000
Links: << >>  << T >>  << A >>
Your problem description is not sufficient.  A little more info would
help!  However...

Lloyd Miller wrote:
> 
> TukryopKim <acsapark@public.bta.net.cn> wrote:
> 
> >I am having duty of to make a algorithm which is able to access the
> >abundant memory with minimum address pin lines. Perhaps that memory has
> >about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
> >boss require me it.
>
	2 ** 10		-> 1KB
	2 ** 20		-> 1MB
	2 ** 30		-> 1GB
	2 ** 40		-> 1TB
	  etc
So you need a few more bits than 40 for "several" terabytes!
 
> Does your boss know anything about binary arithmetic?
> 
> >Probably it could be carried out with only new mathematical approach.
> >With group theory?
>
Is your memory 'linear' or 'holey'.  If linear, than a simple linear
page table with a length register will do the trick.  If the memory is
holey (ie. non-contiguous virtually), then a tree structured page table
is most efficient for very large memories.  The Alpha VM implementation
is a 3-level tree with 43 (8TB) address lines implemented.  There are
also a few more tricks used to save on translation buffer entries such
as the ability to group contiguous virtual/physical pages into 'super'
(can't remember the term in the Alpha Reference Manual) pages of up to
4MB each (ie. 512 normal 8KB pages mapped by 1 TB entry).
 
> Probably not.
> 
> >Any, any hints would be greatly appreciated.
> 
> Use big word sizes and wide busses. 256 bits or 1024 bits per word (or
> more?). Disks call them "block addresses". Same idea.

Disk blocks and memory pages are really much the same think when it
comes to addressability.  The width of the bus really only affects the
speed of access/transfer, not the addressability.  Eg.  Ethernet uses a
48-bit address (256TB) which is somewhat of an overkill for most LANs.

Tony
Article: 4697
Subject: Re: In Search of Xilinx Routing Statistics
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Mon, 02 Dec 1996 04:11:47 -0800
Links: << >>  << T >>  << A >>
timolmst@cyberramp.net wrote:
> Lance Gin <c43lyg@dso.hac.com> wrote:
> >I've just finished a Xilinx 4025E design that PPR required 99% CLB's to
> >place/route. Utilization of CLB resources is a bit on the high side
> >(80%+ FG's, 50%+ DFF's). I've looked at the placed design with FPLAN
> >and PPR appears to have done an OK job given the speed requirements.
> >There are, however, many CLB's where only a few internal resources are
> >used. There are also many split nets (nets routed through CLB's) reported.
> 
> >I'd like to make an informed assessment of how much more logic I can
> >*ADD* to the design. 

> I've been working with Xilinx FPGA's fro several years, though I don't
> have the latest software (I run Xact v4.2 fro financial reasons). A
> rule of thumb I have developed over the years that seems to serve me
> well is to load a device to no more than 70% utilization when doing
> the initila design. You will ALWAYS find something you need to
> change/add as the design is brought up, and this will tend to fill the
> device.
> I would be scared to death of your device that was 99% utilized for
> two reasons....

I'm working on a design that requires 92% of the FFs in a 4010D
and it is routed usually without problems. It has LOTs of counters
and pipeline FFs to get to speed, so it's flipflop bound ( 40 MHz
in a -6 LCA, cannot get a faster chip because some units are 
already in the field.)

I think that PPR  spreads out the logic over as many blocks as it seems
usable if it is given the space; when i look at my chip in XACT i
_never_
see a free block. I feel i still could add a few bits worth of a LFSR
counter or shift registers, but adding a single long line decoder or a
multiplexer with lots of inputs or anything else that affects the
layout in a non-local way will break the routing for sure.

(Note that i don't use a single long line decoder and i have
LOTs of spare function generators.)


_Q_: Does anybody know the LOC= constraint to move a FlipFlop to an
unbonded I/O block? I don't care what block it may end up in, but
i do not want to see it in a CLB or in a usable pin.

Gerhard (still experimenting with Netscape 3, hope it works.)

--
Gerhard Hoffmann	
               ^  I must insist on that second 'n'.

on the air: dk4xp          in the air: D-1441
Article: 4698
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: Kate Meilicke <kate.meilicke@xilinx.com>
Date: Mon, 02 Dec 1996 12:58:12 -0500
Links: << >>  << T >>  << A >>
Mark,

Depending on how you wrote your VHDL code, Synopsys will automatically
optimize a flip-flop into the IOB.  

How did you implement the GSR?  If you have a reset signal connected
to the GSR on the startup block and have a reset signal in your
VHDL code, Synopsys thinks you want an asynchronous reset on 
the FF but the FF's in the IOB don't have an asynchronous reset so
Synopsys must put that FF in a CLB.  Synopsys doesn't understand
the GSR and how it works.  When it sees a reset in the VHDL code,
it attaches the reset line to the reset pin on the FF.  XNFPREP knows
that you are using the GSR so it strips the global reset line that
goes to the asynchronous reset pin o the FF's.

You should not have to use any special commands in the Synopsys script
file.

If all else fails, you can instantiate the IOB in your code.

Kate Meilicke
Xilinx FAE

Article: 4699
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: seward@fc.hp.com (Robert Seward)
Date: 2 Dec 1996 18:35:46 GMT
Links: << >>  << T >>  << A >>
Mark Sandstrom <Mark.Sandstrom@martis.fi> wrote:
>Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
>I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter
>what I try, all my I/O registers are mapped into the CLBs. I'm
>describing the I/O registers in the VHDL description in a normal
>D-flip-flop style. The flip-flops are controlled by the global reset for
>which I use the GSR net. 

>I tell Synopsys:

>set_register_type -exact -flip_flop OFD_F find (design, stm4_out_reg)
>Performing set_register_type on design 'stm4_out_reg'. 
>1

>but the flip_flops synthesize into 'FDC's.

>Thanks for any information that could help!

>Mark

I just recently ran into the same problem.  Synopsys is not the problem,
because it turns everything into generic registers.  It is XBLOX that
will move registers into IOBs.  There are a number of restrictions that
will prevent XBLOX from moving registers into an IOB, listed in the XBLOX
documentation somewhere.  I ended up hand-instantiating the output registers
that I wanted, and that did the trick.

Robert


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