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# Messages from 2000

Article: 2000
Subject: Re: FFT in FPGAs ?
From: jnoll@su19bb.ess.harris.com (John Noll)
Date: 29 Sep 1995 23:33:25 GMT
Links: << >>  << T >>  << A >>
In article lpo@marina.cinenet.net, kirani@cinenet.net (kayvon irani) writes:
> 	I'd like to know if any brave designer out there has tried to
> 	implement an FFT algorithm in an FPGA. Any one has experience
> 	with Mentor/Synopsys tools that take your algorithms and output
> 	VHDL synthesizable code?
>
> 	Regrards,
> 	Kayvon Irani
> 	Lear Astronics
> 	Los Angeles

I doubt it seriously.  With the largest FPGAs around you would be lucky to get one decent size
complex multiplier.  If you could get a CMPLY to fit in an FPGA with some room leftover (good
luck) then you could add some logic to read a RAM/PROM for the twiddle factors and sequence
through the input data.  Several passes and you would have an FFT.  I have given it serious
thought in the past as I have built many FFT processing boards and the answer, so far, has always
been the same:  not enough logic in and FPGA to do enough to make it worth while.  I have always
bought an FFT processor - Plessey, Sharp, LSI - there are many different good options out there
depending on what you need.
---
< < < < < < < < < < < < < < < < < < < < < < < < < < <
John Noll                       /~~\
jnoll@su19bb.ess.harris.com  /\/    \o\_
Palm Bay, Florida           /        \o\\


Article: 2001
From: mercure@primenet.com (Ray Saarela)
Date: Sat, 30 Sep 95 13:56:18 GMT
Links: << >>  << T >>  << A >>

FlexLogix/PLDShell combination from any distributor
regardless of continuos bugging. Then Altera promised
to send one as sample. Never came either ...

I would like to compare FlexLogic parts to AMD MACH and
Lattice ISP parts if I could get the cable somehow, and
I don't want to invest 100 dollars just on a cable ...
( AMD's cable and SW was free as well ... )

Could anybody please let me know the schematic of such a cable,
or where to get such a beast free or unexpensive ... ? Thanx ...


Article: 2002
Subject: Info needed for courses using FPGA and VHDL
From: choi@calliope.cps.msu.edu (Sea-Hawon Choi)
Date: 30 Sep 1995 15:13:36 GMT
Links: << >>  << T >>  << A >>

Hello, world:

We offered an entry level graduate course which utilizes VHDL
and FPGA technology.  Students wrote various
applications using VHDL and synthesized them for an
FPGA-based parallel machine. In this course, we
taught the VHDL language as well as features of FPGAs,
in the context of both embedded and parallel applications.

We are exploring the range of other university
integrate FPGA technology in a hands-on fashion
to support experiential learning in the course.
Courses may range from introductory to digital logic
design to computer architecture to compilers, and so on.
If so, we would be interested to know the type of course
and how FPGAs are used. What FPGA tools are used?
What kind of FPGA board/system is used as the target for
synthesis?  Is there a web page for the course?

If we feel the compiled information is valuable to
everybody, we will post the summary of responses.  Anyone
who provides information should indicate if the response
cannot be included in a summary and if they want a summary
sent directly to them.

Thank you very much for your valuable information.

Sincerely yours,
Sea Choi

choi@cps.msu.edu


Article: 2003
Subject: Re: REPOST: Design Contest Write-up (
From: paysan@informatik.tu-muenchen.de (Bernd Paysan)
Date: Sat, 30 Sep 1995 14:23:51 -0100
Links: << >>  << T >>  << A >>
In article <Pine.SUN.3.91.950928100918.16350D-100000@switha>,
Jonathan AH Hogg <jonathan@dcs.gla.ac.uk> wrote:
>
> it's still early days yet for hardware synthesis. no-one really
> understands what an HDL should look like. an HDL that's based on a
> software language is not a good starting point in my opinion. designing
> software and designing hardware are two different paradigms. since when
> did gate arrays have for' loops? software is based on control flow,
> hardware is based on data flow.
>
> we need to develop new tools and ways of working, not rubbish the whole
> concept and go back to rubbing stick diagrams together...

I like the idea of having a functional HDL. Many hardware constructs are
quite regular and use some sort of recursive algorithms to be constructed.
If I just had a behavioral '+', I don't know how it is synthesized (ok, I
can look into the library documentation). However, for different purposes I
may need different implementations of '+'. Say, for a performance counter
that increments a number each time an instruction is executed, I want to
have a JK-flipflop line (cheap, can be read if you stop counting), and for
the ALU I want to have a top speed carry lookahead adder.

A good approach would be if the HDL allows to specify hardware with all the
power of a functional language (recursive functions to create and arange
gates or transistors/capacities/resistors), give them a name and specify a
simulation behavior (a "specification" which can be used to speed up
simulation and can be verified with a proof program). These components could
then be used to form a behavioral description (and could be provided in a
library, so I as user don't have to think hard about how to implement a good
structured signed multiplication with 3:2 csas - but can break it down
for pipelining purposes, if I want to).

One problem with many current functional languages is, that they can only
return one value (usually). It is extremly important to have multiple
"values" returned, as a "value" in a functional HDL is a wire (or a vector
of wires). One alternativity is a Forth- or Postscript-like approach, i.e.
to use a stack to pass parameters.

--
Bernd Paysan
http://www.informatik.tu-muenchen.de/~paysan/


Article: 2004
Subject: Re: Altera Sim. with Leapfrog
Date: Sat, 30 Sep 1995 19:36:09 GMT
Links: << >>  << T >>  << A >>
In article <1995Sep29.123237.10669@arbi.Informatik.Uni-Oldenburg.DE>,

> Hi,
>
> we use the Synopsys Design Analyzer together with the technology
> libraries provided by Altera for VHDL synthesis targeting Altera
> Flex8000 FPGAs. Up to now we have used the Synopsys VHDL Simulator
> for simulation of the synthesized netlist. We are trying to
> integrate the Cadence Leapfrog simulator into our design flow
> because it promises to be much faster.
>
> Unfortunately, the simulation models of the Altera netlist primitives
> which are supplied together with version 5.2 of the MaxPlus2 software,
> are in Synopsys-specific "encrypted VHDL" (e.g. flex8000_FTGS.vhd.E)
> and can not be compiled with Leapfrog. If you know any workaround,
> because our department got their software for free in a university
> program.
>
Hi Martin,
I guess that you can have the Verilog import option of leapfrog.
if this guess is correct then use the verilog out option of MaxPlus2 -
which give you a verilog netlist ( built of built-in primitives and two
UDP's  - which you'll have to point with the -y option).
so to sum-up: use your VHDL original stimulus and drive your gate level
Altera netlist. the only catch in the flow is the fact that Altera is not
using (yet) SDF backannotation but rather net and delay parameters
associated with UDP's somewhat slow to simulate.
good luck
Zeev


Article: 2005
Subject: Re: AT&T ORCA usable gate count?
Date: Sun, 1 Oct 1995 00:31:45 GMT
Links: << >>  << T >>  << A >>
Chelman Wong <chelman@hal.com> writes:

>Can anyone tell me how the usable gate count
>for the AT&T ORCA's is calculated?

>And what is the general rule of thumb as to
>how many gates/cells and I/O's are really
>usable in a design?

I think that each cell (PFU or PLC) is counted as between 36 and 40
gates.  If you look at the actual cell schematic, it is a hell of a lot
more than 40 gates.  Actual  milage will vary depending on the type
of circuit the cell is used for.  The highest effective gate count
occurs when the cell is used as a 16x4 static ram with latched outputs.
A standard gate array equivalent for this function would burn about 300
to 500 gates (a gate is a 2 input nand gate).

As far as the usable number of cells, it's usually pretty close to 100%,
like that.  The I/O count is about the same.  The smallest part (2C04) has
160 IO pads.  That's pretty good for 4000 gates.

John McCluskey
J.McCluskey@ieee.org


Article: 2006
Subject: Re: Xilinx Flash FPGA ??
From: seeker@indirect.com (Stan Eker)
Date: 1 Oct 1995 20:00:26 GMT
Links: << >>  << T >>  << A >>
NICOLAS TRIBIE (tribien@esiee.fr) wrote:
: Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead
: of a SRAM ?

:  I need to have all the I/O ports free for my application.

I'd avoid doing it in parallel mode 'cos it forces too many of the IOBs (and
the connecting logic / internal delays) into a fixed configuration that you
may not be able to work with, later...

Just about EVERY one of Xilinx's customers has asked for EEPROM on chip for
*SECURITY* issues, but we've all been soundly ignored over the years.  They
keep prattling that it's secure 'cos they don't publish the download stream,
but I made a good start in figuring it out one afternoon, just to see if it
was true.  They're full of it.  If you have unscrupulous competitors (read:
thieves), they can reverse-engineer your design without too much effort.
It's not fun, but it IS do-able if you have the time and intent.  We're
pretty sure that one of our competitors ripped one of my designs that way.
Since there's no encryption, it's relatively simple to start with a blank
chip and set a bit, then see where it comes out in the config stream, then
repeat the process for the other bits.  Just a matter of time to get the
entire device mapped out, as it follows a fixed pattern (if memory serves).

the power up with a battery.  The Ic is low enough when static that it's a
realistic method of securing 'em.  Make sure you set it for READBACK NEVER.
You can make it even more obnoxious by putting traps in the system that
dump the battery if the case is opened, etc., and/or potting it.

For the parts of the design that really need security, use one of the PLDs
that *does* have EEPROM and a security bit, to slow the crooks down.  That
won't stop 'em, but it makes it significantly more expensive.


Article: 2007
Subject: Re: FFT in FPGAs ?
From: Ray Andraka <randraka@ids.net>
Date: 1 Oct 1995 23:05:34 GMT
Links: << >>  << T >>  << A >>
jnoll@su19bb.ess.harris.com (John Noll) wrote:
>
> In article lpo@marina.cinenet.net, kirani@cinenet.net (kayvon irani) writes:
> > 	I'd like to know if any brave designer out there has tried to
> > 	implement an FFT algorithm in an FPGA.

> I doubt it seriously.  With the largest FPGAs around you would be lucky to get one decent size
> complex multiplier.  If you could get a CMPLY to fit in an FPGA with some room leftover (good
> luck) then you could add some logic to read a RAM/PROM for the twiddle factors and sequence
> through the input data.  Several passes and you would have an FFT.  I have given it serious
> thought in the past as I have built many FFT processing boards and the answer, so far, has always
> been the same:  not enough logic in and FPGA to do enough to make it worth while.  I have always
> bought an FFT processor - Plessey, Sharp, LSI - there are many different good options out there
> depending on what you need.
> ---

You can get a butterfly processor into an Atmel AT6005 if you do
the CMULT in two cycles (this way it can be done with two array
multipliers (12x12 bit) a couple of adders and some steering logic.
The speed of the array multiplier limits performance to less than 5M
butterflys per second, which is substantially below the performance of
the GEC Plessey, Sharp, LSI or TRW chips.  This solution is cheaper
than the dedicated chips (which tend to run about $1K) however, and serves nicely to fill the performance/cost gap between the specialty chips and the GP DSP processors. If my memory serves me right, the TRW and LSI chips do 20M butterflys/sec, and the GEC Plessey can do up to 40M. I haven't used the Sharp chip yet. Another approach is to use a bit serial algorithm to do the FFT. again, the performance will be no better than about 5M butterflies, but there should be a substantial reduction in hardware, possibly allowing parallel processes. This technique should permit the FFT to be done in nearly any FPGA (with an external memory and coefficient ROM of course). It may even be possible to use Xilinx 4K memory to generate the coeffs. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure.  Article: 2008 Subject: Re: FlexLogic download cable/schematics for one ? From: devb@lys.vnet.net (David Van den Bout) Date: 1 Oct 1995 18:40:12 -0500 Links: << >> << T >> << A >> In article <44jlog$fk9@nnrp3.news.primenet.com>,
Ray Saarela <mercure@primenet.com> wrote:
>
>	FlexLogix/PLDShell combination from any distributor
>	regardless of continuos bugging. Then Altera promised
>	to send one as sample. Never came either ...
>
Ray:

that attaches to the PC printer port.  Instead, you can use a very simple
cable if you use a 7414 to clean up the signals at the receiving
end near the FLEXlogic FPGA.

Here's a description of the circuit we use.  All it takes is a simple
cable with a male DB-25 on one end and a 26-pin socket on the other.
You'll connect the socket to a 26-pin header on your protoboard and then
run your wires from the header to the EPX780. A 74LS14 is used to
eliminate noise on the TCK line.  Here's how you do it:

1) Connect pin 2 of the header to pin 13 of the 74LS14.  Then connect
pin 12 of the 74LS14 to pin 11 of the 74LS14.  Finally connect pin
10 of the 74LS14 to pin 53 of the EPX780.  This will remove noise
machine in the EPX780.
2) Connect pin 3 of the header to pin 1 of the 74LS14.  Then connect
pin 2 of the 74LS14 to pin 3 of the 74LS14.  Finally connect pin
4 of the 74LS14 to pin 52 of the EPX780.  This will remove noise
state machine.  This is not super-critical, but the gates are there
so we use them.
3) Connect pin 8 of the header to pin 11 of the EPX780.  This is the
4) Connect pin 10 of the EPX780 to pin 5 of the 74LS14.  Then connect
pin 6 of the 74LS14 to pin 9 of the 74LS14.  Finally, connect pin
8 of the 74LS14 to pin 11 of the header.  This will provide a signal
path for the TDO output from the EPX780 to the PC.  The PENGN software
uses this path to get status information out of the EPX780.
5) Connect pin 9 of the header to pin 12 of the header.  The PENGN
software uses this to detect the presence of the cable.  Without this,
PENGN will complain that the TAP cable is not present.
6) You can connect pins 4,5,6,7,8, and 9 of the header to any general-purpose
pins of the EPX780 that you want.  This will allow you to send logic
signals through the PC printer port to the EPX780.  This will make it
easier for you to test any designs you download.  You can omit this

--

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 2009
Subject: Re: Xilinx Flash FPGA ??
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 2 Oct 1995 07:52:54 GMT
Links: << >>  << T >>  << A >>
In article <44e440$48q@srv5.esiee.fr> NICOLAS TRIBIE, tribien@esiee.fr writes: >Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead >of a SRAM ? > > I need to have all the I/O ports free for my application. > I'm pretty sure the answer to this would be no, since it would require completely different silicon. It sounds like a fairly strange request to me, since the usual comment it just to use a larger package. Almost all the signal lines can be used for I/O after configuration, but that usually requires external logic. If you want a higher pin to logic ratio, you could try 4000Hs. Personally I've never used them, but I expect might have greater routing problems - remember that it is difficult to fully utilise an array. I would aim to only use 60% of the array for actual logic, which means that you can route more quickly initially and expand into the remainder if you really have to. _____________________________________________________________ Dr John Forrest Tel: +44-161-200-3315 Dept of Computation Fax: +44-161-200-3321 UMIST E-mail: jf@ap.co.umist.ac.uk MANCHESTER M60 1QD UK  Article: 2010 Subject: Re: REPOST: Design Contest Write-up ( From: torbenm@diku.dk (Torben AEgidius Mogensen) Date: 2 Oct 1995 09:32:06 GMT Links: << >> << T >> << A >> paysan@informatik.tu-muenchen.de (Bernd Paysan) writes: >One problem with many current functional languages is, that they can only >return one value (usually). It is extremly important to have multiple >"values" returned, as a "value" in a functional HDL is a wire (or a vector >of wires). One alternativity is a Forth- or Postscript-like approach, i.e. >to use a stack to pass parameters. THe usual approach for returning multiple values in a functional language is to return a tuple of values. The tuple is considered a single value, but consists of several (non-homogenous) components. Torben Mogensen (torbenm@diku.dk)  Article: 2011 Subject: Re: cheap (free) fpga design software From: "Troy R. Pesola" <troy@cyberoptics.com> Date: 2 Oct 1995 12:58:21 GMT Links: << >> << T >> << A >> There is a package for Linux called 'Alliance' that appears to be a VHDL package. I have not used it, so I can not give details. It might be worth taking a closer look. Here is the main site: ftp://ftp.ibp.fr/ibp/softs/masi/alliance/ The Linux version can be found off of apps/circuits on sunsite. ftp://sunsite.unc.edu/pub/linux/apps/circuits -------------------------------------------------------------- These opinions are mine, ALL mine. -------------------------------------------------------------- Troy R. Pesola troy@cyberoptics.com CyberOptics Corp. trp@starfire.mn.org 612)331-5702 http://www.cyberoptics.com/~trp --------------------------------------------------------------  Article: 2012 Subject: Re: Xilinx Flash FPGA ?? From: "Steven K. Knapp, Xilinx, Inc." <stevek> Date: 2 Oct 1995 18:26:03 GMT Links: << >> << T >> << A >> seeker@indirect.com (Stan Eker) wrote: >NICOLAS TRIBIE (tribien@esiee.fr) wrote: >: Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead >: of a SRAM ? > >: I need to have all the I/O ports free for my application. > >If you serially download it, you don't lose anything. After configuration, >all of the pins not already dedicated to downloading are free for your app. >I'd avoid doing it in parallel mode 'cos it forces too many of the IOBs (and >the connecting logic / internal delays) into a fixed configuration that you >may not be able to work with, later... > >Just about EVERY one of Xilinx's customers has asked for EEPROM on chip for >*SECURITY* issues, but we've all been soundly ignored over the years. They >keep prattling that it's secure 'cos they don't publish the download stream, >but I made a good start in figuring it out one afternoon, just to see if it >was true. They're full of it. If you have unscrupulous competitors (read: >thieves), they can reverse-engineer your design without too much effort. >It's not fun, but it IS do-able if you have the time and intent. We're ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >pretty sure that one of our competitors ripped one of my designs that way. >Since there's no encryption, it's relatively simple to start with a blank >chip and set a bit, then see where it comes out in the config stream, then >repeat the process for the other bits. Just a matter of time to get the >entire device mapped out, as it follows a fixed pattern (if memory serves). > I agree that with enough time and effort, somebody can reverse engineer the bitstream. A few things to make it infinitely harder is to set the READBACK NEVER bit during MakeBits and to run the TIE option. The TIE option connects any unused functions to a Ground, Vcc, or a known value. It does this by using up all unused interconnect. This option should be used for any production bitstreams because it also reduces quiescent current. All that extra tied interconnect makes the interconnect data much more difficult to reverse engineer. Remember, all 2^18,000+ locations need to be correct before you have the full design. This is a daunting task. >Some folks have had reasonably good luck in downloading 'em and then backing >the power up with a battery. The Ic is low enough when static that it's a >realistic method of securing 'em. Make sure you set it for READBACK NEVER. >You can make it even more obnoxious by putting traps in the system that >dump the battery if the case is opened, etc., and/or potting it. > >For the parts of the design that really need security, use one of the PLDs >that *does* have EEPROM and a security bit, to slow the crooks down. That >won't stop 'em, but it makes it significantly more expensive. > Securing a design also depends on the technology. Here are a few suggestions: SRAM-based FPGAs: Battery backed designs provide best security. EPLDs: Use a device with _multiple_ security bits. Most of the devices on the market contain a single security bit. There are "reverse" engineering groups in Asia that easily overcome a single security bit. Usually, the security bit is off, by itself, on the die and easy to identify. The Xilinx XC7300 family has multiple security bits embedded in the product term array. It is virtually impossible to erase all of the security bits without erasing the design. (see http://www.xilinx.com/products/epldspec.htm ) MicroVia-based FPGAs: The XC8100 is based on a MicroVia anti-fuse. The fuse is buried beneath a layer of metal and oxide. Consquently, the XC8100 FPGA family is more secure than even a gate array. The programmed MicroVias are not observable whereas a gate array's metal can be view directly with an optical microscope. (see http://www.xilinx.com/products/fpgaspec.htm#XC8100 ) -- Steve Knapp Corporate Applications Manager Xilinx, Inc.  Article: 2013 Subject: Re: FPGA for a 20k gates micro-controller. From: "Steven K. Knapp, Xilinx, Inc." <stevek> Date: 2 Oct 1995 18:44:57 GMT Links: << >> << T >> << A >> DGVR59A@prodigy.com (Cahill schmitz Cahill) wrote: >I heard that Altera's new Flex 10k family will be well suited to >implementing a core micro controller. They supposedly implemented one >which was then used to control a very old Apple computer running at 8 MHz. > The EAB (embedded array block) is a complex function generator useful >to genereate complex functions very effectively (ie. 4x4 multiplier). >The total implementation was about 10K gates. They used a HDL to >describe the functions of the machine instructions which were then >synthsized and compiled into the device. > >Best of Luck in your search. > This design is probably the venerable 6502 processor used in the Apple II. We have also implemented this design from VHDL. It fits in 90% of a 6,000-gate Xilinx XC8106 FPGA. We put the programmed XC8106 on a daughter card and plugged it into an old Apple II. It runs Apple II software without modification. For more information on the MicroVia-based XC8100 FPGA family, see http://www.xilinx.com/products/fpgaspec.htm#XC8100 -- Steve Knapp Corporate Applications Manager Xilinx, Inc.  Article: 2014 Subject: Re: cheap (free) fpga design software (VHDL) From: ree@ix.netcom.com (Brad Ree ) Date: 3 Oct 1995 01:44:39 GMT Links: << >> << T >> << A >> In <44onld$nuj@ncyber-gw.cyberoptics.com> "Troy R. Pesola"
<troy@cyberoptics.com> writes:
>
>There is a package for Linux called 'Alliance' that
>appears to be a VHDL package.  I have not used it, so I can
>not give details.  It might be worth taking a closer look.

For what it is worth, I would be very carefull in using VHDL for
FPGA designs, especially if the compiler is cheap or free.  I have
found VHDL to be very slopy in its synthesis, and can cause days of
headaches for high speed designs.  Keep in mind that you are designing
logic, and not just running some program on a pentium.  Also, keep in
mind the old saying that you don't get something for nothing.  I have
found Xilinx's development packages very resonable for what you get.
offer limited versions of their software for close to nothing.
However, they do not always come with a simulator, or do not support
large gate count devices.  I suggest that accept the fact that software
cost money, and just invest in a good package.


Article: 2015
Subject: To John Cooley and other members of the FPGA industry:
From: amaraju@onramp.net (Eddie Amara)
Date: Mon, 02 Oct 1995 22:06:55 -0500
Links: << >>  << T >>  << A >>
      I am sincerely sorry for what has happened, and especially for my
actions relating to the comments made by me on the internet directed at an
engineer.  My  actions were wrong and unprofessional. I have no excuses. I
hope you will accept my apology, and rest assured that nothing similar
will occur again.
At SpencerSearch, it has been my responsibility to use the internet
to advertise our openings and handle the internet part of our business. I
generally post our openings in the jobs newsgroups where it is appropriate
to do so. As I have learned more about the internet and the resources that
are available to us, I discovered the discussion groups may be a way to
network also. I tried a few openings, and some of them asked nicely that I
did not post there anymore, which I honered. Some did not seem to mind, so
I experimented further. From now on, I will keep my postings where they
belong, and act in a more professional manner.
I have never before experienced the embarrassment that I have felt
from this mistake. I let Dan, my fellow recruiters, and AT&T down. Dan and
I have reviewed this issue, and you can be assured that it will not occur
again.
My apology at this time cannot undo past damage. My regret is
sincere. My efforts in the future will be guided by this experience. I
hope to continue to do my best to serve my candidates and my clients.
Additionally, as a result of this incident, I will no longer be
recruiting for AT&T's FPGA group. Any interested party should either
contact them directly or Dan Spencer of SpencerSearch at 512-259-3531.

Sincerely,

Eddie Amara

--
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 2016
Subject: (no subject)
Date: 3 Oct 1995 09:49:24 GMT
Links: << >>  << T >>  << A >>
Hi,

It is well known that when performing timing simulation with
QuickSim , on Designs which contain xilinx XBLOX elements,
Then it is not possible to descend down in the hierarchy of
the design and add traces of internal signals. The whole
design is flatenned and the only signals that can be monitored
are the input and output signals.

Does anybody know a way to add traces of internal signals
(possibly by using a force file ) ????
I have tried several things on the force files but they were
not successful.

Thanks,

VLSI Systems Engineering.


Article: 2017
Subject: (no subject)
Date: 3 Oct 1995 10:58:02 GMT
Links: << >>  << T >>  << A >>
Hi,

It is well known that when performing timing simulation with
QuickSim , on Designs which contain xilinx XBLOX elements,
Then it is not possible to descend down in the hierarchy of
the design and add traces of internal signals. The whole
design is flatenned and the only signals that can be monitored
are the input and output signals.

Does anybody know a way to add traces of internal signals
(possibly by using a force file ) ????
I have tried several things on the force files but they were
not successful.

Thanks,

VLSI Systems Engineering.


Article: 2018
Subject: QUICKSIM & XBLOX HELP
Date: 3 Oct 1995 10:58:28 GMT
Links: << >>  << T >>  << A >>
Hi,

It is well known that when performing timing simulation with
QuickSim , on Designs which contain xilinx XBLOX elements,
Then it is not possible to descend down in the hierarchy of
the design and add traces of internal signals. The whole
design is flatenned and the only signals that can be monitored
are the input and output signals.

Does anybody know a way to add traces of internal signals
(possibly by using a force file ) ????
I have tried several things on the force files but they were
not successful.

Thanks,

VLSI Systems Engineering.


Article: 2019
Subject: Re: QUICKSIM & XBLOX HELP
From: Guy LEONHARD <leonhard>
Date: 3 Oct 1995 11:42:57 GMT
Links: << >>  << T >>  << A >>
To add traces of internal signals you must specified the exact name of the
signal you want to see.
Example:

wave simdma.wfw $1I463\end_cycle$1I463\end_dma
$1I463 specified in which componant or sheet the signal is located. Hope this helps. Guy LEONHARD e-mail: Guy.Leonhard@enst-bretagne.fr  Article: 2020 Subject: Re: FlexLogic download cable/schematics for one ? From: ianb@epid.eurotherm.co.uk (Ian Baines) Date: Tue, 3 Oct 1995 13:07:20 GMT Links: << >> << T >> << A >> mercure@primenet.com (Ray Saarela) wrote: > I haven't been able to purchase a download-cable for > FlexLogix/PLDShell combination from any distributor > regardless of continuos bugging. Then Altera promised > to send one as sample. Never came either ... > I would like to compare FlexLogic parts to AMD MACH and > Lattice ISP parts if I could get the cable somehow, and > I don't want to invest 100 dollars just on a cable ... > ( AMD's cable and SW was free as well ... ) > Could anybody please let me know the schematic of such a cable, > or where to get such a beast free or unexpensive ... ? Thanx ... > Appreciados, Hg++ > I have the Intel schematic for the cable interface. It is only a '244 in a printer cable shell. Unfortunately it is only a paper copy. If you let me have your fax number I will send it to you. The Flexlogic parts are architecturally better than the AMD MACHs and the JTAG programming is a great bonus for production programming. Pity Altera charge so much for them! _____________________________________________________________ Ian Baines Eurotherm PID R&D work ianb@epid.eurotherm.co.uk Southdownview Way home ianb@mistral.co.uk Worthing, Tel +44(0)1903-205277 Fax +44(0)1903-524016 BN14 8NN, UK  Article: 2021 Subject: Xilinx security From: davem@hbmltd.demon.co.uk Date: Tue, 03 Oct 95 07:59:00 XAC Links: << >> << T >> << A >>  Newsgroups: comp.arch.fpga Date: Tue, 03 Oct 95 07:49:23 XAC From: davem@hbmltd.demon.co.uk Subject: Re: Xilinx Flash FPGA ?? X-Newsreader: NEWTNews & Chameleon -- TCP/IP for MS Windows from NetManage References: <44e440$48q@srv5.esiee.fr> <44ms0r$kmm@globe.indirect.com> <44parr$cqj@mailman.xilinx>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII

In article <44parr$cqj@mailman.xilinx>, <stevek@hbmltd.demon.co.uk> writes: > SRAM-based FPGAs: Battery backed designs provide best security. I have designed Xilinx with (lithium) battery back up for security. Things to know: 1) Xilinx have neve *guaranteed* that the powerdown current is pico-amps. It usually is, but if you get a batch that takes uA from the battery there is no comeback. 2) The "POWEDOWN" pin must be held *reliably* low at all times with respect to the battery back-up voltage. Most powerdown chips will not do this - the output goes high Z when Vcc drops below 2V (the powerdown chip is usually not battery backed up. If POWERDOWN pin goes high - even momentarily, say during ramp-up of Vcc at power-on, the Xilinx starts to wake up, & draws current from the battery. The design of the powerdown cct is therefore not trivial. > > EPLDs: Use a device with _multiple_ security bits. Most of the devices on the But if you can get the bit-stream directly from the serial EEPROM or monitor CLK and DIN, the security bits don't make any difference. =========== Dave Mould ===========  Article: 2022 Subject: Re: cheap (free) fpga design software (VHDL From: jeffh@oakhill-csic.sps.mot.com (Jeff Hunsinger) Date: 3 Oct 1995 15:25:29 GMT Links: << >> << T >> << A >> In article afn@ixnews4.ix.netcom.com, ree@ix.netcom.com (Brad Ree ) writes: > For what it is worth, I would be very carefull in using VHDL for > FPGA designs, especially if the compiler is cheap or free. I have > found VHDL to be very slopy in its synthesis, and can cause days of > headaches for high speed designs. VHDL doesn't perform the synthesis, the synthesis tool does. The language used to describe your circuit (VHDL, Verilog, etc) is a separate issue. I agree, however, that using a free tool can give more headaches than it's worth. If you can't afford the mainstream tools, you'll have a tough time doing any "real" designs. However, there are some tools that are a bit less expensive.$1000 seems to be the
minimum.

Jeff


Article: 2023
Subject: Call For Papers: FCCM'96
From: jma@descartes.super.org (Jeffrey M. Arnold)
Date: Tue, 3 Oct 1995 15:53:41 GMT
Links: << >>  << T >>  << A >>

#######  #####   #####  #     #           ###    #####   #####
#       #     # #     # ##   ##           ###   #     # #     #
#       #       #       # # # #            #    #     # #
#####   #       #       #  #  #           #      ###### ######
#       #       #       #     #                       # #     #
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#        #####   #####  #     #                  #####   #####

C A L L    F O R    P A P E R S

THE FOURTH ANNUAL
IEEE SYMPOSIUM ON FPGAs FOR CUSTOM COMPUTING MACHINES
Napa, California
April 17-19,1996

http://www.super.org:8000/FPGA/fccm96.html

PURPOSE:  To bring together researchers to present recent work
in the use of Field Programmable Gate Arrays or other devices as
reconfigurable computing elements.  This symposium will focus
primarily on the current opportunities and problems in this new and
evolving technology for computing.  Contributions are solicited on
all aspects of custom computing, including but not limited to:

Coprocessors for augmenting the instruction set of general-
purpose computers;

Attached processors for specific purposes (e.g. signal and image
processing);

Languages, compilation techniques, tools, and environments for
programming;

Application domains;

Prototyping for architecture emulation;

Use of custom computing in education.

SUBMISSIONS: Authors are invited to send submissions (4 copies, 10 pages
double-spaced maximum) by January 12, 1996, to Jeffrey Arnold.
Notification of acceptance will be sent in early March.  Final papers
will be due on the first day of the symposium.  After the Symposium a

Authors may also submit PostScript versions of papers by FTP.  For
instruction on electronic submission, please see the Web page or
contact Jeffrey Arnold.

SPONSORSHIP: The IEEE Computer Society and the Technical Committee on
Computer Architecture.

CO-CHAIRS:
Kenneth L. Pocek
Intel
Mail Stop RN6-18
2200 Mission College Boulevard
Santa Clara, California  95052
Voice: 408-765-6705  Fax: 408-765-5165
kpocek@sc.intel.com

Jeffrey M. Arnold
IDA Center for Computing Sciences
17100 Science Drive
Bowie, Maryland 20715
Voice: 301-805-7479  Fax: 301-805-7604
jma@super.org

ORGANIZING COMMITTEE:
Peter Athanas, Virginia Tech.
Donald Bouldin, University of Tennessee, Knoxville
Duncan Buell, Center for Computing Sciences
Michael Butts, Quickturn Design Systems, Inc.
Pak Chan, Univ. California, Santa Cruz
Apostolos Dollas,  Technical Univ. of Crete
Frederick Furtek, Atmel Corporation
Tom Kean, Xilinx, Inc. (U.K).
Phil Kuekes, HP Labs.
Wayne Luk, Imperial College


Article: 2024
Subject: Re: FPGA for a 20k gates micro-controller.
From: ebcerra@ebc.ericsson.se (Raquette Eric)
Date: 3 Oct 1995 16:55:27 GMT
Links: << >>  << T >>  << A >>
In article <44pbv9\$cqj@mailman.xilinx>, "Steven K. Knapp, Xilinx, Inc." <stevek> writes:
>DGVR59A@prodigy.com (Cahill schmitz Cahill) wrote:
>>I heard that Altera's new Flex 10k family will be well suited to
>>implementing a core micro controller.  They supposedly implemented one
>>which was then used to control a very old Apple computer running at 8 MHz.
>>  The EAB (embedded array block) is a complex function generator useful
>>to genereate complex functions very effectively (ie. 4x4 multiplier).
>>The total implementation was about 10K gates.  They used a HDL to
>>describe the functions of the machine instructions which were then
>>synthsized and compiled into the device.
>>
>>Best of Luck in your search.
>>
>This design is probably the venerable 6502 processor used in the Apple II.  We
>have also implemented this design from VHDL.  It fits in 90% of a 6,000-gate
>Xilinx XC8106 FPGA.  We put the programmed XC8106 on a daughter card and
>plugged it into an old Apple II.  It runs Apple II software without
>modification.
>

Has anyone implemented a 6809 to fit in a FPGA?

/Eric

`