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Messages from 2150

Article: 2150
Subject: Re: Chip Express Expreiences Wanted
From: Nelson.Willhite@AtlantaGA.ATTGIS.com (Nelson Willhite)
Date: Fri, 20 Oct 1995 13:59:25 GMT
Links: << >>  << T >>  << A >>
In article <463h9i$pcl@su102w.ess.harris.com>,
   tboydsto@su102s.ess.harris.com (Ted Boydston) wrote:
>I am getting ready to produce a quick turn ASIC by translating an fpga XNF
>netlist to ASIC.  One of the vendors we are considering to perform this task is
>Chip Express; therefore, I was wondering if anyone has had any experiences they
>could relay to me about Chip Express's translation process.
>
>Specifically:
>
>* How much time was spent translating your design?
>* How many problems did you run into?
>* Did you participate in the translation process or did Chip Express do all the 
work?
>* What did they require of from you to perform the translation?
>
>Since I have personally gone through a translation process, I know that it is 
riddled
>with many pitfalls.  This fact makes me wonder if Chip Express's (as well as 
other
>quickturn vendors--like Orbit) brochures oversimplify the issue.
>
>Any information would be greatly appreciated.
>
>Thanks :)
>

I am interested in information on Chip Express as well.  If e-mailing a response 
to this posting, please copy me on the response.

We have just completed an FPGA conversion with Orbit Semiconductor.  Since they 
were mentioned, I thought I'd comment briefly.  We used VHDL for design entry and 
mapped a ~2K gate design operating at 2.3 MHz to an Altera FPGA using Synopsys 
FPGA Compiler.  (Yes, I know, not lightening speed or density.)  After testing 
this design in the FPGA, we sent Orbit the following information:

1. EDIF Netlist (Synopsys Output)
2. Print-on-change style simulations from Mentor Graphics Quicksim II
3. Desired Package/Pinout
4. Package Marking

Orbit successfully converted this design into their Encore! gate array process 
with very little interaction from our engineering group.  In fact, the level of 
interaction required was so minimal it bothered us!  They completed the conversion 
and had working parts in our hands in about 8 weeks (just within the upper 
variance of their commited design schedule).  The parts performed 100% to 
specification.

After meeting with their Engineering staff in Sunnyvale last month, I learned that 
Orbit is much more successful with designs generated from a top-down, synochronous 
design methodology (as most ASICs are developed), as opposed to schematic-based 
FPGA designs which tend to be problematic.

Orbit's process technology is not the most advanced (1 micron I believe), but they 
are VERY cost-effective.  I would recommend them for small to medium size 
(up to 45K gates) designs up to moderate speeds.  They offer superior value, 
particularly in low volumes.  (We only needed around 2,000 parts, but couldn't use 
an FPGA for production due to the board layout...  we needed a drop-in 
replacement for an obsolete part.)  The nearest ASIC competitor quoted 2.5 times 
the NRE for this design and wanted a guarantee of 6K parts!  I highly recommend 
Orbit Semiconductor for FPGA conversions... they are very experienced.

Hope others find this information useful...


----------------------------------------------------------------------
Nelson W. Willhite                               phone: (770) 623-7417
AT&T Global Information Solutions                  FAX: (770) 623-7044
Retail Products & Systems - Atlanta                VoicePLUS: 751-7417
2651 Satellite Boulevard
Duluth, Georgia 30136

email: Nelson.Willhite@AtlantaGA.ATTGIS.COM
----------------------------------------------------------------------



Article: 2151
Subject: Re: Chip Express Expreiences Wanted
From: hinter@dtc.kodak.com (David Hinterberger)
Date: 20 Oct 1995 18:18:02 GMT
Links: << >>  << T >>  << A >>
I would also appreciate that information. Please include me in that response.

---

David Hinterberger
Eastman Kodak, ASIC Design Group, Digital Technology Center
Phone:     716-726-7202		Fax:       716-726-7131
E-Mail:    hinter@dtc.kodak.com
Mail:      901 Elmgrove Road, Rochester, NY 14653-5211



Article: 2152
Subject: Problem using Xilinx XC4025
From: d0mo@dtek.chalmers.se (Mats Olsson)
Date: 20 Oct 1995 19:56:54 GMT
Links: << >>  << T >>  << A >>
Hello!

I have some problems regarding the XC4025 and I hope someone is
able to give me some hints about it.

First, the device is very hard to route. Even though it is only filled to 50%,
ppr may fail to route it. If it can route it, it takes _hours_ to get is
acceptable.

My current design fills the device to about one third, and doues route, but
I have BIG problems with the timing.
To be more specific, the design is a simple signal processor whith four
16-bit data buses, about 12 XBLOX-add_sub, some  16-bit registers and
many state machines. I only use one clock  (15MHz), but I have an 7.5MHz
internally generated clock-enable to about half the registers (total about
900 ff's).

I use four timespec statements, from 15M to 15M=66ns, from 15M to 7,5M=
66ns, from 7.5M to 15M=66ns and from 7.5M to  7.5M=133 ns.

PPR is able to meet three of the four timespecs, but the one specifying
from 15M to 7,5M is increased to 150!!

I have tried everything, but nothing helps..

HELP!!




Article: 2153
Subject: Re: Help - Searching an PLD/FPGA Selection Software
From: "Steven K. Knapp, Xilinx, Inc." <stevek>
Date: 20 Oct 1995 20:00:55 GMT
Links: << >>  << T >>  << A >>
>David Pashley <david@fpga.demon.co.uk> wrote:
>"
>"
>There's a product out there called PLD Pilot, which contains 
>comprehensive databook info on every PLD and FPGA, as well as 
>macrocell diagrams etc, and the ability to search by various 
>criteria.
>
>I'll try to find contact details...
>
Check out

http://www.reconfig.com/pilot.html

on the Web.  I've downloaded PLD Pilot demo.  It has quite a bit of
info.  My only caveat is to be wary that it may not include the
latest information.

-- Steve Knapp
   Xilinx, Inc.



Article: 2154
Subject: My own hard macro in VHDL?
From: cheng@news.cs.columbia.edu (Fu-Chiung Cheng)
Date: 20 Oct 1995 17:37:47 -0400
Links: << >>  << T >>  << A >>

Hi there,

	I would like to design some components with my own rounting
and these components can be used in VHDL programs.  Thus, I have to 
use Hardmacro. I am using Viewlogic and XACT on Sun workstation.

 	I try the following ways:

1. In Viewlogic Schemtic tool, I can use FMAP (for XC4000). I 
sucessfully use "expt1076" to convert a schematic file to a VHDL
program. But when I want to compile VHDL, it gives me error message.
Could anyone point me how to use FMAP in VHDL? 

2. I can use XDE to generate a .lca file. My question is 
how can I make it (the .lca file) a VHDL component so that I can use 
this "hard macro" component in VHDL programs.

	Is the above doable in Viewlogic and XACT? Does anyone 
have better idea?
	
	Thank you very much in advance.

							-John Cheng



Article: 2155
Subject: FPGAs as a substitute for glue logic?
From: duraid@zip.com.au (Duraid Madina)
Date: 21 Oct 1995 01:55:07 GMT
Links: << >>  << T >>  << A >>
I gather FPGAs are used as a nice way of getting around the millions (or too 
many, at least :) of simple ICs that creep their way into designs. (hello 
74ls08 :) However, I've found no simple way that will let me take my design, 
with glue logic, and implement that in an FPGA such that it's the same 
design, just with an FPGA instead of many discrete ICs.

	Someone help me!

Also, are there any inexpensive ways to accomplish my task? (I'm a school 
student - aargh!)

		...Duraid Madina



Article: 2156
Subject: China business guide
From: keysoft@public.sta.net.cn
Date: 22 Oct 1995 04:36:05 GMT
Links: << >>  << T >>  << A >>

               A DIRECT WAY TO REACH CHINESE BUSINESS

   CHINESE INDUSTRIAL & COMMERCIAL GUIDE V95 is a newly-developed software
runs on  Windows .  It  is based on the database including 38000 records
about main Chinese Industrial & Commercial operations. We have carefully
selected these companies, only those who have good business records are qua-
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Agriculture, Forestry, Fishery, Animal Husbandry, Mining, Food, Textile &
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mobile, Locomotive & Rolling Stock, Shipbuilding, Aircraft, Aerospace, Com-
puter & Software, Electronic Appliances, Chemical & Household Chemical,
Pharmaceutic, Instrument & Meter, Medical Apparatus & Instrument, Tourism &
Transport, Postal & Telecommunication Service, Construct, Mass Media, Adver-
tisement and other fields. All the information is in English.

   China is developing its economy at an ultra speed, it's the time now to 
seek the world's potentially biggest market or to get it's excellent and
inexpensive goods. The Guide will surely be a direct way to reach Chinese
businesses. The powerful browsing, retrieving and printing function can give
you convenience.  Each record shows the company's Address, Zip Code, Tel/Fax
number, President's Name, Main Products and the SIC (Standard Industrial
Code) number. 

   The whole package costs only $1100 (U.S.). This means that each record
will cost 2.9 (cent) only and the world-wide EMS or DHL service fee have al-
ready been included.

   Give your order now to get a short-cut expanding your business!

   Please pay by T/T(Telegraph Transfer) to:
	Keysoft Co.,ltd. Shanghai
	THE PEOPLE'S CONSTRUCTION BANK OF CHINA, 
	SHANGHAI  BRANCH,  XUHUI SUB-BRANCH.
	Account No.: 5122-20026513158

   In order to get the software as soon as possible, please FAX us  your
name, address, Zip code, phone number and Internet E-mail address if  you
have, also don't forget to attach the copy of the T/T voucher. We will im-
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   Thanks & Best Regards!

   Sincerely Yours: 
        ******************************************************************
	Keysoft Co.,ltd., Shanghai, P.R.China
	Tel: 86-21-64823578 64823579;  Fax: 86-21-64823381
	E-Mail: keysoft@public.sta.net.cn
	Add.: 2F, Astronautics Tower, 222 CaoXi Rd., Shanghai 200233 PRC.
        ******************************************************************



Article: 2157
Subject: Re: PLD in small package ?? anyone
From: devb@lys.vnet.net (David Van den Bout)
Date: 22 Oct 1995 08:11:36 -0500
Links: << >>  << T >>  << A >>
In article <46d214$o46@ping1.ping.be>,
Vincent Himpe <Vincent.Himpe@ping.be> wrote:
>
>Are there any FPGA / EPLD / whatever  with low pincounts and lot's of
>gates ?.
>My deisgns mostly use serial communication and don't need lots of I/O.
>So it's pretty silly to put an 132 pin PQFP on your board when you are
>only using 12 pins.

You might look at ICT's PEEL arrays.  The PA7024 (the smallest) has
20 I/Os but 40 registers/latches.  It's still not as small as you
want since it's in a 24-pin DIP, but it's one of the few small
programmable devices I know that doesn't limit the number of
latches to the I/O count.  ICT's phone is (408) 434-0678.  I've never
used the PEEL arrays so I don't know how good they are.


-- 

||  Dave Van den Bout  --   XESS Corp.   ||
||  devb@xess.com      -- (919) 387-1302 ||


Article: 2158
Subject: PLD in small package ?? anyone
From: Vincent.Himpe@ping.be (Vincent Himpe)
Date: Sun, 22 Oct 1995 17:52:29 GMT
Links: << >>  << T >>  << A >>
Hi,

I need a pld that comes in an 8 pin package and something like 16 ff's
and a bunch of colmbinatorial stuff. Pretty much like an iPLD610 or
610 from altera but squeezed into an 8 pin package.
Anyone ? PLLC28 is still too large for me.
I only have 5 I/O's  the rest is buried.

Are there any FPGA / EPLD / whatever  with low pincounts and lot's of
gates ?.
My deisgns mostly use serial communication and don't need lots of I/O.
So it's pretty silly to put an 132 pin PQFP on your board when you are
only using 12 pins.

Regards
vincent



Article: 2159
Subject: Re: PLD in small package ?? anyone
From: wa1hoz@a3bbak.nai.net (Gerry Belanger)
Date: 23 Oct 1995 01:18:24 GMT
Links: << >>  << T >>  << A >>
David Van den Bout (devb@lys.vnet.net) wrote:

: You might look at ICT's PEEL arrays.  The PA7024 (the smallest) has
: 20 I/Os but 40 registers/latches.  It's still not as small as you
: want since it's in a 24-pin DIP, but it's one of the few small
: programmable devices I know that doesn't limit the number of
: latches to the I/O count.  ICT's phone is (408) 434-0678.  I've never
: used the PEEL arrays so I don't know how good they are.

Actually their PEEL parts are pretty good; if you can get them 
when you need them.  Since they are fabless, they are at the mercy
of their foundries.  And since AMI no longer fabs/second sources,
you may get stuck with long lead times.

--
Gerry Belanger, WA1HOZ                      wa1hoz@a3bbak.nai.net
Newtown, CT                                 g.belanger@ieee.org



Article: 2160
Subject: Re: My own hard macro in VHDL?
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 23 Oct 1995 07:52:37 GMT
Links: << >>  << T >>  << A >>
In article <199510202137.RAA02235@ground.cs.columbia.edu> Fu-Chiung
Cheng, cheng@news.cs.columbia.edu writes:
>	I would like to design some components with my own rounting
>and these components can be used in VHDL programs.  Thus, I have to 
>use Hardmacro. I am using Viewlogic and XACT on Sun workstation.
>
> 	I try the following ways:
>
>1. In Viewlogic Schemtic tool, I can use FMAP (for XC4000). I 
>sucessfully use "expt1076" to convert a schematic file to a VHDL
>program. But when I want to compile VHDL, it gives me error message.
>Could anyone point me how to use FMAP in VHDL? 
Perhaps I'm missing something,  but in my book FMAPs are not hardmacros.

>
>2. I can use XDE to generate a .lca file. My question is 
>how can I make it (the .lca file) a VHDL component so that I can use 
>this "hard macro" component in VHDL programs.
>
What ever you want to do, what you need to create is a hierarchical xnf,
with the hardmacro (or predefined block or whatever) as a subunit. This
tends to imply structural VHDL, but it map also relate to function calls
inside a process/procedure. ASYL, which we use, has the notion of a
black-box map - where particular operators at least can be mapped to
arbitrary xnf. You need something similar.

You don't say which version of XACT you use, but they are supposed to be
a thing of the past. I've not used their replacements for XACT v5, but we
did try something similar with the previous software - it required
getting some extra tools for Xilinx to allow the designs from Xde to be
made into hardmacros.

John
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD,UK     URL: http://www.ap.co.umist.ac.uk/~jf


Article: 2161
Subject: Re: Where to find more info on PCI
From: Christian Grebe <grebe>
Date: 23 Oct 1995 09:54:11 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

---------------------------------110932314213284245191748639348
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset=us-ascii

You should try the PCI Special Interest Group (PCI SIG) Home Page:

	http://www.teleport.com/~pc2/pcisigindex.html

There you can subscribe to the Internet mailing list, which serves as a
newsgroup for topics around designing PCI devices.

Regards

Christian Grebe


Here are instructions for the mailing list:

---------------------------------110932314213284245191748639348
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>From pci-sig-request@znyx.com Tue Sep 26 13:51:05 1995
From: pci-sig-request@znyx.com
Date: Tue, 26 Sep 95 05:42:39 -0700
To: grebe@sun2.zfe.siemens.de
X-Loop: pci-sig@znyx.com
Reply-To: Please.write.a.new.mail.instead.of.replying@FIRST.WORD.archive
Content-Id: <rules%pci-sig-request@znyx.com>
Subject: archive retrieval: rules
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Status: RO
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File: rules
BEGIN------------cut here-------------
                          =============
                          PCI SIG GROUP 
                       Internet Mailing List
                       =====================

Purpose
-------

This Internet mailing list is provided to help in the distribution
of pertinent information regarding the PCI bus, as specified by the
PCI Special Interest Group.  The PCI bus has suddenly become one of
the most important developments in the computer industry, 

The topics for discussion may be anything of general interest to
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This mailing list is *not* the official information dissemination for 
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Another area we wish to avoid is silicon product specific and BIOS 
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If your name server cannot resolve znyx.com, the Internet address
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%%% EOF %%%

END--------------cut here-------------


---------------------------------110932314213284245191748639348--


Article: 2162
Subject: Re: FPGAs as a substitute for glue logic?
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Mon, 23 Oct 95 14:19:31 GMT
Links: << >>  << T >>  << A >>
In article <469jtr$vgg@zipper.zip.com.au>,
   duraid@zip.com.au (Duraid Madina) wrote:
>I gather FPGAs are used as a nice way of getting around the millions (or too 
>many, at least :) of simple ICs that creep their way into designs. (hello 
>74ls08 :) However, I've found no simple way that will let me take my design, 
>with glue logic, and implement that in an FPGA such that it's the same 
>design, just with an FPGA instead of many discrete ICs.
>

Generally, FPGAs require synchronous design.
Why won't your design (including glue logic) fit into the FPGA?
Size problems, or design-style problems (async. vs. sync design).

Regards,


Article: 2163
Subject: Re: Problem using Xilinx XC4025
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Mon, 23 Oct 95 14:24:44 GMT
Links: << >>  << T >>  << A >>
Unfortunately, I think you're out of luck.

>From what I hear, the 4025 is basically a 4013, with lots
more cells, and not lots more routing.  So, you're probably
going to fill it up pretty quick.

I haven't used the latest Xilinx tools; they're supposed to have
some sort of floorplanner.  You might try using it to force as
much of your logic to the outside edges, putting blocks that have
lots of internal routing out there.  Then, you'll have more room
in your center for interblock routing.  Of course, you're screwed
on timing.  But, at least it is more likely to fit.

This sounds like a job for ORCA or Altera (here's a great chance
for them to come to the rescue of a student - come on, jump in
there FPGA salespeople!).  I understand they both have some large
parts, and they claim to be more routable than Xilinx (though I
have no personal experience with the large parts).

Let me know if you have any other questions,


Article: 2164
Subject: Re: Comp.Arch.FPGA Reflector V1 #354
From: sharono@ukefl.demon.co.uk (Sharon Okoli)
Date: Mon, 23 Oct 1995 19:26:42 GMT
Links: << >>  << T >>  << A >>
unsubscribe
-- 
Sharon Okoli


Article: 2165
Subject: Re: FPGAs as a substitute for glue logic?
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 23 Oct 1995 21:28:01 GMT
Links: << >>  << T >>  << A >>
In article <469jtr$vgg@zipper.zip.com.au> Duraid Madina,
duraid@zip.com.au writes:
>I gather FPGAs are used as a nice way of getting around the millions (or too 
>many, at least :) of simple ICs that creep their way into designs. (hello 
>74ls08 :) However, I've found no simple way that will let me take my design, 
>with glue logic, and implement that in an FPGA such that it's the same 
>design, just with an FPGA instead of many discrete ICs.
>
>	Someone help me!
>
>Also, are there any inexpensive ways to accomplish my task? (I'm a school 
>student - aargh!)
>
Xilinx, and I expect Altera and a few of the others, have equivalent
macros so TTL designs can be converted into FPGA. However, only a subset
of TTL ICs have equivalents and the timings will be different  in
general, equivalents to registers are tricky.

My suggestion would be to use CPLDs instead. You can get hold of free
software for some devices (eg. use old Intel Pldshell for what are now
Altera Flexlogic devices, available from Altera). You can get hold of
equivalent TTL macros for these too, but I expect it would be easier to
restate the logic. You can save yourself some money by making the
download cable up yourself - look at the archives of this group to see
how.
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD,UK     URL: http://www.ap.co.umist.ac.uk/~jf


Article: 2166
Subject: Re: Programming AMD Mach Parts
From: peter.presti@oip.gatech.edu (Peter Presti)
Date: Mon, 23 Oct 1995 21:58:28 -0500
Links: << >>  << T >>  << A >>
I've been using mach445's for about a year now.  Here's some of my
experience:

A word on programming AMD MACHs with a JTAG cable:

Terminate the 4 JTAG lines to the PLD with 470ohm resistors to Vcc.  You
might want to try to run the return line (TDO) through a 470ohm on the
way back to the CPU.  As of late '94 this info was not part of the
data sheet.

Power supply:

Use capacitors liberally.  Place one 0.1mfd on each side between Vcc and
GND.

I've had sporadic results programming with the JTAG cable.  Maybe my
homebrew "programmer" (a ZIF socket for holding an Aries PGA adaptor)
is flaky.  I have had much better luck programming with the part out of
the circuit.

Good Luck,
-Pete


Article: 2167
Subject: Re: Problem using Xilinx XC4025
From: Christian Grebe <grebe>
Date: 24 Oct 1995 08:31:42 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

---------------------------------4228160711820124532718224029
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset=us-ascii

Hello Mats,

>First, the device is very hard to route. Even though it is only filled to 50%,
>ppr may fail to route it. If it can route it, it takes _hours_ to get is
>acceptable.

This is a known problem with this device. You should try to floorplan your
design with 'place instance' and 'place set' statements in the .cst constraints
file for ppr. With this statements you can place related logic - using
wildcards for instance names - in rectangular areas on the chip, which makes
things much easier for ppr.
You may consider to buy the Xilinx Floorplanner, a good tool if you want to
place parts of the design manually and good for analyzing floorplanning, but
there are restrictions though. Mail me if you want to know more about this.

Use 'realistic' timing constraints with ppr to dramatically speed up place &
route. Otherwise ppr will route forever without meeting your timing. Look at
your critical paths and try to figure out why the delay is that big. If there
are extensive routing delays, floorplanning may help.

If you have question, don't hesitate to mail me.

Regards,

---------------------------------4228160711820124532718224029
Content-Transfer-Encoding: 7bit
Content-Type: text/plain

Christian Grebe

Siemens Nixdorf Informationssysteme AG
Line of Business High-Performance Printers
ASIC's (HLD ST 35)
Siemensallee 2
85586 Poing
Germany

Phone  : +49 (8121) 72-4912
Fax    : +49 (8121) 72-3173
EMail  : grebe@sun2.zfe.siemens.de  

---------------------------------4228160711820124532718224029--


Article: 2168
Subject: Chip Express Results...So Far
From: tboydsto@su102s.ess.harris.com (Ted Boydston)
Date: 24 Oct 1995 16:07:06 GMT
Links: << >>  << T >>  << A >>
So far, I have received many requests for a summary of responses to my original
post about Chip Express.  Unfortunately, I have received no responses about Chip
Express itself.  In fact, I have recieved more informaiton about Orbit than Chip
Express (1 responses versus 0 responses).

I would be willing to cut-n-paste the responses I get and post them, BUT
I do not want to become the maintainer of a FAQ for Chip Express.  So, please email
me only about information concrening Chip Express.  That means no "me too" mailings
requesting a copy of the responses.

I will relay a copy of all the responses I get to the following newsgroups on Monday
October 30:

comp.arch.fpga
comp.cad.synthesis
comp.cad.cadence
comp.lang.vhdl

If I get no responses, I'll post a statement about that too.

Thanks :)

---
  +-------------------------------------------------------------------------+
 /                            TED L. BOYDSTON IV                             \
+ Harris Corporation, GASD * PO Box 94000 * MS 102-4823 * Melbourne, FL 32902 +
 \ Email: tboydsto@harris.com * Fax: (407) 729-2782 * Voice: (407) 729-7999  /
  +-------------------------------------------------------------------------+

======================================================================================

THE ORBIT RESPONSE I RECEIVED
-----------------------------

We have just completed an FPGA conversion with Orbit Semiconductor.  Since they 
were mentioned, I thought I'd comment briefly.  We used VHDL for design entry and 
mapped a ~2K gate design operating at 2.3 MHz to an Altera FPGA using Synopsys 
FPGA Compiler.  (Yes, I know, not lightening speed or density.)  After testing 
this design in the FPGA, we sent Orbit the following information:

1. EDIF Netlist (Synopsys Output)
2. Print-on-change style simulations from Mentor Graphics Quicksim II
3. Desired Package/Pinout
4. Package Marking

Orbit successfully converted this design into their Encore! gate array process 
with very little interaction from our engineering group.  In fact, the level of 
interaction required was so minimal it bothered us!  They completed the conversion 
and had working parts in our hands in about 8 weeks (just within the upper 
variance of their commited design schedule).  The parts performed 100% to 
specification.

After meeting with their Engineering staff in Sunnyvale last month, I learned that 
Orbit is much more successful with designs generated from a top-down, synochronous 
design methodology (as most ASICs are developed), as opposed to schematic-based 
FPGA designs which tend to be problematic.

Orbit's process technology is not the most advanced (1 micron I believe), but they 
are VERY cost-effective.  I would recommend them for small to medium size 
(up to 45K gates) designs up to moderate speeds.  They offer superior value, 
particularly in low volumes.  (We only needed around 2,000 parts, but couldn't use 
an FPGA for production due to the board layout...  we needed a drop-in 
replacement for an obsolete part.)  The nearest ASIC competitor quoted 2.5 times 
the NRE for this design and wanted a guarantee of 6K parts!  I highly recommend 
Orbit Semiconductor for FPGA conversions... they are very experienced.

Hope others find this information useful...

Nelson W. Willhite  
Nelson.Willhite@AtlantaGA.ATTGIS.COM
 


Article: 2169
Subject: Re: FPGAs as a substitute for glue logic?
From: biggs@qcktrn.com ( Tom Biggs )
Date: 25 Oct 1995 01:58:58 GMT
Links: << >>  << T >>  << A >>

In article vgg@zipper.zip.com.au, duraid@zip.com.au (Duraid Madina) writes:
> I gather FPGAs are used as a nice way of getting around the millions (or too 
> many, at least :) of simple ICs that creep their way into designs. (hello 
> 74ls08 :) However, I've found no simple way that will let me take my design, 
> with glue logic, and implement that in an FPGA such that it's the same 
> design, just with an FPGA instead of many discrete ICs.
> 
> 	Someone help me!
> 
> Also, are there any inexpensive ways to accomplish my task? (I'm a school 
> student - aargh!)
> 
> 		...Duraid Madina
> 

Many FPGA schematic capture libraries have descrete equivalents so that you can
rebuild your schematic with these elements. However, as a student, you
should take the long term view. You really ought to stop thinking in
terms of discrete ICs, which are quickly becoming obsolete, and think
in terms of generic ANDs/ORs, Flip flops, counters, etc. Another way to
design is with equations and state machines (Abel, Verilog, VHDL). 

So use a more employable design methodology, throw your schematic away ;) 
and design with an FPGA from the start. Put that 74ls08 on your shelf next
to the vacuum tubes.

   -tom


   -tom





Article: 2170
Subject: Re: PLD in small package ?? anyone
From: manoj_chaubal@psilongbeach.com (Manoj Chaubal)
Date: Wed, 25 Oct 1995 13:40:02 GMT
Links: << >>  << T >>  << A >>
Vincent.Himpe@ping.be (Vincent Himpe) wrote:

>Hi,

>I need a pld that comes in an 8 pin package and something like 16 ff's
>and a bunch of colmbinatorial stuff. Pretty much like an iPLD610 or
>610 from altera but squeezed into an 8 pin package.
>Anyone ? PLLC28 is still too large for me.
>I only have 5 I/O's  the rest is buried.

>Are there any FPGA / EPLD / whatever  with low pincounts and lot's of
>gates ?.
>My deisgns mostly use serial communication and don't need lots of I/O.
>So it's pretty silly to put an 132 pin PQFP on your board when you are
>only using 12 pins.

>Regards
>vincent

I have worked with lots of PLDs and I haven't come across a PLD like
that.  The smallest PLD I have seen so far is 20pin PLCC, 16v8.  But
then, I have only used PLDs from major manufactures.
Manoj Chaubal



Article: 2171
Subject: Help needed: TNM attributes (Xilinx)
From: Peter Wurbs <pwu@maz-hh.de>
Date: 25 Oct 1995 21:22:49 GMT
Links: << >>  << T >>  << A >>

Hi Xilinx-Users,

how can I add TNM attributes to the design without
changing the XNF-File before Place&Route with PPR.
I use the SYNOPSYS-Design-Flow, therefore I can't
add TNM attributes during design entry or within
SYNOPSYS.
Any ideas or recommendations welcome.

Thanks.


--------------------------------------------------
Peter Wurbs
MAZ Hamburg GmbH
pwu@maz-hh.de 
--------------------------------------------------



Article: 2172
Subject: Re: Xilinx Configuration Memory Hacking
From: daveb@iinet.net.au (David R. Brooks)
Date: Wed, 25 Oct 1995 22:13:29 GMT
Links: << >>  << T >>  << A >>
fmicale@motown.ge.com (Francesco Micale, X4438) wrote:

>You can avoid an invalid bitstream causing any havoc by specifying CRC inclusion
>in the bitstream. That will cause the device to abort during programming, and 
>stay in its quiescent mode. At least it does in XC40xx series devices.
>-fm

  I'm not sure this helps in this case - we are looking at hacking the
bitstream to identify the function of various bits. Unless a good CRC
is computed for each hacked bitstream (or CRC is disabled), nothing
can work, and we can learn nothing.
  For those with access to it, a safer method might be to use the XACT
configuration editor. Say, set up a basic Boolean function in a known
CLB location, with all its wiring hand routed. Build a bitstream. Now
change one item (location of a route, or the Boolean function itself),
and look for the changes in the bitstream. Very tedious, I admit, but
hopefully all the CLB sites program identically, so you would only
need to attack a limited subset.


David R. Brooks <daveb@iinet.net.au>    Tel/fax. +61 9 434 4280



Article: 2173
Subject: US-CO-Boulder Digital Designer (EE) Job Opening
From: "Rainer M. Malzbender" <rainer@displaytech.com>
Date: 25 Oct 1995 23:43:13 GMT
Links: << >>  << T >>  << A >>

We currently have an opening for an electrical engineer with several years
of experience in digital logic. The ideal candidate would be familiar with
digital video, FPGA development, new DRAM architectures like SDRAM and
Rambus, and have an appreciation for the problems associated with high speed
design. We value solid skills, innovation, the ability to learn quickly, and
flexibility more than we do sheepskins, but this position will require the
equivalent of at least a BSEE and several years of solid experience. Good
analog skills would be a definite plus.

Displaytech manufactures a variety of electro-optic devices based on high
speed ferroelectric liquid crystals, including the next generation of high
resolution full color miniature displays for head mounted applications,
portable computing, and communications.  The person hired will work on
display controller electronics based largely on FPGAs, CPLDs, and off the
shelf devices, but should be prepared for a migration to custom silicon.

Displaytech is located in Boulder, CO and is privately held. Although we
have been in existence for more than ten years, we are currently in a period
of growth more typical of a startup.

Please send resumes to resumes@displaytech.com (preferred) or to

     Human Resources
     Displaytech, Inc.
     2200 Central Ave.
     Boulder, CO 80301

No phone calls please; I will try to answer email unless I get flooded.

--
Rainer M. Malzbender                             Senior Research Physicist
rainer@displaytech.com                                   Displaytech, Inc.
303.449.8933                           2200 Central Ave. Boulder, CO 80301




Article: 2174
Subject: Re: PLD in small package ?? anyone
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 26 Oct 1995 14:47:13 GMT
Links: << >>  << T >>  << A >>
Vincent.Himpe@ping.be (Vincent Himpe) wrote:
>I need a pld that comes in an 8 pin package and something like 16 ff's
>and a bunch of colmbinatorial stuff. Pretty much like an iPLD610 or
>610 from altera but squeezed into an 8 pin package.
>Anyone ? PLLC28 is still too large for me.
>I only have 5 I/O's  the rest is buried.

manoj_chaubal@psilongbeach.com (Manoj Chaubal):
>The smallest PLD I have seen so far is 20pin PLCC, 16v8.  But
>then, I have only used PLDs from major manufactures.

So what *is* the smallest PLD available today?  I have seen a number 
of fine pitch packages that were tiny, but didn't pay that much attention.

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's






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