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Messages from 4275

Article: 4275
Subject: Atmel Serial Configuration EEPROM - AT17C128
From: Andrew Siska <asiska@interaccess.com>
Date: Tue, 08 Oct 1996 21:58:04 -0700
Links: << >>  << T >>  << A >>
Hello,

I just picked up a tube of Atmel AT17C128 for use with a Xilinx XC5204
design - I was getting tired of throwing away ($) using the Xilinx OTP
configuration prom.

Programming the Atmel part with a known good design and plugging it into
known good hardware causes the system to do nothing.  However, if I
probe around the Atmel part with a scope, the system fires up.  

Xilinx claims that the Atmel EEPROMS have a power up problem, Atmel
claims that there is nothing wrong with the parts (I have verified the
lot numbers with those that Atmel knows there is a problem).

Has anyone experienced similar problems?  Whats the cure?

Thanks,

Andy

Embedded Systems Electronics, Inc.
(630) 960-0052
Fax: (630) 960-0046
Article: 4276
Subject: Re: Reversible LFSR?
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 9 Oct 1996 05:37:31 GMT
Links: << >>  << T >>  << A >>
This is not too hard. The bit that was just shifted in was the result of
the previous state, including the last bit that you have just shifted 
out and thrown away. It must include the last bit since not including it 
would be an LFSR of a shorter length. So all the data you need is at the
bit positions 1 after the tap positions of the forward polynomial. 

If this is the LFSR

   Q0   Q1   Q2   Q3   Q4   Q5   Q6   Q7

And the shifter shifts from Qn to Qn+1, the what you just lost was the old
Q7, and the new value is in Q0. Lets assume the LFSR runs with the following
feedback term:

Q0 <=  .not. ( Q2 .xor. Q7)

then old Q2 is in Q3 now. So....

Old Q7 = .not. ( Q3 .xor. Q0 )   (hmmmm.. I wonder if there is some symetry)

Anyway, with the second eqn, and a mux on the input to each FF to allow
you to reverse direction, you could reverse the LFSR.

I leave other LFSR examples as an exercise for the reader.

Philip Freidin


In article <325A7D29.1335@univision.com> "John L. Smith" <jsmith@univision.com> writes:
>LFSRs make good cheap address generators for FIFOs, but how about
>an address generator for a LIFO? Has anyone ever looked at an LFSR
>that can run in both directions? One bit is lost from the end of the
>shift register each clock, but perhaps there is an interesting
>combination of xor's that can produce the neccessary bits for shifting
>reversibly in either direction? Just posing the question...
>
>-- 
>John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
>Univision Technologies, Inc. | those who are once-and-a-half witted
>6 Fortune Dr.                | with the half-witted, because we
>Billerica, MA 01821-3917     | appreciate only a third part of their wit.
>jsmith@univision.com         | - Henry David Thoreau


Article: 4277
Subject: 16x16 multiplier needer (Altera or VHDL)
From: Matthew J Myers <mattt+@CMU.EDU>
Date: Wed, 9 Oct 1996 01:47:37 -0400
Links: << >>  << T >>  << A >>
Can anybody point me to a 16x16 multiplier design made for an Altera
FPGA (preferably FLEX 8000 series), either AHDL, VHDL, or graphical
format?

Thanks,

---
   _____          __    __    __   
  /     \ _____ _/  |__/  |__/  |_ 
 /  \ /  \\__  \\   __\   __\   __\
/    Y    \/ __ \|  |  |  |  |  |  
\____|__  (____  /__|  |__|  |__|  
        \/     \/                  

Article: 4278
Subject: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
From: pak@cse.ucsc.edu (Pak K. Chan)
Date: 9 Oct 1996 05:51:01 GMT
Links: << >>  << T >>  << A >>
mis-spelt! <scannner@dial.pipex.com> wrote:
>
>I want to plot a lot of files, and would like to run the plotter.exe
>program (part of the Xilinx/Viewlogic v.4.1 DOS suite) on its own.
>
I couldn't find any doc on metafiles. This is what I did:

The trick is to ask workview to keep a log (record) of what you are doing
first, like open a single schematic, using the plot function, generate a
postscript, close the schematic.

You save this log file (a very simple text file)
and use it as a template to create
a much bigger log file (call this "bigfile")
with all the names of schematic that you need to plot.

You can then evoke workview and ask it to execute the bigfile. 

Article: 4279
Subject: Re: Reversible LFSR?
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 9 Oct 1996 05:51:57 GMT
Links: << >>  << T >>  << A >>
In article <325ABF85.2A1A@wlv.hp.com> "Jorge P. Seidel" <jseidel@wlv.hp.com> writes:

Jorge posted a nice long article on LFSR's , which I won't fully quote, 
but...

>/*******************************************************************/
>Courtesy of Chuck Erickson at Xilinx:
>
>It is always possible to have an up/down LFSR counter:
>
>n=16
>
> +--- XOR_R=2,3,5,16                              XOR_L=1,3,4,16 --+
> |     +-----------------------------------------------------+     |
> |     |                                                     |     |
> +---->|      16-bit Right/Left Shift Register               |<----+
>       |                                                     |
>       +-----------------------------------------------------+
>            |  |
>Clock ------+  |
>               |
>R/L -----------+

So here the FFs are called Q1 thru Q16 and since XOR_R has '16' in it,
this diagram has Q1 at the left, and Q16 at the right, and XOR_R is used
for a right shift from Qn to Qn+1, which is the same layout as in my 
previous response.

If you look at my previous mail, the XOR_L should be 1,3,4, and 6 , 
rather than the shown 1,3,4,16. I would be delighted for someone else
to confirm this correction.

>
>Determining the taps for the reverse shift is not trivial, indeed, 

Clearly, I disagree.

>determining taps for LFSR's is always difficult, but for your 

Only difficult if you are silly enough to write the program to calculate 
the tap positions in Prolog    :-)    

>application, since the length of the LFSR register will be fairly small,
>it should be doable.

Philip



Article: 4280
Subject: Re: Reversible LFSR?
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Wed, 09 Oct 1996 07:48:01 +0100
Links: << >>  << T >>  << A >>
Jorge P. Seidel wrote:
> 
> John L. Smith wrote:

> may have obtained the proof from another source.

Indeed, this is not hard to see: 
LFSR are the generated sequence in the multplicative group
of a finite field. The inverse of a generator is a 
generator, too. 
Furthermore it is not hard to find: just an gcd computation.
Just my 2%
Andreas
Article: 4281
Subject: Re: Atmel Serial Configuration EEPROM - AT17C128
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Wed, 09 Oct 1996 08:04:06 GMT
Links: << >>  << T >>  << A >>
Andrew Siska <asiska@interaccess.com> wrote:

>Hello,

>I just picked up a tube of Atmel AT17C128 for use with a Xilinx XC5204
>design - I was getting tired of throwing away ($) using the Xilinx OTP
>configuration prom.

>Programming the Atmel part with a known good design and plugging it into
>known good hardware causes the system to do nothing.  However, if I
>probe around the Atmel part with a scope, the system fires up.  

>Xilinx claims that the Atmel EEPROMS have a power up problem, Atmel
>claims that there is nothing wrong with the parts (I have verified the
>lot numbers with those that Atmel knows there is a problem).

>Has anyone experienced similar problems?  Whats the cure?

>Thanks,

>Andy

>Embedded Systems Electronics, Inc.
>(630) 960-0052
>Fax: (630) 960-0046

The Atmel parts have programmable reset sense, have you set this to
match the Xilinx OTP?

TTFN

Julian


-- 
---------------------------------------------------------------------
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
Hardware development eng.                          August Systems Ltd
---------------------------------------------------------------------
                                          


Article: 4282
Subject: Re: 16x16 multiplier needer (Altera or VHDL)
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Wed, 09 Oct 1996 08:12:06 GMT
Links: << >>  << T >>  << A >>
Matthew J Myers <mattt+@CMU.EDU> wrote:

>Can anybody point me to a 16x16 multiplier design made for an Altera
>FPGA (preferably FLEX 8000 series), either AHDL, VHDL, or graphical
>format?

>Thanks,

>---
>   _____          __    __    __   
>  /     \ _____ _/  |__/  |__/  |_ 
> /  \ /  \\__  \\   __\   __\   __\
>/    Y    \/ __ \|  |  |  |  |  |  
>\____|__  (____  /__|  |__|  |__|  
>        \/     \/                  


Use lpm_mult.


-- 
---------------------------------------------------------------------
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
Hardware development eng.                          August Systems Ltd
---------------------------------------------------------------------
                                          


Article: 4283
Subject: Xilinx Startup symbol instantiation in VHDL using Viewlogic ?
From: Rynier van der Watt <arvdwatt@csir.co.za>
Date: Wed, 09 Oct 1996 12:39:14 +0200
Links: << >>  << T >>  << A >>
Hi

Does anybody know how to instantiate the Xilinx Startup symbol in VHDL 
for Viewlogic's Viewsynthesis?

I am currently using the Workview Office for Windows95 tools and a 
XC4025E device.

Thank you very much in advance.

Rynier van der Watt
CSIR South Africa

Email: arvdwatt@csir.co.za
Article: 4284
Subject: ORCA 2C10A - RAM placement advice
From: Richard Jozefowski <richard@milliped.demon.co.uk>
Date: Wed, 09 Oct 1996 11:00:33 +0000 (GMT)
Links: << >>  << T >>  << A >>
I've been evaluating a pre-production version of Foundry 9.0 and have
designed a FIFO with asynchronous I/O using the dual port RAMs (this is a
great feature of the A series and potentially makes asynchronous FIFOs so
easy to design).  My RAM block is 128x10 (40 PFUs).  I'm having trouble
meeting a read access frequency of 27MHz (at least with -2 parts), the best
PAR so far being about 22MHz.  About 70% of the access time is spent in
routing the 4 low order read address bits to the 40 PFUs.  Being close to
the required rate I'd like to put a bit more effort into getting there
without moving to the more expensive -3 or -4 parts.

Any ideas on how I can improve the placement/routing of the four address
lines?  Any advice on hand placement?  Of course, I've already made the nets
critical.  Is there the equivalent of the Xilinx longlines?  So far the
2C10A is only 50% utilised - there's a lot more junk in there than just the
FIFO and there's yet more to go in!

-- 
Richard Jozefowski

Article: 4285
Subject: Re: 16x16 multiplier needer (Altera or VHDL)
From: mav@asd470.dseg.ti.com (Michael Vincze)
Date: 9 Oct 1996 14:19:45 GMT
Links: << >>  << T >>  << A >>
In article omKnlt200YUp0QWr80@andrew.cmu.edu, Matthew J Myers <mattt+@CMU.EDU> () writes:
>Can anybody point me to a 16x16 multiplier design made for an Altera
>FPGA (preferably FLEX 8000 series), either AHDL, VHDL, or graphical
>format?
>
>Thanks,
>
>---

OK.  In VHDL:

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;

  entity mult is
    port(a, b: in  std_logic_vector(3 downto 0);
         c   : out std_logic_vector(7 downto 0));
  end;

  architecture rtl of mult is
  begin
  c <= a * b;
  end;

Best regards,
Michael Vincze


Article: 4286
Subject: Re: Anyone using Altera MaxPlus VHDL ???
From: tres@tc.fluke.COM (Mike Treseler)
Date: Wed, 9 Oct 1996 19:30:41 GMT
Links: << >>  << T >>  << A >>
sja@world.std.com (Stuart J Adams) writes:

>I am considering getting Altera's MaxPlus VHDL synthesis
>add-on. Was wondering if anyone is using this and how it
>compares to other synthesis tools such as Synplicity,
>Synopsys, or Exemplar ???


>Thanks,
>  Stuart Adams
>  sja@world.std.com

>-- 

>Stuart Adams
>Chief Engineer
>Bright Star Engineering

We use Exemplar, but I have spent a day on MaxPlus VHDL.
Maxplus is very easy to use and has well integrated tools.
The downside is Altera-only synthesis and no support of VHDL
testbenches.

----------------------------------------------------------------------
     tres@tc.fluke.com                       Mike Treseler
                                             Fluke Networks Division
voice:  (206) 356-5409                       Fluke Corporation
fax:    (206) 356-5043                       P.O. Box 9090
                                             Everett, WA  98206-9090
----------------------------------------------------------------------
Article: 4287
Subject: Re: Atmel Serial Configuration EEPROM - AT17C128
From: Andrew Siska <asiska@interaccess.com>
Date: Wed, 09 Oct 1996 18:06:47 -0700
Links: << >>  << T >>  << A >>
Julian Cox wrote:
> 
> Andrew Siska <asiska@interaccess.com> wrote:
> 
> >Hello,
> 
> >I just picked up a tube of Atmel AT17C128 for use with a Xilinx XC5204
> >design - I was getting tired of throwing away ($) using the Xilinx OTP
> >configuration prom.
> 
> >Programming the Atmel part with a known good design and plugging it into
> >known good hardware causes the system to do nothing.  However, if I
> >probe around the Atmel part with a scope, the system fires up.
> 
> >Xilinx claims that the Atmel EEPROMS have a power up problem, Atmel
> >claims that there is nothing wrong with the parts (I have verified the
> >lot numbers with those that Atmel knows there is a problem).
> 
> >Has anyone experienced similar problems?  Whats the cure?
> 
> >Thanks,
> 
> >Andy
> 
> >Embedded Systems Electronics, Inc.
> >(630) 960-0052
> >Fax: (630) 960-0046
> 
> The Atmel parts have programmable reset sense, have you set this to
> match the Xilinx OTP?
> 
> TTFN
> 
> Julian
> 
> --
> ---------------------------------------------------------------------
> CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
> Hardware development eng.                          August Systems Ltd
> ---------------------------------------------------------------------
> 
Julian,

Thanks for the reply, however the use of programmable reset polarity is
made quite obvious in Atmel's data sheet.

Andy
Article: 4288
Subject: Re: Xilinx Startup symbol instantiation in VHDL using Viewlogic ?
From: "H.Spaargaren" <hspaarga@best.ms.philips.com>
Date: Thu, 10 Oct 1996 08:04:17 +0200
Links: << >>  << T >>  << A >>
Rynier van der Watt wrote:
> 
> Hi
> 
> Does anybody know how to instantiate the Xilinx Startup symbol in VHDL
> for Viewlogic's Viewsynthesis?
> 
> I am currently using the Workview Office for Windows95 tools and a
> XC4025E device.
> 
> Thank you very much in advance.
> 
> Rynier van der Watt
> CSIR South Africa
> 
> Email: arvdwatt@csir.co.za

-- 

I give here an example how I implemented it for Examplar Galileo.
It synthesizes Global Set Reset correctly, but there is still a
problem with Global Three State. Maybe Viewsynthesis does it better.

You have to instantiate a STARTUP component in your top level entity,
with inputs gsr and gts. Then connect the reset and output enable
input signals to STARTUP by PORT MAP.


-------------------------------------------------

---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool.
--
-- EASE/VHDL Version 2.4 (Revision -8).
-- Time stamp  : Thu Oct 10 07:47:40 1996.
--
-- Designed by : .
-- Company     : .
-- Design info : .
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Entity declaration of 'core'.
---------------------------------------------------------------------------

LIBRARY ieee, synergy ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_1164.ALL ;
USE synergy.signed_arith.ALL ;
USE work.ALL ;

ENTITY core IS
  PORT(
    clk    : IN     std_ulogic ;
    en_out : IN     std_ulogic ;
    reset  : IN     std_ulogic ;
    a      : IN     std_ulogic ;
    q1     : OUT    std_ulogic ) ;
END core ;

---------------------------------------------------------------------------
-- Architecture 'a0' of 'core'.
---------------------------------------------------------------------------


ARCHITECTURE a0 OF core IS

signal q1_a:  std_ulogic;

BEGIN

process(reset,clk,a)
begin
   if reset = '1' then
      q1_a <= '0';
   elsif clk = '1' and clk'event then
      q1_a <= a;
   end if;
end process;

process(q1_a,en_out)
begin
   if en_out = '1' then
      q1 <= q1_a;
   else
      q1 <= 'Z';
   end if;
end process;

END a0 ;

---------------------------------------------------------------------------
-- Entity declaration of 'xxx'.
---------------------------------------------------------------------------


LIBRARY ieee, synergy ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_1164.ALL ;
USE synergy.signed_arith.ALL ;
USE work.ALL ;

ENTITY xxx IS
  PORT(
    a      : IN     std_ulogic ;
    reset  : IN     std_ulogic ;
    en_out : IN     std_ulogic ;
    q1     : OUT    std_ulogic ;
    clk    : IN     std_ulogic ) ;
END xxx ;

---------------------------------------------------------------------------
-- Architecture 'a0' of 'xxx'.
---------------------------------------------------------------------------

ARCHITECTURE a0 OF xxx IS

 COMPONENT core
  PORT(
    clk    : IN     std_ulogic ;
    en_out : IN     std_ulogic ;
    reset  : IN     std_ulogic ;
    a      : IN     std_ulogic ;
    q1     : OUT    std_ulogic ) ;
 END COMPONENT ;
 COMPONENT startup                --  <--------------------------
  PORT(
    gsr : IN     std_ulogic ;
    gts : IN     std_ulogic ) ;
 END COMPONENT ;
 SIGNAL clock : std_ulogic ;
 SIGNAL rst   : std_ulogic ;
 SIGNAL ain   : std_ulogic ;
 SIGNAL ena   : std_ulogic ;
 
BEGIN

 clock <= clk ;
 rst <= reset ;
 ain <= a ;
 ena <= en_out ;

 u0: core
    PORT MAP(
      clk => clock,
      en_out => ena,
      reset => rst,
      a => ain,
      q1 => q1 ) ;

 u4: startup                      -- <----------------------
    PORT MAP(
      gsr => rst,
      gts => ena ) ;

END a0 ; -- of xxx



-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Hans Spaargaren			(for: Philips Medical Systems Nederland B.V.)
Origin
Engineering Services, CAD/CAM-E
Building QG-037                       Internet:
hspaarga@best.ms.philips.com
P.O. Box 10.000                       Voice:		+31 40 2763018
5680 DA  Best    		      Fax:		+31 40 2765641
the Netherlands				
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Article: 4289
Subject: FPGA Web Links
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 10 Oct 1996 14:44:50 GMT
Links: << >>  << T >>  << A >>
It has been a while since I visited this FPGA links page:

  http://www.mrc.uidahol.edu/fpga/fpga.html

Congrats to whomever maintains it.  It is greatly improved!

It contains links to FPGA related conferences, tools, education 
groups & projects, vendors, comp.arch.fpga archives, tutorials, 
consultants, etc.  Check it out.

-- 
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's


Article: 4290
Subject: help: max+ edif input problems
From: Sebastian H Ziesler <sz29+@andrew.cmu.edu>
Date: Thu, 10 Oct 1996 14:32:04 -0400
Links: << >>  << T >>  << A >>
Hi.
I have been trying to input an edif file written by Synplicity's
synplify into Altera's Max+plusII.  When I try to compile the design,
Max+II first reads the synplcty.lmf mapping file but then gets an error
when it reads the edif file.

anyways heres the spot in the edif file where I get a parsing syntax error

  (library (rename WORK "work")
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell (rename ALT "alt") (cellType GENERIC)
       (view (rename VERILOG "verilog") (viewType NETLIST)
         (interface
error --->  (port (array (rename addrc "addrC[10:0]") 11) (direction OUTPUT))
            (port (array (rename mac "MAC[1:0]") 2)(direction OUTPUT))

We then tried to pull the (array (rename ....)) stuff out side of the
(port ...), but that just caused major errors later on.

The version of Max+II is 5.4 and the synplify version is 2.6
Anyone know whats happening?  Do I need a newer version of Max+II or is
the problem with synplify? Is there some sort of workaround to get it to
work?

Any help would be great.
Thanks,
~~seb

Article: 4291
Subject: Re: ORCA 2C10A - RAM placement advice
From: daved@wmi.com (David Dea)
Date: Thu, 10 Oct 1996 12:21:10
Links: << >>  << T >>  << A >>
In article <ant0911330b02QYK@milliped.demon.co.uk> Richard Jozefowski <richard@milliped.demon.co.uk> writes:

>I've been evaluating a pre-production version of Foundry 9.0 and have
>designed a FIFO with asynchronous I/O using the dual port RAMs (this is a
>great feature of the A series and potentially makes asynchronous FIFOs so
>easy to design).  My RAM block is 128x10 (40 PFUs).  I'm having trouble
>meeting a read access frequency of 27MHz (at least with -2 parts), the best
>PAR so far being about 22MHz.  About 70% of the access time is spent in
>routing the 4 low order read address bits to the 40 PFUs.  Being close to
>the required rate I'd like to put a bit more effort into getting there
>without moving to the more expensive -3 or -4 parts.

>Any ideas on how I can improve the placement/routing of the four address
>lines?  Any advice on hand placement?  Of course, I've already made the nets
>critical.  Is there the equivalent of the Xilinx longlines?  So far the
>2C10A is only 50% utilised - there's a lot more junk in there than just the
>FIFO and there's yet more to go in!

>-- 
>Richard Jozefowski

I've found that net criticality is not very effective.  I would try a MAXDELAY 
preference on the address nets instead.  Duplicating the source logic to 
decrease the net loading may also help, but eats up more PLC's.

There are longlines, called xL R-Nodes, but only 4 per row/column, 1 of which 
may be used for your clock tree.  The USE LONGLINE preference tells par
to try to use them.  

If you do hand placement, keep all the RAM in one quadrant of the chip, so that
par can use the xH R-Nodes (4 per row/column) which run half the array.

This is all based on non-A experience.  I haven't done any 2CxxA designs yet.

Also, it is very possible that the -3  may end up being the slowest speed bin 
for the A parts, so in the long term the -2 & -3 may be almost the same 
price.

Good luck,

Dave Dea


Article: 4292
Subject: Re: FPGA for Reed-Solomon Codec
From: "X0033$" <"X0033$"@mailgw.sanders.lockheed.com>
Date: Thu, 10 Oct 1996 13:53:50 -0700
Links: << >>  << T >>  << A >>
Hui Zhang wrote:
> 
> Hi!
> 
> Has anyone done any FPGA design for Reed-Solomon Codec (which is for
> error correction in data communication)? I would like to do some
> perfomance/cost comparison between FPGA, Custom IC, and processors,
> etc..
> 
> Any information will be appreciated.
> 
> Thomas H. Zhang
> email: hui@eecs.berkeley.edu

Hello,
	I have designed a Reed-Solomon Decoder for a space tape recorder 
that was implimented with FPGA's.  Since we could only use radiation 
hardened FPGA's, the decoder was placed into 3 Actel 1280's, 1 2k RAM, 
and 1 2k ROM.  I'm sure it would fit into a single chip Altera or Xilinx 
which contains RAM. The design is 2 years old and has been space 
qualified.  The Reed-Solomon encoder was on another board and easily goes 
into a Actel 1020.  
	I have also designed many other Reed-Solomon encoders all 
targeted for FPGA's but of differenct number of checkbytes.

				Joe Keith
				(603) 885-5949
				
x0033$_AT_NCALAN1@MAILGW.SANDERS.LOCKHEED.COM
Article: 4293
Subject: JOB: US-IN. VHDL/ASIC Design. HW/SW Integration debug. FPGAs. - ddiekhof@notes.techni-source.com
From: ddiekhof@notes.techni-source.com (Dan Diekhoff)
Date: Fri, 11 Oct 1996 00:40:45 GMT
Links: << >>  << T >>  << A >>
Technisource has an immediate need for an Electrical Engineer in Northern 
Indiana.  Position is contract in nature and carries a duration of at least 
18 months+.  Competitive rates, 401k eligibility, and insurance (salaried 
individuals) are provided. Interviews are currently taking place.

DESIRED SKILLS: 
*VHDL design
*HW/SW Integration debug
*System Test evaluation
*Specs, procedures, documentation
*Writing code for FPGAs
*Sun work station, PC, logic analyzer
*BSEE

PLEASE RESPOND ASAP TO:

Dan Diekhoff
Technisource
8465 Keystone Crossing
Suite 270
Indianapolis, Indiana  46240
800-330-5150
(Fax)317-466-0162
ddiekhof@notes.techni-source.com

OTHER OPPORTUNITIES AVAILABLE NATIONWIDE!!!

Article: 4294
Subject: Make Money
From: e106196@orca.cc.metu.edu.tr (arif tumer)
Date: 11 Oct 1996 08:02:57 GMT
Links: << >>  << T >>  << A >>

THIS REALLY DOES WORK!!!!
It only cost me the postage and $5.
READ ON.

Hello! I've got some awesome news that I think you need to take
two minutes to read if you have ever thought "How could I make
some serious cash in a hurry???" , or been in serious debt,  ready
to do almost anything to get the money needed to pay off those
bill collectors. So grab a snack, a warm cup of coffee, or a glass
of your favorite beverage, get comfortable and listen to this
interesting, exciting find!
   Let me start by saying that I FINALLY FOUND IT! That's right!
I found it! And I HATE GET RICH QUICK SCHEMES!! I hate those
schemes like multi-level marketing, mail-order schemes, envelope
stuffing scams, 900 number scams... the list goes on forever. I
have tried every darn get rich quick scheme out there over the
past 12 years. I somehow got on mailing lists for people looking
to make money (more like 'desperate stupid people who will try
anything for money!').  Well,  when I was a teenager,  these
claims to 'get me rich quick' sounded irresistible! I would shell
out $14.95 here, $29.95 there, $24.95 here, and another $49.95
there.  I had maxed out my new Circuit City Card AND my Visa...I
was desperate for money!!  So, I gave them all a chance but
failed at every one of them! Maybe they worked for some people,
but not for me.  Eventually, I just tossed that JUNK MAIL in the
trash when I got the mail.  I recognized it right away.  I can
smell a money scam from a mile away these days,  SO I THOUGHT....
I thought I could sniff out a scam easily.  WAS I WRONG!!
......I LOVE THE INTERNET!!!

   I was scanning thru a NEWSGROUP and saw an article stating to
GET CASH FAST!!  I thought..."Here on the Internet??  Well, I'll
just have to see what schemes could possibly be on the internet."
The article described a way to MAIL A ONE DOLLAR BILL TO ONLY
FIVE PEOPLE AND MAKE $50, 0000 IN CASH WITHIN 4 WEEKS!  Well,
the more I thought about it, the more I became very curious. Why?
Because of the way it worked AND BECAUSE IT WOULD ONLY COST ME
FIVE DOLLARS (AND FIVE STAMPS), THAT'S ALL I EVER PAY....EVER!!

   Ok, so the $50,000 in cash was maybe an tough amount to reach,
but it was possible.  I knew that I could at least get a return
of $1,000 or so.  So I did it!! As per the instructions in the
article, I mailed out ('snail mail'for you e-mail fanatics) a
single dollar bill to each of the five people on the list that
was contained in the article.  I included a small note, with the
dollar, that stated "Please Add Me To Your List."  I then removed
the first position name of the five names listed and moved
everyone up one position, and I put my name in position five of
the list.  This is how the money starts rolling in!  I then took
this revised article now with my name on the list and REPOSTED IT
ON AS MANY NEWSGROUPS AND LOCAL BULLETIN BOARD
MESSAGE AREAS THAT I KNEW.  I then waited to watch the money
come in...prepared to maybe receive about $1000 to $1500 in cash or
so....
But what a welcome surprise when those envelopes kept coming in!!!  I
knew what they were as soon as I saw the return addresses from people
all over the world-Most from the U.S., but some from Canada, even
some from Australia!  I tell you, THAT WAS EXCITING!!  So how
much did I get in total return?  $1000? $5000? Not even!!! I
received a total of $23,343!!!  I couldn't believe it!!

   I now have a brand new black Acura Integra to speak for, due
to this!! Now after almost 8 months, I am ready to do it again!!!
So maybe it was possible to get $50,000 in cash, I don't know,
but  IT COMPLETELY DEPENDS ON YOU, THE INDIVIDUAL!  You
must follow through and repost this article everywhere you can think
of!  The more postings you achieve will determine how much cash
will arrive in your very own mailbox!!  It's just too easy to
pass up!!!

   Let's review the reasons why you should do this:  The only
cost factors are for the five stamps, the 5 envelopes and the 5
one dollar bills that you send out to the listed names by snail
mail (US Postal Service Mail).  Then just simply repost the
article (WITH YOUR NAME ADDED) to all the newsgroups and local
BBS's you can.  Then sit back and, (ironically), enjoy walking
(you can run if you like! :o  ) down your driveway to your
mailbox and scoop up your rewards!!  We all have five dollars to
put into such an easy effortless investment with SPECTACULAR
REALISTIC RETURNS OF $15,000 to $25,000 in about 3-5 weeks!  So
HOLD OFF ON THOSE LOTTERY NUMBERS FOR TODAY,EAT AT
HOME TONIGHT INSTEAD OF TAKEOUT FROM McDONALDS AND
INVEST FIVE  DOLLARS IN THIS AMAZING MONEY MAKING SYSTEM
NOW!!! YOU CAN'T LOSE!!

   So how do you do it exactly, you ask?  I have carefully
provided the mostdetailed, yet straightforward instructions on
how to easily get this underway and get your cash on its way.
SO, ARE YOU READY TO MAKE SOME CASH!!!?? HERE WE GO!!!

*** THE LIST OF NAMES IS AT THE END OF THIS ARTICLE. ***

OK,  Read this carefully.  Get a printout of this information,
if you like, so you can easily refer to it as often as needed.

INSTRUCTIONS:

1.  Take a sheet of paper and write on it the following:
"Please add my name to your list".  This creates a service out
of this money making system and thus making it completely legal.
You are not just randomly sending a dollar to someone, you are
paying one dollar for a legitimate service.  Make sure  you
include your name and address.  I assure you that,  again,  this
is completely legal!  For a neat little twist, also write what
slot their name was in: "You were in slot 3",  Just to add a
little fun!  This is all about having fun and making money at
the same time!

2.  Now fold this sheet of paper around a dollar bill ,(no
checks or money orders), and put them into an envelope and send
it on its way to the five people listed.  The folding of the
paper around the bill will insure its arrival to its recipient.
THIS STEP IS IMPORTANT!!

3.  Now listen carefully, here's where you get YOUR MONEY COMING
TO YOUR MAILBOX.   Look at the list of five people;  remove the
first name from position one and move everyone on the list up
slot one on the list.  Position 2 name will now move to the
position 1 slot ,  position 3 will now become position 2, 4 will
be be 3, 5 wil be 4.  Now put your name, address, zipcode AND
COUNTRY in position 5, the bottom position on the list.

4.  Now upload this updated file to as many newsgroups and local
bulletin boards' message areas & file section as possible.  Give
a catchy description of the file so it gets noticed!!  Such as:
"NEED FAST CASH?, HERE IT IS!" or "NEED CASH TO PAY OFF
YOUR DEBTS??",  etc.  And the more uploads, the more money you
will make, and of course, the more money the others on the list will
make too.  LET'S ALL TAKE CARE OF EACH OTHER BY BEING
HONEST AND BY PUTTING FORTH 120 PERCENT INTO THIS
 PROFITABLE & AMAZING SYSTEM!!! You'll reap the benefits, believe
me!!! Set a goal for the number of total uploads you'll post, such as
15-20 postings or more!  Always have a goal in mind!!! If you can UUE
encode the file when uploading,  that will make it easier for the
people to
receive it and have it downloaded to their hard drive.  That way
they get a copy of the article right on their computer without
hassles of viewing and then saving the article from the File menu.
Don't alter the file type, leave it as an MS-DOS Text file. The
best test is to be able to view this file using Microsoft's
Notepad for Windows 3.x or WordPad for Windows '95. If the margins
look right without making the screen slide left or right when at
the ends of the sentences, you're in business!

5.  If you need help uploading, simply ask the sysop of the BBS,
or "POST" a message on a newsgroup asking how to post a file,
tell them who your Internet provider is and PEOPLE WILL ALWAYS BE
GLAD TO HELP.  I would try to describe how to do it but there are
simply too many internet software packages with slightly different
yet relatively simple ways to post or upload a file.  Just ask for
help or look in the help section for 'posting'. I do know that for
GNN, you simply select 'POST' then enter a catchy description
under the subject box, choose 'ATTACH', selecting 'UUE' and NOT
'TXT', then choose 'Browse' to go look for the file. Find your
text file CASH.TXT and click on it and choose 'OK'.  Place a one
line statement in the main body section of the message post
screen. Something like "Download this to read how to get cash
arriving in your mailbox with no paybacks!" or whatever. Just make
sure it represents its true feasibility, NOT something like...
"Get one million dollars flooding in your mailbox in two days!"
You'll never get ANY responses!

6.  And this is the step I like.  JUST SIT BACK AND ENJOY LIFE
BECAUSE CASH IS ON ITS THE WAY!!  Expect to see a little money
start to trickle in around 2 weeks, but AT ABOUT WEEKS 3 & 4, THE
MONEY STORM WILL HIT YOUR MAILBOX!! All you have to do is take it
out of the mailbox and try not to scream too loud (outside anyway)
when you realize YOU HIT THE BIG TIME AT LAST!!

7.  So go PAY OFF YOUR BILLS AND DEBTS and then get that something
special you always wanted or buy that special person in your life
(or the one you want in your life)  a gift they'll never forget.
ENJOY LIFE!

8.  Now when you get low on this money supply,  simply re-activate
this file again; Reposting it in the old places where you
originally posted and possibly some new places you now know of.
Don't ever lose this file, always keep a copy at your reach for
when you ever need cash.  THIS IS AN INCREDIBLE TOOL THAT YOU
CAN ALWAYS RE-USE TIME AND TIME AGAIN WHEN CASH IS
NEEDED!

*******************************************************************
*******************************************************************
THE NAMES LIST       THE NAMES LIST      THE NAME LIST
*******************************************************************
  HONESTY IS WHAT MAKES THIS PROGRAM SUCCESSFUL!!!
  

   1. Sam Roberts	 
      4200 East Fletcher Ave.  #227 
      Tampa, Fl.   33613-4902	 
   
   2. Greg Stein 
      8790 Davis Blvd. 
      NRH, TX  76180  
  
   3. Danny Wagner
      21755 ventura blvd ste 491
      Woodland Hills, Ca 91364

   4. G. Antonio Cortizo
      Geminis 129-6 Colonia Contry
      C.P. 64860 
      Monterrey N.L. 
      Mexico
  
    5. Arif Tumer
       Dikmen Cad. 13. Sokak
       SumerSitesi 20/27
       Dikmen / Ankara
       Turkey
 ********************************************************************

NOTE:
Try to keep a list of everyone that sends you a dollar and always keep
an eye on the local postings of this file... Just to make sure that
everyone is playing the game fairly. You know where your name should
be.....

*** AGAIN,  HONESTY IS THE BEST THING WE HAVE GOING FOR US ON THIS
PLAN.

*** By the way, if you try to deceive people by posting the messages
with your name in the list and not sending the money to the people
already included, you will not get much. I know someone who did this and 
only got about $150 (and that's after two months). Then he sent the 5
bills, people added him to their lists, and in 4-5 weeks he had over 
$10000! All the lists are re-distributed as soon as the money is received.

And you can't lose anyway! If only 6 people send you the money, you are alredy 
winning 1 buck!


Article: 4295
Subject: Next conf
From: Frederic Gruau <gruau@~gruau.cwi.nl>
Date: Fri, 11 Oct 1996 15:16:23 GMT
Links: << >>  << T >>  << A >>
Thank you for emailing me  the list of the next CFP of FPGA conf.
Frederic.
Article: 4296
Subject: Re: FPGA Web Links
From: hutch@ee.byu.edu (Brad Hutchings)
Date: 11 Oct 1996 15:20:21 GMT
Links: << >>  << T >>  << A >>
>>>>> "John" == John L Smith <jsmith@univision.com> writes:
In article <325E77BB.42B@univision.com> "John L. Smith" <jsmith@univision.com> writes:


    John> William J. Wolf wrote:
    >>  It has been a while since I visited this FPGA links page:
    >> 
    >> http://www.mrc.uidahol.edu/fpga/fpga.html
    >> 
    >> It contains links to FPGA related conferences, tools, education
    >> groups & projects, vendors, comp.arch.fpga archives, tutorials,
                                                            ^^^^^^^^^
    >> consultants, etc.  Check it out.

For those interested specifically in tutorials for configurable
computing platforms, you may want to look into
http://splish.ee.byu.edu and follow the tutorials link. We also still
maintain an annotated bibliography of configurable-computing
references (in bibtex format).



-- 
Brad L. Hutchings                                         VOICE: (801) 378-2667
Dept. of Elec. & Computer Eng.                              FAX: (801) 378-6586
459 Clyde Building                                      EMAIL: hutch@ee.byu.edu
Brigham Young University 
Provo, Utah 84602                http://www.ee.byu.edu/faculty/hutch/hutch.html


Article: 4297
Subject: Re: FPGA Web Links
From: "John L. Smith" <jsmith@univision.com>
Date: Fri, 11 Oct 1996 09:37:15 -0700
Links: << >>  << T >>  << A >>
William J. Wolf wrote:
> 
> It has been a while since I visited this FPGA links page:
> 
>   http://www.mrc.uidahol.edu/fpga/fpga.html
> 
> Congrats to whomever maintains it.  It is greatly improved!
> 
> It contains links to FPGA related conferences, tools, education
> groups & projects, vendors, comp.arch.fpga archives, tutorials,
> consultants, etc.  Check it out.
> 
> --
> - Bill Wolf, Raleigh NC
> - My opinions, NOT my employer'sThanks for the link, but that should read:

 http://www.mrc.uidaho.edu/fpga/fpga.html


-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 4298
Subject: Serial EEPROM problem
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 11 Oct 1996 09:53:41 -0700
Links: << >>  << T >>  << A >>
Andrew, below is the advice I gave to the Xilinx FAEs when debugging a
configuration problem.
Your case is simpler, because you know that it works with a Xilinx
SPROM.
Hook a scope, or better a Logic Analyzer onto the CCLK, DIN, and DOUT
pins and compare the behavior during the first 40 clock ticks of CCLK. I
am pretty sure you will find the problem there. Check the CCLK speed:
Atmel PROMs are slower than Xilinx, but that should not matter below 5
MHz.
How many PROMs do you intend to save with all this agony ?

Peter Alfke, Xilinx Applications

Here comes my advice:

Configuration Problems;

Best diagnosis:
First check for proper dc levels on the Mode pins. Any voltage between
0.4 and 2.5 V indicates a problem that absolutely must be fixed fist.

Then check for the appearance of the 40-bit preamble at each Dout, even
along the daisy-chain. If it doesn’t appear perfectly, staggered by only
one CCLK period, on all DOUT pins, then there is something seriously
wrong with the beginning of the file, or with CCLK. 
If the preamble is transmitted correctly, then it is meaningful to
investigate the content of the configuration file. Always check DOUT
first.

Most likely causes of configuration problems :

1. Bad levels on mode pins, when these pins are not directly connected
to Ground or to a max 5kilohm pull-down or pull-up resistor.
Recent revisions of the XC3k devices have a stronger internal “weak”
pull-up, below 20 k*, which is not compatible with a high-value external
pull-down resistor. Our traditionally recommended value of 5 kilohm is
still ok, but don't go any higher.

2. Overshoot, undershoot and ringing on CCLK. This is a very fast
output, it cannot be made slew-rate limited, and it might be routed a
long distance, driving many daisy-chained devices. That’s a troublesome
combination.
Remedies are: slowing CCLK down by loading it with a 50 pF capacitor,
terminating it at the far end, buffering it, changing CCLK distribution
from a string to a star, re-laying out the pc-board, etc.

3. SPROM RESETbar not driven by INITbar. Yes, there are other ways to
reset the XC1700 serial EPROMs, but INITbar is the only way to be immune
to strange Vcc rise times, and it is the mandatory method when you use 
serial PROMs from AT&T or Atmel.

Consult the Xilinx ‘96 data book, pages 13-25 ... 34 ( 14-25...34  in
the first printing) when you run into a configuration problem. 
Be confident, it can always be fixed ! Most ( not all ! ) problems are
caused by silly oversights.

Hope this helps,
Peter Alfke
Article: 4299
Subject: Info/opinions wanted for PCI interface in an FPGA
From: dan.bartram@gtri.gatech.edu (Dan Bartram)
Date: Fri, 11 Oct 96 17:08:46 GMT
Links: << >>  << T >>  << A >>
I'm planning on a PCI interface design and would like some first-hand
experiences and opinions on implementing this interface in an FPGA,
especially a Xilinx part.  If you have done this, any comments would be
appreciated.

thank you,

Dan Bartram

****************************************************************************
Dan Bartram, Jr.
Internet:  dan.bartram@.gtri.gatech.edu
****************************************************************************


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