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Messages from 4200

Article: 4200
Subject: CDMA DSP
From: "A. Spanias" <spanias@asu.edu>
Date: Wed, 25 Sep 1996 11:22:01 -0700
Links: << >>  << T >>  << A >>
****  CDMA   *****   DSP   ******   CDMA   ******    DSP   *****   CDMA 
 ****



* Announcing Two Short Courses in CDMA Communications & DSP *
              ** December 1996 in Phoenix Arizona **


            (1) Fundamentals of Digital Signal Processing

                    December 2-4, 1996 (3 days)
                 Instructor: Prof. Andreas Spanias 
                     of Arizona State University
                Includes: Hands on Experiments on the PC
             Description of Algorithms and Applications
               Participants take back to Work Place
                Software and a complete set of Notes


       (2) Principles and Applications of CDMA Communications

                     December 5-6, 1996 (2 days)
     Instructors: Prof. John Sadowsky and Prof. Andreas Spanias
                   of Arizona State University
     Includes Description of IS-95, IS-96, and IS-127 Standards
    Participants take back to Work Place a Complete Set of Notes



    At Grace Inn Hotel Awhatukee, Phoenix, Arizona

Coordinator for both courses: Andreas Spanias of Arizona State 
University

**** Group and Early registration Discounts ***

If you need a complete brochure

Send email to:
spanias@asu.edu


Please include:
name
company (include mail stop)
address
city, state, zip
phone/fax
email


****  CDMA   *****   DSP   ******   CDMA   ******    DSP   *****   CDMA 
 ****
Article: 4201
Subject: Re: How to Begin with FPGA design?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 25 Sep 1996 13:25:10 -0700
Links: << >>  << T >>  << A >>
In the spirit of helping newcomers, 
the www addresses are the obvious:

www.actel.com     www.altera.com      www.xilinx.com

strictly in alphabetical order, or in reverse order of revenue :-)

Peter Alfke, Xilinx Applications
Article: 4202
Subject: Re: 4800 baud serial input to xc4000
From: Ray Andraka <randraka@ids.net>
Date: Wed, 25 Sep 1996 14:55:50 -0700
Links: << >>  << T >>  << A >>
Curt Schibonski wrote:
> 
> Help!
> The problem that I see is how to input the ascii data serially.
> 
> I want to input the character strings, manipulate them, and them pass them out the "other side".
> 
> How can I sample the serial input as not to lose bits of data?
> 
> Any ideas?

The technique for sampling the data is pretty well defined in the 8530 
UART data sheets from Zilog and others.  Basically you want to run a 
higher frequency clock (typically 16x) and sample the incoming data 
stream at that rate.  Before a start bit is recognized, you look for a 
couple of consecutive mark samples (typically 3 or 4) before deciding 
that it really is a start bit.  THis kills noise effects.  Then sample at 
the bit mid points (the start bit mid point would be 4 or 5 clocks from 
the detection of the start in a 16x system).  Sample again every 16th 
clock to read the midpoints of the bits.  If you want to get fancier, you 
can sense several of the samples around the mid points and vote on the 
level for a little more noise immunity.  Naturally, the recieve clock 
bit rate needs to be reasonably close to the transmitter.  The exact 
amount of error tolerable can be calculated from the cumulative drift 
over the bits (When the cumulative error exceeds a half bit time either 
way the reception gets garbled).  Realistically, your tolerance is a 
little tighter to account for noise on the start detection and bit 
jitter.  Hope this gets you started.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 4203
Subject: Re: Q: PLD vs. FPGA
From: janoss@vcd.hp.com (Janos Szamosfalvi)
Date: 25 Sep 1996 23:24:37 GMT
Links: << >>  << T >>  << A >>
Michael Payne (mpayne@io.com) wrote:

: My problems is that when I use external memory with an MCU most of my I/O 
: pins get used and there isn't enough left to connect the rest of my 
: components.  I searched for a simple control port chip but could not find 
: one that would solve my problem.  Would an FPGA or PLD solve my problem?  
: Could I use one of these devices to map into the address space and access 
: these devices?  Also, could I program an FPGA or PLD to do my data access 
: for me and just send an interrupt when the data was ready?

The sort answer is yes for all the above; nonetheless, based on 
your post I think you could do just fine if you do multiplexed I/O
if very high performance is not a requirement.

You probably need some bidirectional latches and maybe a few other 
miscellaneous parts.
Article: 4204
Subject: Re: 4800 baud serial input to xc4000
From: "John L. Smith" <jsmith@univision.com>
Date: Wed, 25 Sep 1996 18:38:46 -0700
Links: << >>  << T >>  << A >>
Curt Schibonski wrote:
> 
> Help!
> 
> I am working on a project that requires a 4800 baud serial input to an xc4000.
> I am using a Maxim202 to convert from RS232 to TTL...works great.
> 
> I have contacted Xilinx, checked out their homepage, and data books, but I can't find any examples or ideas to help me input this data.
> 
> The problem that I see is how to input the ascii data serially.
> 
> I want to input the character strings, manipulate them, and them pass them out the "other side".
> 
> How can I sample the serial input as not to lose bits of data?
> 
> Any ideas?
> 
> Thanks
> 
> Curt Schibonski
> Electrical Engineering
> St. Cloud State University
> curtis@tigger.stcloud.msus.edu

Check _1st_ edition of Xilinx data book if you can find one.
It contains a UART design example. Don't know how it works.

-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 4205
Subject: Partition tool for FPGAs?
From: Teppo Hemia <teppo.hemia@nmp.nokia.com>
Date: Thu, 26 Sep 1996 16:13:30 +0300
Links: << >>  << T >>  << A >>
Hi all,

Does anyone know a good partition tool for multiple
FPGAs? It should not be too automatic letting possible
to do the partition partly manually also. 

It can be fully manual, if it is interactive for 
resulting the partition changes.

Any suggestion most welcome.

T. Hemia
Article: 4206
Subject: hardware implementation of permutation multiplication
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Thu, 26 Sep 1996 16:54:25 +0200
Links: << >>  << T >>  << A >>
Hello,
The subject states it (I hope):
I am looking for work on implementing the multiplication of 
permutations (i.e. elements of the symmetric group) in 
hardware (FPGA, VHDL, gates or so). 
I am totally free in encoding the elements, but
of course some compact representation is required 
(O(log n!)).
Thanks in advance.
-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                 
                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 4207
Subject: Re: XilinX XC5200 address pointer based FIFO
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 26 Sep 1996 09:11:49 -0700
Links: << >>  << T >>  << A >>
The implementation depends on the synchronous or asynchronous nature of
the FIFO write and read operations. It is very simple when there is a
common clock for read and write, but more demanding when the two
operations are asynchronous.
By the way, the Xilinx XC4000E family is more efficient in implementing
FIFOs:
In XC5200 the FIFO storage must use the available flip-flops ( 4 per CLB
), so an 8-wide, 16 deep FIFO needs 32 CLBs just for storage ( plus some
for addressing and control )  while the same size FIFO needs only 8 CLBs
for storage in XC4000E, using the dual-port RAM structure which also
avoids address multiplexing and speeds up operation.

There is a new Xilinx app note on the web that describes the control
structure of fast ( >50 MHz for simultaneous read and write )
synchronous and asynchronous FIFOs, 16, 32, or 64 deep, using XC4000E.
It is called "XAPP051: Synchronous / Asynchronous FIFOs".

Peter Alfke, Xilinx Applications
Article: 4208
Subject: Re: How to Begin with FPGA design?
From: lharold@mrc.uidaho.edu (Len Harold)
Date: 26 Sep 1996 16:31:20 GMT
Links: << >>  << T >>  << A >>
Scott Schlachter (scotts@actel.com) inspired us with the words:
> Xiangdong:
> There is actually a very large amount of information available 
> to the internet community regarding FPGA's at the various
> vendor sites.  Before I came to work here at Actel, I spent some
> time researching the general subject of "Programmable Logic 
> Devices" for a report I did in school.  I found that the World
> Wide Web sites for Actel, Altera, and Xilinx alone had fairly large
> amounts of information on them regarding not just their 
> particular products, but programmable logic devices in general.
> If you want to learn more about FPGAs in general, as well as
> getting an idea of what the various vendors have available, 
> you might try checking out their Web sites.  
> Actel's URL is http://www.actel.com  
>
> (I forget what Xilinx or Altera's URLs are... ;-) )

Just point to the FPGA meta-index to find them.  It is at:

  http://www.mrc.uidaho.edu/fpga/


Len Harold
--
     ___    ___  ________  ______
    /\  \  /|  \|\   _   \/\   __\     Len Harold
    \ \   - |   \ \  \_\ /_ \  \_/
     \ \  \ _|\  \ \   _   \ \  \___   Phone: 208-885-7034
      \ \__\/\ \__\ \__\ \__\ \_____\  Fax:   208-885-6840
       \/__/  \/__/\/__/\/__/\/_____/  Internet:
                                       lharold@mrc.uidaho.edu
Article: 4209
Subject: Re: 4800 baud serial input to xc4000
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 26 Sep 1996 17:21:13 -0700
Links: << >>  << T >>  << A >>
The XC4000 device can implement any combinatorial or sequential logic
that you can think of.
Somehow, you have to end up with a data line and a clock signal. How you
get there depends on the available input. Is it self-clocking ( like
Manchester code ), or is it like a UART, and how stable is the incoming
bit rate?

If you can be more specific about the nature of your input signal, it
will be easy to describe the circuit implementation.
Peter Alfke, Xilinx Applications ( peter@xilinx.com )
Article: 4210
Subject: CFP: Design and Test
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 27 Sep 1996 04:10:10 GMT
Links: << >>  << T >>  << A >>
Sorry if this is a repost.  Aggies have been messing with our mail
system.


                        Call For Papers:  FPGA
                  IEEE Design and Test of Computers
                            Special Issue
                   Spring 1998, Volume 15, Number 1
     Web Page: http://www.cs.tamu.edu/faculty/lombardi/datsi.htm

IEEE Design and Test of Computers seeks original manuscripts for a
theme issue on Field Programmable Gate Arrays (FPGAs) scheduled to
appear in the first issue of 1998.  Articles concerning applied
research and practical experience reports are solicited.  The topics
of interest include, but are not limited to:

   FPGA Fabrication and Technology.  Manufacturing, process control,
   yield enhancement, and novel architectures for and device
   technology to support field programmable chips.

   Exploitation of Field Programmability.  Configurable computer
   architectures, rapid prototyping, programmable interconnect
   architectures, field configurable memories, programmable I/O
   systems, and novel implementations.

   Reliable Online Implementations.  Online testing, built-in
   self-test, concurrent testing, design for rapid testability,
   latency reduction, fault containment, verification of
   reprogramming, online reconfiguration approaches, and design for
   reconfigurability.

   Synthesis Approaches and Tools.  Partitioning, logic minimization
   and technology mapping, placement and routing, test generation,
   verification of synthesis, and design for synthesizability.

Submitted articles must not have been previously published or
currently submitted for publication elsewhere.  Authors should submit
their original work to the guest editor by May 1, 1997, formatted
according to the instructions below.  Notification of acceptance will
be sent September 1, 1997.  Camera-ready copy for accepted papers will
be due November 1, 1997.

Submit articles by May 1, 1997 to:

Prof. Fabrizio Lombardi, Guest Editor
Department of Computer Science                  Phone:  (409) 845--5464
Texas A & M University                            Fax:  (409) 847--8578
College Station TX  77843-3112            E-Mail:  lombardi@cs.tamu.edu

Important dates:

        May 1, 1997:  Submission deadline
  September 1, 1997:  Authors notified of acceptance
                      with requested revisions
   November 1, 1997:  Final copy due to Design & Test Managing Editor
        Spring 1998:  Publication in IEEE Design and Test of Computers

Submission requirements:

Send six (6) copies of the manuscript, in English, to the guest
editor.  Manuscripts are not to exceed 35 double-spaced pages,
inclusive of figures and tables, in A4 or 8.5 by 11 inches.  Type size
must be at least 12 point.  Each copy of the manuscript must contain a
cover page with author contact information (name, postal address,
telephone number, and e-mail address) and a 100-word abstract.
Manuscripts must be cleared for publication.  Accepted manuscripts
will be edited for technical content, structure, style, clarity, and
grammar.  Detailed information for authors can be found at the Computer
Society D&T website at http://www.computer.org/pubs/d&t/d&t.htm or in
the Spring 1996 issue of Design & Test.
Article: 4211
Subject: Re: Q: PLD vs. FPGA
From: granville@decus.org.nz
Date: 27 Sep 96 21:22:31 +1300
Links: << >>  << T >>  << A >>
In article <51vi06$3ad@nntp-2.io.com>, mpayne@io.com (Michael Payne) writes:
> I'm a hobbyist that is designing a project using an MCU (PIC17 or 
> something else) that will connect to the following:
> 
> * 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
> * Graphic LCD display with builtin controller
> * Serial A/D converter
> * An A/D device that clocks out 24-bits of data 4-bits at a time.
>   This device needs two 2ms delays before bit 0 and bit 12.
> * Possibly a serial eeprom for data storage
> * 3-5 pushbuttons of user input
> 
> My problems is that when I use external memory with an MCU most of my I/O 
> pins get used and there isn't enough left to connect the rest of my 
> components.  I searched for a simple control port chip but could not find 
> one that would solve my problem.  Would an FPGA or PLD solve my problem?  
 Quite probably ( and also cause a few more :-)

> Could I use one of these devices to map into the address space and access 
> these devices?  Also, could I program an FPGA or PLD to do my data access 
> for me and just send an interrupt when the data was ready?
 

> 
> I've seen PLD designs that are basic I/O control ports (Amtel had one on 
> their web page) but one of my devices needs two 2ms delays during it's 
> access.  Can you program delays in PLDs?
 You can do anything, wihtin reason in a PLD/FPGA - the question is cost.
When you have a micro right next door, it is best to leave this to do
the slow ( 2mS ) stuff.
Likewise, a PLD could do state machine scanning & store, but unless speed
is imperative the micro is better at this.

 we have designs for Serial ( i2c bus for medium, 24 Pin PLDs, SPI bus for
the smallest ones )
 Addressable LATCH ( busable )
and Port Expansion ( like 82C55 )
All have their relative merits.
 Parallel bus designs are fast, but you are into 44 pin plds typically.
 Add Latch are bit accessible, good for 7i7o or 8i8o in small plds
 SPI are slowest, but are serially cascadable - you get 6i7o, for example
 i2c needs a smarter PLD, but uses the lowest CPU pin overhead, and low
SW overhead, if you already have Serial EE or similar.
 
===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ======
* Developers and suppliers of HDL PLD applications libraries                 *
* for Microcontroller expansion and interface.           		     *
* x51 C, Pascal & Modula-2 Compilers, Simulators, Emulators & FLASH Pgmrs    *
* Contact : Jim Granville . Email above.                                     *

>I've already built this project with a 68HC711E9 and a 2x16 LCD display 
> but the 12K of internal EPROM was a little small and the 512 bytes of 
> EEPROM was not enough.
> 
> Any help or opinions would be appreciated
> 
> Regards,
> Mike
> 
> mpayne@io.com
> 
Article: 4212
Subject: Re: hardware implementation of permutation multiplication
From: hrubin@b.stat.purdue.edu (Herman Rubin)
Date: 27 Sep 1996 07:02:33 -0500
Links: << >>  << T >>  << A >>
In article <324A9921.174F@iti.mu-luebeck.de>,
Andreas Doering  <doering@iti.mu-luebeck.de> wrote:
>Hello,
>The subject states it (I hope):
>I am looking for work on implementing the multiplication of 
>permutations (i.e. elements of the symmetric group) in 
>hardware (FPGA, VHDL, gates or so). 
>I am totally free in encoding the elements, but
>of course some compact representation is required 
>(O(log n!)).
>Thanks in advance.

Extremely crude methods will get O(log n!).  Just storing a
permutation as a mapping takes n log(n), while log n! is less
than n (base e) less than this.  And if n in the image is raised
to the next power of 2, the increase is less than n (base 2).
So compact representations are not particularly needed to 
achieve the order.

-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
hrubin@stat.purdue.edu	 Phone: (317)494-6054	FAX: (317)494-0558
Article: 4213
Subject: Source for 8259 PIC
From: Soren Kristensen <sorenk@inet.uni-c.dk>
Date: Fri, 27 Sep 1996 16:24:50 +0200
Links: << >>  << T >>  << A >>
I'm looking for either vhdl source or schematic for some intel 
peripherals, the 8259 int ctrl, 8254 timer and 8237 dma ctrl. I'm going 
to put them in an actel fpga, but i can use the source and/or schematic 
for any technology.

Does anybody have, or know where to get the source and/or schematics for 
free or a very low fee ?


regards

soren
Article: 4214
Subject: CFP - 1997 Intl. Symp. on Physical Design, April 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Sat, 28 Sep 1996 01:19:47 GMT
Links: << >>  << T >>  << A >>
                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

The International Symposium on Physical Design provides a forum to exchange
ideas and promote research on critical areas related to the physical design
of VLSI systems.     All aspects of physical design, from interactions with
behavior- and logic-level synthesis, to back-end performance analysis and
verification, are within the scope of the Symposium.    Target domains include 
semi-custom and full-custom IC, MCM and FPGA based systems.
 
The Symposium is an outgrowth of the ACM/SIGDA Physical Design Workshop.  
Following its five predecessors, the symposium will highlight key new 
directions and leading-edge theoretical and experimental contributions to 
the field. Accepted papers will be published by ACM Press in the Symposium 
proceedings. Topics of interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:
    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:
    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Past Chair:                  G. Robins (Virginia)
General Chair:               A. B. Kahng (UCLA and Cadence)
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) and E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego),
                             W. W.-M. Dai (UC Santa Cruz), 
                             J. Frankle (Xilinx), 
                             D. D. Hill (Synopsys), 
                             M. A. B. Jackson (Motorola), 
                             J. A. G. Jess (Eindhoven),  
                             Y.-L. Lin (Tsing Hua), 
                             C. L. Liu (Illinois),
                             M. Marek-Sadowska (UC Santa Barbara),
                             M. Sarrafzadeh (Northwestern), Chair, 
                             C. Sechen (Washington), 
                             K. Takamizawa (NEC),
                             M. Wiesel (Intel), 
                             D. F. Wong (Texas-Austin), 
                             E. Yoffa (IBM)
 

Article: 4215
Subject: Re: FIR filter using FPGAs??
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 28 Sep 1996 15:35:35 -0400
Links: << >>  << T >>  << A >>
K. S. Venkatraman wrote:
> 
> Hi:
> 
> I am interested in writing VHDL code for the AT&T ORCA FPGA in
> order to implement an FIR filter. I have the ORCA Foundry software,
> but do not have Exemplar.. instead we have AutoLogic. I need to know if
> I can generate the appropriate EDIF files using AutoLogic.
> 
> Any tips?
> 
> Thanks,
> Venkat.
> What is AutoLogic ? If AutoLogic is an HDL tool you should certainly be 
able to write an FIR filter. What type of FIR are you after? 


Richard
Article: 4216
Subject: Re: Source for 8259 PIC
From: scanner@dial.pipex.com (Peter)
Date: Sun, 29 Sep 1996 07:57:29 GMT
Links: << >>  << T >>  << A >>
I have always kept an eye open for these things, and have never seen
them. The reasons are probably obvious; the same reasons you don't see
the schematics of a Z80 published. A lot of people would give their
right arm for these things, when doing an ASIC.

I have seen a simplified schematic of one of the old Intel UARTs in an
old Altera app note book.

However, some ASIC vendors will have "macros" for these or similar
chips. Some will be licensed, some not, and sometimes they will keep
relatively quiet about this capability :) But they won't give you the
stull unless you are doing an ASIC with them.

>I'm looking for either vhdl source or schematic for some intel 
>peripherals, the 8259 int ctrl, 8254 timer and 8237 dma ctrl. I'm going 
>to put them in an actel fpga, but i can use the source and/or schematic 
>for any technology.
>
>Does anybody have, or know where to get the source and/or schematics for 
>free or a very low fee ?

Article: 4217
Subject: Z8000 microprocessors, C cross-compiler and a PLZ/ASM assembler
From: Thomas Scherrer <tscherrer@ite.dk>
Date: Mon, 30 Sep 1996 13:30:42 +0200
Links: << >>  << T >>  << A >>
We're using a Zilog S8000 system to develop Z8000 embedded inertial
navigation software, using the Zilog C and Zilog PLZ/ASM assembly
language.
 We are contractually obligated to support our systems for 20 years, but
Zilog no longer supports the S8000 or the Z8000 microprocessors.  We
wish to
obtain a C cross-compiler and a PLZ/ASM assembler that will run on a Sun
(first choice) or PC.

Help!

Larry Riggs
Litton Aero Products
Woodland Hills, CA
(818) 226-2031
mailto:laarry@aol.com


-- 
Thomas Scherrer-Tangen.                mailto:tscherrer@cybernet.dk
                                      
http://www.cybernet.dk/users/tscherrer
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Article: 4218
Subject: money maker
From: Eric Page <bart@ultranet.com>
Date: Mon, 30 Sep 1996 12:42:49 -0400
Links: << >>  << T >>  << A >>
Hi There!  I've got some fantastic news!  I think you should read if you

need to get some serious cash in a hurry.  Get a printout of this

information or save this on your desktop.  This works, I did it. It got

me out of debt and paid for an upgrade in my computer equipment.  Let's

start by saying that I don't trust get rich schemes.  We've all seen

them on late night T.V. and we've all tuned them out.  Maybe they work

for some people but

 not me.  The difference with this system is the low investment, only

$5, the cost of a lunch, and quick turnover.  I was scanning through a

Newsgroup and saw an article stating that I could get rich fast.  The

article described a way to MAIL A ONE DOLLAR BILL TO ONLY FIVE PEOPLE

AND MAKE $50,000 IN CASH IN ONLY FOUR WEEKS!!!  The more I considered it

the more excited I became about the idea.  Considering just my credit

cards alone and ho

w much of each of my payments went to interest alone, $5 was a tiny

investment and it got me the money to pay off my debts.  IT ONLY COST ME

FIVE(5) DOLLARS, AND FIVE STAMPS, THATS ALL I EVER PAY...EVER!!!  Ok, so

maybe $50,000 in cash was maybe a tough amount to reach but it was

possible.  I knew that I could get a return of $1,000 or so.  SO I DID

IT!!  As per the instructions in the article, I mailed out ("snail mail"

for you e-mail fans) a single dollar bill to each of the five names on

the list contained in the article.  I included a note with the dollar,

that stated "Please Add Me To Your List.  "Then I removed the first name

on the list of five names, moved everyone up one position and added my

name to the end of the list.  This is how the money starts rolling in!! =


I then took the revised article now with my name on the list and

REPOSTED IT ON AS MANY LOCAL BULLET

IN BOARDS THAT I KNEW(ABOUT 200). I then waited and watched for the

money to come in, prepared for maybe $1,000 to $1,500 in cash or

anything at all.  But what a shock when the envelopes kept coming in!!! =


I knew what they were as soon as I saw the return addresses from people

all over the world, Mostly from the U.S.A., but some from Canada and

even Australia!  So how much did I get in return? $1,000? $5,000? No

Way!!! I received a totaL =


OF $19,471!!!  I WAS SHOCKED!       =




Now after almost a year, I am ready to try it again! So was it possible

to hit $50,000, I don't know, but it COMPLETELY DEPENDS ON YOU, THE

INDIVIDUAL! You must follow through and repost this article everywhere

you can think of! The more postings you achieve will determine how much

cash will arrive in your mailbox!!!  It's just too easy to pass up!! =


Let's review the reasons why you should do this: the cost is only five

one dollar bills, =


five stamps, five envelopes, five minutes to mail them off and time to

post your updated article (with your name in possition five) in as many

newsgroups and BBS's as you can find.  We all have $5 to put into such

an easy and effortless investment with SPECTACULAR REALISTIC RETURNS OF

$15,000 to $20,000 in 3-5 weeks!  YOU CAN'T LOSE!!  So how do you do it

exactly, you ask? I Have provided the most detailed yet straightforward

insrtuctions

 for you.  SO, ARE YOU READY TO MAKE SOME MONEY? HERE WE GO!!! =




***THE LIST OF NAMES IS AT THE END OF THE ARTICLE***



Read this carefully or get a printout if you like, so that you may refer

to it as often as you like.



1.  Take a sheet of paper and write on it the following: "please add me

to your list".  This creates a service out of this money making system

and makes it perfectly legal. You are not just randomly mailing a dollar

to someone, you are paying for a legitimate service.  Make sure to

include your name and address.  Also add the name of a newsgroup where

it will be posted, so that the receipent may check if he/she wishes.



2.  Now take this sheet of paper and wrap it around the dollar bill,

then put it into an envelope and mail it to one of the five paople on

the list. Folding the paper around the bill and concealing it will

insure it's arrival and reduce mail theft. A thick, dark paper is

recommended to prevent theft. THIS IS IMPORTANT!!



3.  Now listen carefully, here's where you get your money rolling in.

Look at the list. remove the first name. Move everyone up on the list.

The name in position 2 moves to position 1, position 3 to 2, position 4

to 3, position 5 to 4. Then add your name, address, zipcode and country

to position 5.



4. Now upload the updated article to as many newsgroups as you can.  Try

to post it to as many loca BBS=92s as possible too.  Give it a catchy

title.  Such as "EA$Y MONEY", "FA$T CA$H" or "NEED CASH TO PAY OFF

DEBTS?".  The more posts the more money you will make, and of course,

the more money the others on the list make too.  PLEASE REMEMBER that

this program remains successful because of the honesty and integrity of

the participants and b

y their carefully adhering to the directions.  REMEMBER, BE HONEST AND

EVERYONE WILL MAKE MONEY OUT OF THIS PROFITABLE AND EASY SYSTEM!!! You

will reap the benefits, believe me!!!  Set a goal for the number of

posts, at least 200, and always have a goal in mind.



5.  This is the step I like. JUST SIT BACK , RELAX AND WAIT FOR THE CASH

TO ARRIVE!!  The first one or two weeks will be slow but it will pick up

and your mailman will hate you because of all of the extra weight! So

pay off your bills and debts and if you ever need any extra cash repost

it every year or so.  =




NOW LET ME TELL YOU WHY THIS SYSTEM WORKS!  Of every 200 postings I

made, I received an average of 5 replies, YES ONLY 5, each with a $1

bill enclosed. You make $5 for every 200 postings WITH YOUR NAME AT

NUMBER 5.  Each person who sent you $1, now also makes let's say, only

200 additional postings WITH YOUR NAME AT NUMBER 4, i.e. 1000 postings. =


On average therefore, 50 people will send you $1 with your name at

number 4. You make $50.  Y

our 50 new agents make 200 posting each WITH YOUR NAME AT NUMBER 3 or

10,000 postings - average return 500 at $1 each is $500. They make 200

postings each WITH YOUR NAME AT NUMBER 2 =3D 100,000 postings =3D 5,000

returns at $1 each =3D $5,000. Finally, 5,000 people make 200 postings

each WITH YOUR NAME AT NUMBER 1 and you get a return of $50,000 before

your name drops off the list.  AND THAT'S IF EVERYONE DOWN THE LINE ONLY

MAKES 200 POSTINGS! =


 Total income in one cycle =3D $55 500.  From time to time, when your nam=
e

is no longer on the list, you can take the latest posting that is

appearing in the newsgroups, SEND OUT ANOTHER $5 TO THE NAMES THAT ARE

ON THE LIST, PUT YOUR NAME IN AT NUMBER 5 AND START POSTING AGAIN. =


Remember, 200 postings is only a guideline. The more you post, the

greater the return.  Some people have said to me "What happens if the

scheme is 'played out' and =


no one sends me any money"? Big deal! So you lose $5 - but what are the

chances of that happening?  Do you realise how many Internet Users there

are?  Do you realise how many times this scheme can be utilised over and

over again - with COMPLETELY NEW people participating?  There are not

HUNDREDS, NOT EVEN THOUSANDS, BUT HUNDREDS OF THOUSANDS OF NEW INTERNET

USERS EVERY MONTH! Remember, read the instructions carefully and play

FAIRLY...that's the only way this will work. Get a printout so you can

refer back to this article easily.  Try to keep a list of everyone that

sends you money and always keep an eye on the newsgroup postings to make

sure everyone is playing fairly. You know where your name should be.



********************************************************************  =


NAMES LIST     NAMES LIST     NAMES LIST     NAMES LIST       =


********************************************************************

           !!!!!!!!HONESTY IS WHAT MAKES THIS PROGRAM WORK!!!!!!!!



1. Christy Johnson

   P.O. Box  181, =


   C.R. , IA 52406-0181



2. Gilbert Banks Jr.

   707 Wedgewood Plaza Drive, =


   Riviera Beach, FL 33404	=




3. Brian Edwards

   5635 Kirkwood Blvd. SW # 8,  =


   Cedar Rapids, IA 524042

 =


4. John Nicholas

   P.O. Box 640144

   Bayside, NY 11364



5. Eric Page =


   20 Mercury Lane =


   Nashua, NH   03062	=


   =


********************************************************************

THIS REALLY WORKS, IT GOT ME OUT OF DEBT AND PAID FOR A NEW =


COMPUTER. SO GIVE IT A TRY! AND REMEMBER, THIS PERFECTLY LEGAL

********************************************************************
Article: 4219
Subject: Viewlogic 4.1 (DOS) mouse alternatives?
From: scanner@dial.pipex.com (Peter)
Date: Tue, 01 Oct 1996 11:05:13 GMT
Links: << >>  << T >>  << A >>
Hello,

The above app requires a "Mouse Systems PC Mouse". It calls it
directly, on com1 or com2, so any driver emulation does not work.

Has anyone ever found a way to use a normal "Microsoft" serial or bus
mouse with this program?

The reason I ask is that mice which *internally* emulate the old
PC-Mouse are now rare. Perhaps I should ask if anyone has one of the
original 3-button Mouse Systems optical mice to sell :)

I cannot afford to move to any of the Windows versions of this prog -
even if they were better.

Peter.
Article: 4220
Subject: Re: Viewlogic 4.1 (DOS) mouse alternatives?
From: ecla@world.std.com (alain arnaud)
Date: Tue, 1 Oct 1996 16:05:29 GMT
Links: << >>  << T >>  << A >>
Peter (scanner@dial.pipex.com) wrote:
: Hello,

: The above app requires a "Mouse Systems PC Mouse". It calls it
: directly, on com1 or com2, so any driver emulation does not work.

: Has anyone ever found a way to use a normal "Microsoft" serial or bus
: mouse with this program?

	Try a 3 button Logitech serial mouse.
Article: 4221
Subject: Re: XilinX XC5200 address pointer based FIFO
From: Marc Baker <marc.baker@xilinx.com>
Date: Tue, 01 Oct 1996 11:18:14 -0700
Links: << >>  << T >>  << A >>
Here is the exact location of the Xilinx FIFO app note:

http://www.xilinx.com/xapp/xapp051.pdf

There is also on app note called "Implementing FIFOs in
XC4000E RAM:

http://www.xilinx.com/xapp/xapp053.pdf

which has design files available at:

ftp://ftp.xilinx.com/pub/xapp/FIFO/4kefifo.zip
Article: 4222
Subject: Re: Viewlogic 4.1 (DOS) mouse alternatives?
From: daveb@iinet.net.au
Date: Tue, 01 Oct 1996 22:03:56 GMT
Links: << >>  << T >>  << A >>
ecla@world.std.com (alain arnaud) wrote:

>Peter (scanner@dial.pipex.com) wrote:
>: Hello,

>: The above app requires a "Mouse Systems PC Mouse". It calls it
>: directly, on com1 or com2, so any driver emulation does not work.

>: Has anyone ever found a way to use a normal "Microsoft" serial or bus
>: mouse with this program?

>	Try a 3 button Logitech serial mouse.

Also the 3-button Genius mouse. Using the Genius driver, this will
also emulate a M$ mouse, under DOS and Windows.


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html

Article: 4223
Subject: Has anyone changed from ViewLogic to Foundation [Q]
From: gavin@cypher.co.nz (Gavin Melville)
Date: Wed, 02 Oct 1996 00:52:01 GMT
Links: << >>  << T >>  << A >>
Hi,

As a long time ViewLogic user I am considering changing to the Aldec
tools (Foundation) -- mainly to get a usable simulator.

Has anyone else done this, and how did the changeover go ? -- I am
aware that you can convert the schematics, but this involves a bigger
picture.

TIA,


--
Gavin Melville,
gavin@cypher.co.nz

Article: 4224
Subject: Re: Has anyone changed from ViewLogic to Foundation [Q]
From: mush@netgate.net (David Decker)
Date: Wed, 02 Oct 1996 03:16:57 GMT
Links: << >>  << T >>  << A >>
gavin@cypher.co.nz (Gavin Melville) wrote:

>Hi,

>As a long time ViewLogic user I am considering changing to the Aldec
>tools (Foundation) -- mainly to get a usable simulator.

>Has anyone else done this, and how did the changeover go ? -- I am
>aware that you can convert the schematics, but this involves a bigger
>picture.

>TIA,


>--
>Gavin Melville,
>gavin@cypher.co.nz

I have been told by Xilinx that Foundation cannot do hierarchal XBLOX.

I have also been told that the next release (end of October) updates
the obsolete Pro Series to WorkView Office, Win3.1, where the
simulator should work.

Anyone tried Synario for big chips? (4025E)



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