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You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8926
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8927
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8928
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8929
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8930
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8931
You should try to get a copy of the XACTStep 6000 software for Workstations- the libraries are included on there. Craig Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>... >Hi there, > >We are trying to obtain Xilinx XC6200 software through the Xilinx >University Program, but we haven't any news from them. Has anybody >got the Synopsys libraries for this FPGA?Article: 8932
Lars wrote: > Hello, > I have an Asic that is going out of production because the vendor is no > longer supporting this process. The design is about 12500 gates (where a > nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and > runs at 50MHz, made in a 1u process. It is not possible to the chip run > at a higher speed because of all the logic between clocks (Pipelining). > There are many clocks, and a lot of different clears on the FFs. Also > delaylines internally is used. The timing is extremly important, and > must be known. So to my questions: > > 1) Does an FPGA give you the same control over the design as an Asic > does? > 2) Is this a recommended way of going? The alternative is to do another > Asic. We can not afford to use too long time on this. The volum is > pretty low. Hi, Lars If you developed a real synchronous design then you would haven't any headaches today. Your design is mostly asynchronous (many different clocks, using asynchronous set and clear on the FF's not only for intialization I suppose) !!!! Using delaylines in any design make the design very sensitive for any technology alterations!!! I don't know any real cause why you used delaylines in a 50 Mhz design! If you make a redesign of your circuit you should redesign it totally synchronous! If you don't, you'll get the same headaches again and again with every process improvement in the future no matter which vendor you use. If you need small quantities of an ASIC you should use programmable technologies as XILINX for instance. If you later need large quantities XILINX can offer a HardWire solution to you. A synchronous design can be tuned to work at any speed up to the limiting frequency of the technology you used. You must run a Post-Layout-Simulation of your circuit implemented in your technology to calculate this limiting frequency. Hope it helps... AS ( an ASIC-designer who hates headaches)Article: 8933
I find that XMAKE & WIR2XNF just terminate immediately, without doing anything. Neither of these programs check the dongle, so that cannot be the issue. Are there specific settings for the NT4 DOS box, for XACT6? BTW, WIR2XNF has a dreadful piece of code in it, flushing disk write buffers many thousands of times in a tight loop. Under DOS, this really slows it down although SMARTDRV helps. Under win3.x (DOS box) with "32-bit file access" it runs much faster, about 20x. Under NT I can't say, for the above reason. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8934
You are of course absolutely right. But may I say there can be legitimate reasons for using delay elements - in ASICs. The problem with a sync design is that nothing can happen in between clock edges. So one may need a 100MHz clock for a very small part of the circuit, and this is a terrible waste of power, and produces problems with EMC compliance, not to mention clock distribution. This can be quite inflexible, and delay elements can provide an elegant solution to the need for several clock edges in rapid succession. The reason why this technique can be perfectly reliable is that the delay in such elements will scale with the rest of the circuit, so if the temperature drops to -40C and the delays shorten by x3, the speed of everything else goes up 3x too, and everything still works. A large proportion of older CPU and similar chips use delays to drive pipelined structures, and this is only what I know about. I am sure these techniques are widely used in today's chips too. In today's ever more demanding low power applications the use of such tricks is the only way to reconcile the need for low dynamic Icc with the need for high performance, without the use of ridiculous clock speeds. There are lots of reasons why such tricks don't work in an FPGA, unless one has carefully done a lot of low level layout by hand, and then the design can be unmaintainable. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8935
Chip Express or QuickLogic or anyone else would probably just use Exemplar Logic software to do the translation and retargetting. You can hand to them, or use it yourself. Check out the website for more info. www.exemplar.com. Larry Steve Mitchell wrote: > > The NRE to do another ASIC would kill you, considering that you have low > volumes. A Xilinx 4K series device would probably suit your application. > I would consider redesign (delay lines - yuck!), but I don't know your > design. Another option is to consult with a company such as Chip Express > or QuickLogic to see if they can translate your ASIC into their technology. > > Steve Mitchell > > In article <34DAAE53.5AB8@online.no>, larsher@online.no says... > > > >Hello, > >I have an Asic that is going out of production because the vendor is no > >longer supporting this process. The design is about 12500 gates (where a > >nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and > >runs at 50MHz, made in a 1u process. It is not possible to the chip run > >at a higher speed because of all the logic between clocks (Pipelining). > >There are many clocks, and a lot of different clears on the FFs. Also > >delaylines internally is used. The timing is extremly important, and > >must be known. So to my questions: > > > >1) Does an FPGA give you the same control over the design as an Asic > >does? > >2) Is this a recommended way of going? The alternative is to do another > >Asic. We can not afford to use too long time on this. The volum is > >pretty low.Article: 8936
In article <34de9232.90032309@news.netcomuk.co.uk> z80@ds.com (Peter) writes: >I find that XMAKE & WIR2XNF just terminate immediately, without doing >anything. > >Neither of these programs check the dongle, so that cannot be the >issue. XMAKE does not check the dongle. WIR2XNF certainly does. You may need the RAINPORT driver installed to make this work. I am assuming you are using WIR2XNF, V5.2.0, which was part of the WV-ProSeries escape (I mean release). It is 661204 bytes, dated 9-15-95 > >Are there specific settings for the NT4 DOS box, for XACT6? Not really > >BTW, WIR2XNF has a dreadful piece of code in it, flushing disk write >buffers many thousands of times in a tight loop. Under DOS, this >really slows it down although SMARTDRV helps. Under win3.x (DOS box) >with "32-bit file access" it runs much faster, about 20x. Under NT I >can't say, for the above reason. This insane bug has been reported to Xilinx multiple time (by me at least 5 different times ), but this is unsupported old software, which they won't fix. I believe that the bug is that some debug code that was used to debug WIR2XNF when they were porting it to Solaris or something, is still in there, and it is doing a flush after every component write. This makes it run 10 (ten!) times slower than the previous release, both in DOS and in NT. The prior version, 378579 bytes, 10-24-94 does not have this problem, but I was never able to get it to run in a DOS box under NT, or even under W3.11. >Peter. Philip FreidinArticle: 8937
I've been using PALASM and GAL20V8 for hobby projects. Don't need much more capability, just more of the same. Like a GAL32V128. The problem with FPGAs is that I can't find any affordable tools to program them. Does anyone support their programmable devices with free base development software? I don't need anything more capable than PALASM. I have a second item on my wish list. I'd like to be able to reprogram an FPGA on the fly. Back when I had access to Xilinx tools, there still was no information available to know which bits did which functions. Best I could do was route it and load the resultant secret patterns. What I really want is to define a few "architecture files" that define the base FPGA configurations that could be loaded into the FPGA configuration RAM. Then I need the capability to reprogram polarities of nodes on the fly. I'll probably buy two FPGAs, total, so there's not much use in asking a vendor for something that's not already published. That's the problem with being retired. You lose access to all those neat expensive hi-tech tools. Any ideas? miker -- Return Address is Bogus. TO REPLY CLICK BELOW. http://www.ethergate.com/users/miker/index.html Usually have stuff WANTED and FOR SALE. If you get a URL error, try again later.Article: 8938
Hello: I direct an entrepreneurial association known as The PARALLEL Processing Connection. We meet monthly in Palo Alto (Sun Microsystems) CA. This Monday's (February 9th) meeting will deal with a new compiler known as C2Verilog. Please attend if you are able. We also have tools that were donated by various vendors ... Altera, etc. for PPC member use at our lab/office in Sunnyvale CA. The point is, you may only be using two FPGA's and therefore are not able to properly influence vendors. However, we as an association have enough leverage for various reasons to be able to better interact with the vendors than any of us as individuals. For example, a while back, Altera donated about $12,000 of hardware/software to PPC. In article <34DD1F0E.74AAA61B@ethergate.com>, Don't, Hit, Reply, Use, the, Link wrote: >I've been using PALASM and GAL20V8 for hobby projects. Don't need much >more capability, just more >of the same. Like a GAL32V128. > >The problem with FPGAs is that I can't find any affordable tools to >program them. Does anyone support their >programmable devices with free base development software? I don't need >anything more capable than PALASM. > >I have a second item on my wish list. I'd like to be able to reprogram >an FPGA on the fly. >Back when I had access to Xilinx tools, there still was no information >available to know which bits >did which functions. Best I could do was route it and load the >resultant secret patterns. > >What I really want is to define a few "architecture files" that define >the base FPGA configurations that could >be loaded into the FPGA configuration RAM. Then I need the capability >to reprogram polarities of nodes on the fly. I'll probably buy two >FPGAs, total, so there's not much use >in asking a vendor for something that's not already published. > >That's the problem with being retired. You lose access to all those >neat expensive hi-tech tools. > >Any ideas? >miker >-- >Return Address is Bogus. >TO REPLY CLICK BELOW. >http://www.ethergate.com/users/miker/index.html >Usually have stuff WANTED and FOR SALE. >If you get a URL error, try again later. -- B. Mitchell Loebel CEO, Chief Technical Officer MultiNode Microsystems Corporation 408 732-9869 Executive Director The PARALLEL Processing Connection 408 732-9869Article: 8939
Todays HOT number comes to from http://21only.com/strip Dia your Intl. access code and then 6787 7401. Get connected to some of the hootest girls in the world. LD rates onlt apply. No charge for service. Over 18 only.Article: 8940
Miker, For $350.00 you can get the APS-X84 Foundation base kit which comes with Foundation base programming tools for FPGAs upto 8Kgates! It also comes with the X84 board which is programmed in circuit. All relavent schematics and documents on how to do this are included. The board can also be used externally with an Xchecker cable (which comes with the kit). You also get full ABEL support for the XILINX CPLDs. It's a great deal, and can be gotten from : http://www.associatedpro.com/aps &miker wrote: &miker wrote: > I've been using PALASM and GAL20V8 for hobby projects. Don't need much > more capability, just more > of the same. Like a GAL32V128. > > The problem with FPGAs is that I can't find any affordable tools to > program them. Does anyone support their > programmable devices with free base development software? I don't need > anything more capable than PALASM. > > I have a second item on my wish list. I'd like to be able to reprogram > an FPGA on the fly. > Back when I had access to Xilinx tools, there still was no information > available to know which bits > did which functions. Best I could do was route it and load the > resultant secret patterns. > > What I really want is to define a few "architecture files" that define > the base FPGA configurations that could > be loaded into the FPGA configuration RAM. Then I need the capability > to reprogram polarities of nodes on the fly. I'll probably buy two > FPGAs, total, so there's not much use > in asking a vendor for something that's not already published. > > That's the problem with being retired. You lose access to all those > neat expensive hi-tech tools. > > Any ideas? > miker > -- > Return Address is Bogus. > TO REPLY CLICK BELOW. > http://www.ethergate.com/users/miker/index.html > Usually have stuff WANTED and FOR SALE. > If you get a URL error, try again later. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8941
SUPER SPECIAL VHDL KIT OFFER!!!! That's Synthesis and Simulation for all leading Vendors plus a XILINX X84 Test board with VHDL examples and labs on CD and a leading VHDL text book. All for under 5K!! You can now get direct from APS the following bundled package: *PeakVHDL PRO+VITAL VHDL SIMULATOR with VITAL SUPPORT * PeakFPGA Synthesis (XILINX,LUCENT,ALTERA,VANTIS,ACTEL,QUICKLOGIC) *One years free maint. *VHDL Made Easy Text *APS-X84 all for $4975.00 !!! see: http://www.associatedpro.com/aps -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8942
Hi, you can get free tools for some GALs and ISP (In Circuit Programmable) small FPGAs from Lattice Semiconuctor- they send you a CDROM with some nice tools, limited to a few small GALs and FPGAs. Their FPGAs are neat BTW. Also you can get a free (but again limited) version of Altera's MAX+ by a web download; check out their web site. The downside to this one is that you have to be on a network to use it. Otherwise it is a good pc of SW. Good luck Jeff &miker <&miker@ethergate.com> wrote in message <34DD1F0E.74AAA61B@ethergate.com>... >The problem with FPGAs is that I can't find any affordable tools to >program them. Does anyone support their >programmable devices with free base development software? I don't need >anything more capable than PALASM. > >Return Address is Bogus. >TO REPLY CLICK BELOW. >http://www.ethergate.com/users/miker/index.html >Usually have stuff WANTED and FOR SALE. >If you get a URL error, try again later. > >Article: 8943
>I've been using PALASM and GAL20V8 for hobby projects. Don't need much >more capability, just more >of the same. Like a GAL32V128. > >The problem with FPGAs is that I can't find any affordable tools to >program them. Does anyone support their >programmable devices with free base development software? I don't need >anything more capable than PALASM. Xilinx now do some relatively cheap software for their low-end XC4000 devices. Ask their local office. Whether you will get the devices at prices which even begin to compare with a PLD is another matter, especially by the time you cost in the means of loading in the bitstream. The historical problem with cost of FPGA software is that Xilinx etc have to pay a hefty license fee to people like Viewlogic. This is out of Xilinx's control. Also, there is the perception, presumably maintained by Marketing Depts that anyone using FPGAs must be rich. So, even though it has always been theoretically possible for Xilinx to give out XACT for free (they actually used to do this in the late 1980s, to "promising" customers) they could not legitimately do this with the schematic part. The obvious solution is for Xilinx to develop their own software, and this is now finally happening, but speaking to people who use the stuff (called Foundation) it still has some way to go to get the bugs out. Also, you can go PALASM (or CUPL) -> PDS2XNF.EXE -> XNFOPT -> XNF and then you need only the place & route tools, e.g. M1.4. I believe that cut-down versions of those are also available. However, Xilinx no longer give out the PDS2XNF etc Palasm to XNF conversion programs. I have done the above from CUPL, with XACT as the P&R back end, but I still used a schematic prog (Viewdraw) to draw the top-level sheet listing the pins etc. I think this is easy enough to get around, though. I have never heard of any *free* toolkit for Xilinx, and there cannot be one as long as Xilinx charge for the P&R tools, since Xilinx is the sole vendor of P&R tools for their devices. >I have a second item on my wish list. I'd like to be able to reprogram >an FPGA on the fly. >Back when I had access to Xilinx tools, there still was no information >available to know which bits >did which functions. Best I could do was route it and load the >resultant secret patterns. You can with RAM-based FPGAs, e.g. Xilinx, but the bit patterns are still secret. This is a selling point, making reverse engineering much harder. >What I really want is to define a few "architecture files" that define >the base FPGA configurations that could >be loaded into the FPGA configuration RAM. Then I need the capability >to reprogram polarities of nodes on the fly. I'll probably buy two >FPGAs, total, so there's not much use >in asking a vendor for something that's not already published. Not possible AFAIK. The only way is to generate a .bit file for each combination you want. I suppose you could work out which bits in the .bit file change as you change some small details. That way, you could potentially reverse engineer the bitstream. Presumably Neocad did that, plus (I certainly would in such a situation) disassembly of XACT.EXE and such. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8944
>XMAKE does not check the dongle. WIR2XNF certainly does. You may need the >RAINPORT driver installed to make this work. I am assuming you are using >WIR2XNF, V5.2.0, which was part of the WV-ProSeries escape (I mean release). >It is 661204 bytes, dated 9-15-95 Mine is 15/09/95 14:34 661,204 WIR2XNF.EXE It came on the XACT6.01 CDROM. Same one as yours. I will work on it. There is still the problem with XMAKE though. Odd. >This insane bug has been reported to Xilinx multiple time (by me at least >5 different times ), but this is unsupported old software, which they won't >fix. Unsupported? Not only it comes on the XACT6 CDROM, which cost me $4000 (a substantially discounted figure back then) in 1996, but they also *presently* ask $1600 (UK, this is) for annual maintenance on *this* software. I wonder if NT's disk caching stops this. Win3.x certainly does. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8945
Nobody mentionned Actel's "free" Designer Lite place & route tool good for designs up to 8000 gates. They also provide a free VHDL synthesiser (although somewhat limited) good for a certain number of lines of code (don't remember exactly how many). However, with Actel devices you need a programmer which can be a little expensive but I assume you probably have one, being a "programmable logic kinda' guy". Hope this helps, Sam Falaki &miker wrote: > I've been using PALASM and GAL20V8 for hobby projects. Don't need much > more capability, just more > of the same. Like a GAL32V128. > > The problem with FPGAs is that I can't find any affordable tools to > program them. Does anyone support their > programmable devices with free base development software? I don't need > anything more capable than PALASM. > > I have a second item on my wish list. I'd like to be able to reprogram > an FPGA on the fly. > Back when I had access to Xilinx tools, there still was no information > available to know which bits > did which functions. Best I could do was route it and load the > resultant secret patterns. > > What I really want is to define a few "architecture files" that define > the base FPGA configurations that could > be loaded into the FPGA configuration RAM. Then I need the capability > to reprogram polarities of nodes on the fly. I'll probably buy two > FPGAs, total, so there's not much use > in asking a vendor for something that's not already published. > > That's the problem with being retired. You lose access to all those > neat expensive hi-tech tools. > > Any ideas? > miker > -- > Return Address is Bogus. > TO REPLY CLICK BELOW. > http://www.ethergate.com/users/miker/index.html > Usually have stuff WANTED and FOR SALE. > If you get a URL error, try again later.Article: 8946
I am interested but in the Chicago area. I am interested in FPGA tools good enough to design 4K to 10K gate microprocessors, with possibly 128 bytes of internal RAM (not counting registers). I want to design a generic board so that different designs could be tried out against different classes of problems. I have no problem with board design but lack the $$$ required for the FPGA tools. Simon m-node@ix.netcom.com (mitchell) wrote: >Hello: > >I direct an entrepreneurial association known as The PARALLEL Processing >Connection. We meet monthly in Palo Alto (Sun Microsystems) CA. This >Monday's (February 9th) meeting will deal with a new compiler known as >C2Verilog. Please attend if you are able. > >We also have tools that were donated by various vendors ... Altera, etc. >for PPC member use at our lab/office in Sunnyvale CA. The point is, you >may only be using two FPGA's and therefore are not able to properly >influence vendors. However, we as an association have enough leverage for >various reasons to be able to better interact with the vendors than any of >us as individuals. For example, a while back, Altera donated about $12,000 >of hardware/software to PPC. > > >In article <34DD1F0E.74AAA61B@ethergate.com>, Don't, Hit, Reply, Use, the, >Link wrote: > >>I've been using PALASM and GAL20V8 for hobby projects. Don't need much >>more capability, just more >>of the same. Like a GAL32V128. >> >>The problem with FPGAs is that I can't find any affordable tools to >>program them. Does anyone support their >>programmable devices with free base development software? I don't need >>anything more capable than PALASM. >> >>I have a second item on my wish list. I'd like to be able to reprogram >>an FPGA on the fly. >>Back when I had access to Xilinx tools, there still was no information >>available to know which bits >>did which functions. Best I could do was route it and load the >>resultant secret patterns. >> >>What I really want is to define a few "architecture files" that define >>the base FPGA configurations that could >>be loaded into the FPGA configuration RAM. Then I need the capability >>to reprogram polarities of nodes on the fly. I'll probably buy two >>FPGAs, total, so there's not much use >>in asking a vendor for something that's not already published. >> >>That's the problem with being retired. You lose access to all those >>neat expensive hi-tech tools. >> >>Any ideas? >>miker >>-- >>Return Address is Bogus. >>TO REPLY CLICK BELOW. >>http://www.ethergate.com/users/miker/index.html >>Usually have stuff WANTED and FOR SALE. >>If you get a URL error, try again later. > >-- >B. Mitchell Loebel >CEO, Chief Technical Officer >MultiNode Microsystems Corporation 408 732-9869 > >Executive Director >The PARALLEL Processing Connection 408 732-9869 Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 8947
Also check out Altera's free PLS-WEB software - it allows design up to 10K gates. www.altera.com Regards, Steve.Article: 8948
"Adam J. Elbirt" <aelbirt@viewlogic.com> wrote: >Geir, > >What really matters in this case is whether or not the synthesis tool is >smart enough to take advantage of the element for your given design. Some >are, some aren't, and there are a lot of factors that come into play. >Typically, each tool has a variety of settings that result in the usage of >different library elements. A typical example is a resource sharing option >that would use an ADDSUB component when turned on and one each of ADD and >SUB components when turned off. For situations like these, you need to >examine your synthesis tool outputs and typically tweak the appropriate >settings to try and get what you want. Even then, you may have to resort >to schematics to implement EXACTLY what you want for optimal performance or >area utilization. > >Adam > It's not only whether it can use special elements of a particular FPGA, but also whether it's smart enough to minimize logic. When I checked out Alta Group's SPW and Synopsis's Behavioral, Altera's DSP Tools, and Exemplar, a couple of years ago, None of them correctly recognized that a constant multiply by 9 of an 8 bit number, should use a 9 bit adder to get the 12 bit result. Sure, they could be forced, kicking and screaming, to implement it this way, but schematics seemed far simpler. Schematic capture also provided an easy way to control the relative placement of the logic. this meant that I could build up libraries of minimized, preplaced DSP parts, for easy reuse. I'd rather spend 4 hours doing manual placement one time, than 40 hours of dubious automatic placement for every design change. I wonder if any of these tools have improved enough, in the last two years, that they would now instantiate a 9 bit adder, and permit me to graphically, hierarchally, edit the placement of this adder with respect to the registers on its input and/or output. Dave Decker Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 8949
>XMAKE does not check the dongle. WIR2XNF certainly does. I think this is incorrect. I think only APR/PPR/XACT check the dongle, on XACT6.01. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.
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