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Messages from 9100

Article: 9100
Subject: $3000 Cash!!!
From: "Karl Andersson" <fd@ddd.com>
Date: Fri, 20 Feb 1998 17:59:03 +0100
Links: << >>  << T >>  << A >>
Please contact us if can write a FPGA/ASIC Program (Verrrryyyyy High
Speeeeddd)
If you make it work, then you have made $3000 Cash!!!
contact: office@exelab.com

Regards
Per



Article: 9101
Subject: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 20 Feb 1998 17:15:08 GMT
Links: << >>  << T >>  << A >>
I believe the problem lies in Altera's introduction of timing
based optimization. 



In article <6ck9e3$aij$1@nnrp2.dejanews.com>,  <tim_kellis@ahh.com> wrote:
>I understand that there are problems with Altera's new release of its
>Max+Plus II software, version 8.2, that has severely impacted compile times. 
>Does anyone have any knowledge or experience with this software version.

>thanks

Tim
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/   Now offering spam-free web-based newsreading


Article: 9102
Subject: Re: buft and bufe
From: fliptron@netcom.com (Philip Freidin)
Date: Fri, 20 Feb 1998 21:12:27 GMT
Links: << >>  << T >>  << A >>
In article <01bd3df8$b69f0320$3433a8c0@java> "Frank" <xzf@usa.net> writes:
>Can anybody tell me what's the difference between BUFT and BUFE in Aldec
>Foundation Series software? I use it to do design with Xilinx device.
>

BUFT is tristate when the T pin is high, driving when it is low
BUFE is tristate when the T pin is low,  driving when it is high

Philip


Article: 9103
Subject: Re: buft and bufe
From: cls@wurzelausix.CS.Uni-SB.DE (Cedric Lichtenau)
Date: 20 Feb 1998 21:24:21 GMT
Links: << >>  << T >>  << A >>
In article <01bd3df8$b69f0320$3433a8c0@java>, Frank <xzf@usa.net> wrote:
>
>Can anybody tell me what's the difference between BUFT and BUFE in Aldec
>Foundation Series software? I use it to do design with Xilinx device.
>
BUFE has a active-High output enable Pin (E), and BUFT has a Tristate Pin (T)
i.e. active-Low output enable!
The difference between both drivers costs me one full day then... :+(

Cedric

-- 
--> Cedric Lichtenau, Chaos 11       Phone: +49 681-302-4490
    Universitaet des Saarlandes      Fax:   +49 681-302-4290
    Im Stadtwald                     Email: cls@cs.uni-sb.de
    66123 Saarbruecken               WWW:   http://www-wjp.cs.uni-sb.de/~cls
Article: 9104
Subject: Re: crossbar switch
From: Nancy Donahue <ndonahue@ma.ultranet.com>
Date: Fri, 20 Feb 1998 17:30:56 -0500
Links: << >>  << T >>  << A >>
Lattice has an in-system-programmable and in-system-configurable digital
cross point switch which also has registers and muxes embedded within,
so that virtually any bus functions can be emulated ('244s, '373s, etc).
The specs and appnotes, as well as the developement software are
available on our web page: www.latticesemi.com.

--
_/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/)
_/)

Nancy Donahue                        office: 781-279-3000
Field Applications Engineer          fax:    781-279-3730
Lattice Semiconductor                voice mail: 1-800-870-4270 x 623
41 Montvale Ave, Suite B75           email:
nancy_donahue@latticesemi.com
Stoneham, MA 02180                   web site: www.latticesemi.com

_/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/) _/)
_/)


Article: 9105
Subject: Re: System Gates and Logic Cells...
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 20 Feb 1998 14:56:00 -0800
Links: << >>  << T >>  << A >>

--------------B1BAC02D0AB6D9F4AA130E7C
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Peter wrote:

> This argument will go on forever.
> I recently did an ASIC, which was prototyped in a XC3090, and the FPGA
>
> was about 80% full (on the CLB count). But counting the gates in the
> XNF netlist yielded only about 2000 gates.

That is one extreme.Here is the opposite real-life extreme case:

I visited one of our major customers, and they had implemented a design
in an XC4010, for which Xilinx claims 10,000 gates.
They had tried to convert that design into a gate array, and found that
it required 50,000 gates, since the design uses reloadable look-up
tables all over the chip, and those get really expensive in a gate
array. They then stayed with the XC4010.

I don't claim that this is a normal situation, but it is real, and there
are more  such cases, where our gate claim is conservative by a factor
up to five. Obviously not in normal logic implementation, but rather in
DSP or other user-modifiable applications where the small LUTs are used
extensively.

Please, don't flame me !
I know that many designs achieve less than the stated gate count.

ASIC gates are an almost meaningless way

to measure the capacity of LUT-based FPGAs.

Peter Alfke, Xilinx Applications

--------------B1BAC02D0AB6D9F4AA130E7C
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<HTML>
<BODY BGCOLOR="#FFFFFF">
Peter wrote:
<BLOCKQUOTE TYPE=CITE>This argument will go on forever.
<BR>I recently did an ASIC, which was prototyped in a XC3090, and the FPGA
<BR>was about 80% full (on the CLB count). But counting the gates in the
<BR>XNF netlist yielded only about 2000 gates.</BLOCKQUOTE>
That is one extreme.Here is the opposite real-life extreme case:

<P>I visited one of our major customers, and they had implemented a design
in an XC4010, for which Xilinx claims 10,000 gates.
<BR>They had tried to convert that design into a gate array, and found
that it required 50,000 gates, since the design uses reloadable look-up
tables all over the chip, and those get really expensive in a gate array.
They then stayed with the XC4010.

<P>I don't claim that this is a normal situation, but it is real, and there
are more&nbsp; such cases, where our gate claim is conservative by a factor
up to five. Obviously not in normal logic implementation, but rather in
DSP or other user-modifiable applications where the small LUTs are used
extensively.

<P>Please, don't flame me !
<BR>I know that many designs achieve less than the stated gate count.
<H2>
ASIC gates are an almost meaningless way</H2>

<H2>
to measure the capacity of LUT-based FPGAs.</H2>


<P>Peter Alfke, Xilinx Applications
</BODY>
</HTML>

--------------B1BAC02D0AB6D9F4AA130E7C--

Article: 9106
Subject: Re: Why altera CPLDS are slow to power-up?
From: Isabelle Gonthier <igonthie@total.net>
Date: Fri, 20 Feb 1998 19:09:19 -0500
Links: << >>  << T >>  << A >>
waynet@pop.phnx.uswest.net wrote:
> 
> Okay...
> 
> Peter is just mad because his company is now the number TWO programmable
> logic supplier in the world.   I think Peter is an excellent resource for
> detailed Xilinx technical information; perhaps he should stick with his
> strengths...
> 
> Also, Peter, there may indeed be no guts on Orchard Parkway, considering
> Altera moved to 101 Innovation Drive some months ago.  You remember
> innovation, don't you?  Hint: think back before the XC5200 and XC9500
> families that looked curiously like Flex8000 and Max7000S...
> 
> Sorry to everyone for the non-technical post; I didn't take the first shot
> however.  I hope it was at least entertaining!
> 
> Wayne Turner
> Altera Field Applications
> (posting from home and speaking for myself)
> 
> Peter Alfke wrote:
> 
> > [snipped...]
> > It is sad that there is nobody at Altera willing to stick his head out.
> > Of course they are monitoring this newsgroup, but there's no guts on
> > Orchard Parkway...
> >
> > It's fun to needle somebody who is too afraid to come out of hiding, and
> > relies on being rescued, occasionally, from New Zealand...
> >
> > Peter Alfke, Xilinx Applications
Wayne,
	Funny you mention the 7000S comparing it to the 9500.  Xilinx had the
full 9500 family out before Altera could even ship any 7000S!!! If you
want to associate the XC5200 family to the Flex 8K, then why did Altera
come out with the Flex 6K to go up against the XC5200?????
Article: 9107
Subject: Re: Free FPGA tools???
From: jesse@onshore.com (Jesse Bouwman)
Date: 21 Feb 1998 00:26:47 GMT
Links: << >>  << T >>  << A >>
In article <34DD1F0E.74AAA61B@ethergate.com>, &miker wrote:

> The problem with FPGAs is that I can't find any affordable tools to
> program them.  Does anyone support their programmable devices with
> free base development software?  I don't need anything more capable
> than PALASM.

I've been having this problem too, the closest I've come to a solution
was to pick up a book called "VHDL for Programmable Logic" by Kevin
Skahill which includes a set of tools for Cypress parts. Anyways, that
was yesterday evening at about 9 pm, so I can't really vouch for it
yet and I'm new at this anyways. But the book was $48.50 with both
Sparc and PC versions of the software, and that's about the lowest I've 
seen for something to get started with. Not to mention that the text 
looks pretty good too. Hope that helps?

Jesse Bouwman


Article: 9108
Subject: Re: download cable for lattice ISP -> schematics
From: "Alexandre Pechev" <A.Pechev@rdg.ac.uk>
Date: Sat, 21 Feb 1998 10:37:56 -0000
Links: << >>  << T >>  << A >>

>Does anybody know where I can find
>information about it?



It can be found in Application Note 8003 which details "The Basics of
One-Wire ISP with an IrDA Example" (it's in AN8003.PDF).

You can find this AN on their site

I hope this helps

Alex


Article: 9109
Subject: Re: Free FPGA tools???
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 05:17:45 -0600
Links: << >>  << T >>  << A >>
There is some free stuff out there, I believe
http://www.optimagic.com
has a good listing of what is availible.  Also I note that there are many low $
solutions mentioned in the replies.  Most of them student additions that are part of
some book.  I am sure some of these are quite useful, I have used the Cypress book
the book is good.

For near the price of college text $95 one can get a copy of Foundation Base, this
is not a student edition, it includes support for all Xilinx (3K, 4K,5200 & 9500)
devices but the 6K series up to 4010s ( A rather large device).  The kit also comes
with an X-checker and parralle port down load cable. Unlike any other of the "free"
tools"  that I am aware of Foundation supports full timing simulation as well as
functional (Many free tools do functional) simulation.  A good deal at the price.

Nick Hartl
Yes I work for a Xilinx, Cypress distributor.
www.marshall.com

Edward Lee wrote:

> &miker wrote:
> >
> > Richard Schwarz wrote:
> >
> > > Miker,
> > >
> > > For $350.00 you can get the ...snip
> >
> > Thanks for the input.  I guess I should have explained the concept "free"
> > :-).What I meant was, no cost, without payment, provided gratis by the vendor,
> >
> ...
> >  The problem with FPGAs is that I can't find any affordable tools to
> >  program them.  Does anyone support their
> >  programmable devices with free base development software?  I don't need
> >  anything more capable than PALASM.
> >
> >  I have a second item on my wish list.  I'd like to be able to reprogram
> >  an FPGA on the fly.
> ...
> How about the AMD/Vantis Machxl 2.0?  You can download it free from
> AMD/Vantis.
> It's DOS based, but good enough for simple design.  It comes with lots
> of
> design reports and simulations.  You can program it ISP with a parallel
> port
> cable.  I tried out the software, but i have not actually programmed it
> yet.
> --
> Embedded Programming Lab
> http://www.glasscloth.com/epl
> epl@rocket_dot_com (_dot_ -> .)


Article: 9110
Subject: Re: Free FPGA tools???
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 05:18:20 -0600
Links: << >>  << T >>  << A >>
There is some free stuff out there, I believe
http://www.optimagic.com
has a good listing of what is availible.  Also I note that there are many low $
solutions mentioned in the replies.  Most of them student additions that are part of
some book.  I am sure some of these are quite useful, I have used the Cypress book
the book is good.

For near the price of college text $95 one can get a copy of Foundation Base, this
is not a student edition, it includes support for all Xilinx (3K, 4K,5200 & 9500)
devices but the 6K series up to 4010s ( A rather large device).  The kit also comes
with an X-checker and parralle port down load cable. Unlike any other of the "free"
tools"  that I am aware of Foundation supports full timing simulation as well as
functional (Many free tools do functional) simulation.  A good deal at the price.

Nick Hartl
Yes I work for a Xilinx, Cypress distributor.
www.marshall.com

Edward Lee wrote:

> &miker wrote:
> >
> > Richard Schwarz wrote:
> >
> > > Miker,
> > >
> > > For $350.00 you can get the ...snip
> >
> > Thanks for the input.  I guess I should have explained the concept "free"
> > :-).What I meant was, no cost, without payment, provided gratis by the vendor,
> >
> ...
> >  The problem with FPGAs is that I can't find any affordable tools to
> >  program them.  Does anyone support their
> >  programmable devices with free base development software?  I don't need
> >  anything more capable than PALASM.
> >
> >  I have a second item on my wish list.  I'd like to be able to reprogram
> >  an FPGA on the fly.
> ...
> How about the AMD/Vantis Machxl 2.0?  You can download it free from
> AMD/Vantis.
> It's DOS based, but good enough for simple design.  It comes with lots
> of
> design reports and simulations.  You can program it ISP with a parallel
> port
> cable.  I tried out the software, but i have not actually programmed it
> yet.
> --
> Embedded Programming Lab
> http://www.glasscloth.com/epl
> epl@rocket_dot_com (_dot_ -> .)


Article: 9111
Subject: Re: Xilinx download cable ??????
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 05:29:05 -0600
Links: << >>  << T >>  << A >>
Non-volatile programming download cable programming of Xilinx parts can
be done to the 95xx series CPLDs.  All the SRAM based parts can be
programmed with an X-checker or parallel down load cable but the
configuration is lost at power down.

THIEBOLT Francois wrote:

> Hi,
>
> Can someone tell me what are the FPGA Xilinx parts that could be
> programmed using a simple download cable (like lattice parts) ???
>
> Thanks for your help.
>
> Francois.
>
> --
> -------------------------------------------------------------
> THIEBOLT Francois \ You think your computer run too slow ?
> UPS Toulouse III  \ - Check nobody's asked for tea !
> thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
> -------------------------------------------------------------

Article: 9112
Subject: Re: System Gates and Logic Cells...
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 05:38:32 -0600
Links: << >>  << T >>  << A >>
Logic cells are a hard metic of device size.  One can count the exact
number of LCs in a device.  System level gates is a much more difficult
term.  What is a gate? 2 input NAND? If so how many of these are in a four
input LUT? Or a RAM?

System level gates are genrally given to provide some metric against full
up ASICs that are tratitionally measured in gates.  So if one fills up a
40125 and is wondering about how big an ASIC that would be, well one can
guess that it is about 500k gates.

Nick

M. Aberbour wrote:

> Hello,
>
> What is the difference between System Level Gates and Logic cells?
> These two terms are used widely by Xilinx in describing their products.
>
> Example:
> In their description of the XC40125XV products they say:
>
>      ## 10,982 to 20,102 logic cells (4-input look-up-table and
> flip-flop)
>      ## Up to 500,000 system level gates
>      ## Up to 448 user I/O pins
>      ## ...
>
> Thanks.
> --
>                                           ,,,
>                                          (o o)
> ####=================================oOO==(_)==OOO================####
> ##      _         |                                                 ##
> ##     (_)        | M. ABERBOUR                                     ##
> ##  _   _   ___   | Laboratoire LIP6 / Equipe CAO-VLSI              ##
> ## | | | | |   )  | Universite Pierre et Marie Curie (Paris 6)      ##
> ## | | | | | 6  ) | Couloir 55-65 2eme etage                        ##
> ## | | |_| |  _)  | 4, place Jussieu, 75252 Paris Cedex 05          ##
> ## | |___  | |    | Tel: (33) 1 44 27 71 24 Fax: (33) 1 44 27 72 80 ##
> ## |_____| |_|    | mailto:mourad.aberbour@lip6.fr                  ##
> ##                | http://asim.lip6.fr/~mourad/                    ##
> ####==============================================================####


Article: 9113
Subject: Re: XACT6 & ORCAD IV
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 05:49:43 -0600
Links: << >>  << T >>  << A >>
Lots of experience.  Did many designs using Orcad IV and XACT 6.0.  It
worked for me.  One must have the last version of the pre-386 Unified
libraries ( which as I remember where shipped with Orcad IV.  Did they
also come on the XACT 5 CD?  I forget.) to make it work. If Orcad does not
yell that the libraries are of incompatible types (i.e. 386 libs) you
should be fine.  (This is not a garantee! )

 I could go on about Orcad VST vs. Foundation but I won't. Except to say I
now use Foundation.

Have FUN!!
Nick

Krzysztof Rozniak wrote:

> I'd like to use Xilinx XACT 6 with old Orcad IV. I've found sources of
> SDT and VST unified libraries for XACT 5.0 (on CD) and compiled them
> without problems. But I wonder whether they are equivalent to original
> ones. Haven't checked it yet. Another problem is that Xilinx technical
> support says one should upgrade to OrCad 386+ as soon as possible,
> because the source files has not been thoroughly tested. It is
> impossible for me, at least for now. Has anyone experience with such
> configuration?
>
> Regards
> Chris
> --
> Christopher Rozniak
> Gdansk, Poland, Europe, Earth
> E-mail: k.rozniak@XXX.ien.gda.pl
> remove anty-spam XXX. to email



Article: 9114
Subject: Re: System Gates and Logic Cells...
From: z80@ds.com (Peter)
Date: Sat, 21 Feb 1998 16:08:20 GMT
Links: << >>  << T >>  << A >>

>That is one extreme.Here is the opposite real-life extreme case:
>
>I visited one of our major customers, and they had implemented a design
>in an XC4010, for which Xilinx claims 10,000 gates.
>They had tried to convert that design into a gate array, and found that
>it required 50,000 gates, since the design uses reloadable look-up
>tables all over the chip, and those get really expensive in a gate
>array. They then stayed with the XC4010.

My case was extreme because a 3090 gives poor utilisation for any
design with a lot of random logic; a 3090 has lots of CLBs but not
enough interconnect.

However I must say that even further down the range, down to a XC3042,
I was seeing a similar ratio. Basically the devices are poor at random
logic, e.g. muxes - one has lots of such stuff when building a
peripheral with readable+writeable registers. But everyone knows that
FPGAs are inefficient for random logic. It still amazes me how many
people think they can put a Z80 (etc) in an FPGA.

Yours was extreme presumably because the FPGA design was making use of
the RAM in various places, and the proposed ASIC version did not have
the distributed RAM option. But an ASIC *can* have distributed RAM. It
all depends on how much money one spends on it.

As I say, this goes on. FPGAs have their place, and ASICs have their
place.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 9115
Subject: Re: XACT6 & ORCAD IV
From: z80@ds.com (Peter)
Date: Sat, 21 Feb 1998 16:08:21 GMT
Links: << >>  << T >>  << A >>

>Lots of experience.  Did many designs using Orcad IV and XACT 6.0.  It
>worked for me.  One must have the last version of the pre-386 Unified
>libraries ( which as I remember where shipped with Orcad IV.  Did they
>also come on the XACT 5 CD?  I forget.) to make it work. If Orcad does not
>yell that the libraries are of incompatible types (i.e. 386 libs) you
>should be fine.  (This is not a garantee! )

Did you ever use SDT/386 with XACT6?

> I could go on about Orcad VST vs. Foundation but I won't. Except to say I
>now use Foundation.

I assume you are referring to the buggy VST. I don't have VST/386 but
wonder if this was any better.

The major reason why historically so many people have been using the
hugely expensive Viewlogic tools for FPGA work was the poor simulation
facilities in Orcad and similar programs. The schematic entry part is
perfectly OK for any project I have ever done.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 9116
Subject: Re: crossbar switch
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 21 Feb 1998 11:15:24 -0800
Links: << >>  << T >>  << A >>
I'm not sure if this is exactly what you're looking for but take a look at
the various vendors that supply Field Programmable InterConnect devices
(FPIC).  There's a list on The Programmable Logic Jump Station at
http://www.optimagic.com/companies.html#Interconnect .

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Mourad Khediri wrote in message <6cer8d$2d5$2@canard.ulcc.ac.uk>...
>hello,
>
>I wonder wether there is someone out there to help me.......!!!!
>
>I am doing a project on reconfigurable compiler for general purpose
>computing.... I need to find out more about the architecture of a cross-bar
>switch....... please help if you can!!!
>
>
>Thank you
>
>Mourad


Article: 9117
Subject: Re: Free FPGA tools???
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 21 Feb 1998 11:19:14 -0800
Links: << >>  << T >>  << A >>
We keep a mostly-complete listing of free and low-cost software packages for
programmable logic design on The Programmable Logic Jump Station.  See
http://www.optimagic.com/lowcost.html .

Also, a few people have mentioned the Xilinx and Altera student edition
books.  See http://www.optimagic.com/books.html for more information on
these publications.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Scott Campbell wrote in message <34EA49C3.234548C8@sbee.sunysb.edu>...
>Timothy Oconnell wrote:
>
>> In article <34DD1F0E.74AAA61B@ethergate.com>,
>> &miker  <Don't, Hit, Reply, Use, the, Link> wrote:
>> >
>> >The problem with FPGAs is that I can't find any affordable tools to
>> >program them.  Does anyone support their
>> >programmable devices with free base development software?  I don't need
>> >anything more capable than PALASM.
>> >
>>
>> I recently bought a book that included a CDROM with the student edition
>> of MAX+PLUS II 7.2 software from Altera.  The book wasn't exactly free
>> (~90$) but I know that Altera gives the software away to Universities.
>> I'm a strong believer in the Altera design environment.  This version can
>> only program the FLEX 10K20 and one other device but it's fully
>> functional in every other respect: full VHDL, AHDL, schematic entry,
>> simulation, timing, etc.
>>
>> If you want the book and publisher, let me know -- I don't have it with
me.
>>
>>                 Tim.
>>                 University of Cincinnati
>
>This is a good book and a good tool.  Look at the following URL
>for more information:
>
>http://www.altera.com/html/new/textbook.html
>
>Scott Campbell
>
>
>


Article: 9118
Subject: See What's New on The Programmable Logic Jump Station
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 21 Feb 1998 13:09:51 -0800
Links: << >>  << T >>  << A >>
There is new information on The Programmable Logic Jump Station!

               http://www.optimagic.com

The Programmable Logic Jump Station is a comprehensive set of
links to nearly all matters related to programmable logic.

Featuring:
---------
          --- Frequently-Asked Questions (FAQ) ---

Programmable Logic FAQ - http://www.optimagic.com/faq.html
A great resource for designers new to programmable logic.


          --- FPGAs, CPLDs, FPICs, etc. ---

Recent Developments - http://www.optimagic.com
Find out the latest news about programmable logic.

Device Vendors - http://www.optimagic.com/companies.html
FPGA, CPLD, SPLD, and FPIC manufacturers.

Device Summary - http://www.optimagic.com/summary.html
Who makes what and where to find out more.

Market Statistics - http://www.optimagic.com/market.html
Total high-density programmable logic sales and market share.


            --- Development Software ---

Free and Low-Cost Software - http://www.optimagic.com/lowcost.html
Free, downloadable demos and evaluation versions from all the major
suppliers.

Design Software - http://www.optimagic.com/software.html
Find the right tool for building your programmable logic design.

Synthesis Tutorials - http://www.optimagic.com/tutorials.html
How to use VHDL or Verilog.


              --- Related Topics ---

FPGA Boards - http://www.optimagic.com/boards.html
See the latest FPGA boards and reconfigurable computers.

Design Consultants - http://www.optimagic.com/consultants.html
Find a programmable logic expert in your area of the world.

Research Groups - http://www.optimagic.com/research.html
The latest developments from universities, industry, and
government R&D facilities covering FPGA and CPLD devices,
applications, and reconfigurable computing.

News Groups - http://www.optimagic.com/newsgroups.html
Information on useful newsgroups.

Related Conferences - http://www.optimagic.com/conferences.html
Conferences and seminars on programmable logic.

Information Search - http://www.optimagic.com/search.html
Pre-built queries for popular search engines plus other
information resources.

Related Books - http://www.optimagic.com/books.html
Books on programmable logic, VHDL, and Verilog.  Most can be
ordered on-line.

            . . . and much, much more.

Bookmark it today!




Article: 9119
Subject: ICCD Call for Papers
From: Andreas Kuehlmann <kuehl@eecs.berkeley.edu>
Date: Sat, 21 Feb 1998 19:28:32 -0800
Links: << >>  << T >>  << A >>
International Conference on Computer Design
                                   ICCD'98

                            October 5 - 7, 1998
                Marriott Hotel at the Capital, Austin, Texas

                                  Sponsored by:

           IEEE Computer Society and IEEE Circuits and Systems Society
               In Cooperation with: IEEE Electron Devices Society

                 http://domino.watson.ibm.com/iccd98/iccd98.nsf

-----------------------------------------------------------------------

                          ICCD '98 Call for Papers

The International Conference on Computer Design encompasses a wide range
of topics in the design and implementation of computer systems and their
components. ICCD's multi disciplinary emphasis provides an ideal
environment for developers and researchers to discuss practical and
theoretical work covering system and computer architecture, verification
and test, design and technology, and tools and methodologies. Authors
are invited to submit full technical papers no longer than 20 double
spaced pages describing original work in one of the following five
areas:

Integrated Systems
     Advances in system and technology integration, particularly for
     single-chip and MCM based systems; Embedded, networked and
     multimedia systems; Microelectronics for telecommunications and 
     multimedia; ASIC, Gate-array and FPGA architectures; Architectures, 
     design and test techniques for embedded systems including
     hardware/software partitioning and codesign, compilation and 
     performance evaluation; Communications subsystems; Network
     interfaces, protocols and applications.
Architecture and Algorithms
     Advanced computer architecture for general purpose and specialized
     processors, including signal, image, and multimedia processors;
     Architecture modeling and performance analysis; Computer
arithmetic;
     Architectural support for operating systems and languages; Memory
     hierarchy; Design and analysis of sequential and parallel
     algorithms, numerical methods, system design methods.
Design and Technology
     Design of digital, analog, mixed-signal and structured circuits;
     Circuit simulation; Design for optimal timing, noise, power, and
     layout; Silicon and non-silicon process technology trends and
     implications.
Verification and Test
     Simulation-based and formal techniques for functional design
     verification; Equivalence checking, model checking, theorem
proving;
     High-level design validation; Design error debug & diagnosis;
     Hardware/Software validation; Fault simulation and automatic test
     generation; Design for testability; Mixed signal test; Embedded
core
     testing; Quality and Reliability; Fault modeling; On-line testing.
Tools and Methodology
     Design methodologies for large systems; Concurrent engineering
     methodologies; Hardware description languages; CAD algorithms and 
     tools hardware-software codesign, high-level and logic synthesis,
     physical design, automatic analysis and optimization of timing,
     power, and noise; Integrated CAD systems.

Papers describing innovative features of new products, and focusing on
the overall integration of these areas into the computer design process
are of particular interest for ICCD. Some submissions will be accepted
as poster presentations. Proposals for specially organized sessions,
embedded tutorials, and panel discussions are also solicited. Awards
will be presented to the best conference papers in each technical
area. There is a limit of six (6) pages for the final publication of
accepted papers in the conference proceedings.

----------------------------------------------------------------------

Instructions to Authors:

For the first time, ICCD will support electronic submission of paper
manuscripts. Authors are strongly encouraged to use this
facility. Detailed instructions can be found on the ICCD web page at
http://domino.watson.ibm.com/iccd98/iccd98.nsf.

Schedule Information:

     - Submissions must be received by March 16, 1998
     - Notification of acceptance will be given on May 15, 1998
     - Final manuscript is due on July 15, 1998

-----------------------------------------------------------------------

ICCD'98 People:

- General Chair:
     Bing Sheu, University of Southern California, USA
- Technical Program Chair:
     Andreas Kuehlmann, IBM T. J. Watson Research Center, USA
- Integrated Systems Track Co-Chairs:
     Rajesh Gupta, University of California, Irvine, USA
     John Trotter, Lucent Bell Laboratories, USA
- Architecture and Algorithms Track Co-Chairs:
     Craig Chase, University of Texas at Austin, USA
     David Witt, Advanced Micro Devices, USA
- Design and Technology Track Co-Chairs:
     Sandip Kundu, Intel Corp., USA
     Sarma B. K. Vrudhula, University of Arizona, USA
- Verification and Test Track Co-Chairs:
     Warren A. Hunt, Jr., IBM Austin Research Laboratory, USA
     Wolfgang Kunz, University of Potsdam, Germany
- Tools and Methodology Track Co-Chairs:
     Joel Grodstein, Digital Equipment Corp., USA
     Kenneth L. Shepard, Columbia University, USA
Article: 9120
Subject: Re: XACT6 & ORCAD IV
From: Nick Hartl <nhartl@earthlink.net>
Date: Sat, 21 Feb 1998 22:13:26 -0600
Links: << >>  << T >>  << A >>


Peter wrote:

> >Lots of experience.  Did many designs using Orcad IV and XACT 6.0.  It
> >worked for me.  One must have the last version of the pre-386 Unified
> >libraries ( which as I remember where shipped with Orcad IV.  Did they
> >also come on the XACT 5 CD?  I forget.) to make it work. If Orcad does not
> >yell that the libraries are of incompatible types (i.e. 386 libs) you
> >should be fine.  (This is not a garantee! )
>
> Did you ever use SDT/386 with XACT6?
>
> > I could go on about Orcad VST vs. Foundation but I won't. Except to say I
> >now use Foundation.
>
> I assume you are referring to the buggy VST. I don't have VST/386 but
> wonder if this was any better.
>
> The major reason why historically so many people have been using the
> hugely expensive Viewlogic tools for FPGA work was the poor simulation
> facilities in Orcad and similar programs. The schematic entry part is
> perfectly OK for any project I have ever done.
>
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiXYZserve.com but
> remove the XYZ.

  Yes Orcad did ok in schematics once one had the macros down one could be
fast.

One of the things that caused me to leave Orcad though was that "tool' called
VST.
There have been few things put in a box and sold for money that were worth less
then that "tool".
Brown stuff that comes out of bulls maybe, but little else.

The Foundation simulator on the other hand is why I picked that tool in the
first place.  I started using
it when it was just Active-Cad no Xilinx deal had been done, bang for buck it
is the best I know of.
Though I must admit I am looking forward to the next major build of the
schematic tool......

Nick

Article: 9121
Subject: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
From: "Matthew Alan Kendall" <kendall.nospam@cti-pet.com>
Date: Sun, 22 Feb 1998 11:51:19 -0500
Links: << >>  << T >>  << A >>
>I understand that there are problems with Altera's new release of its
>Max+Plus II software, version 8.2, that has severely impacted compile
times.


Tim,

I upgraded to v8.2 from v8.14 last week.  All of my designs ( about 70% gdf,
and 30% HDL) compile, fit, and simulate just fine.  There is no appreciable
time difference whatsoever.

Matthew Alan Kendall



Article: 9122
Subject: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
From: mikeh@winnet-corp.com
Date: Sun, 22 Feb 1998 14:15:00 -0600
Links: << >>  << T >>  << A >>


We have noticed that a 80% full 10K50 which used to take
2 hours on Ver 8.14 now takes 12 hours on 8.2.

If anyone has any clues how to set the options to get the performance
back I would appreciate it.

Mike
mikeh@winnet-corp.com

In article <6cpl58$ph1$1@gaia.ns.utk.edu>,
  "Matthew Alan Kendall" <kendall.nospam@cti-pet.com> wrote:
>
> >I understand that there are problems with Altera's new release of its
> >Max+Plus II software, version 8.2, that has severely impacted compile
> times.
>
> Tim,
>
> I upgraded to v8.2 from v8.14 last week.  All of my designs ( about 70% gdf,
> and 30% HDL) compile, fit, and simulate just fine.  There is no appreciable
> time difference whatsoever.
>
> Matthew Alan Kendall
>
>


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9123
Subject: Advantech pc-uprog
From: rizzodav@tin.it (Davide Rizzo)
Date: Sun, 22 Feb 1998 23:36:35 GMT
Links: << >>  << T >>  << A >>
Hi, people
Can anybody say me where can I find some updated software for my
Advantech Pc-Uprog universal programmer ?
Thank you to all
rizzodav@tin.it

Article: 9124
Subject: Correlation implementation...
From: Erik Kobal <ekobal@now-online.com>
Date: Mon, 23 Feb 1998 00:48:00 GMT
Links: << >>  << T >>  << A >>
We are looking to implement signal arrival time detection using the
correlation method.  Our design involves a steady stream of 8-bit
samples at a sampling rate of 20 Msps.  Our pattern that we are
attempting to match is 40 samples wide.  Now the problem we have arrived
at is the following:  we need to perform a 40x8 bit matrix
multiplication.  This is only the root of our design problem, since our
application is multichannel.  We are not sure whether our design would
work best using a standard DSP, or whether we should use an FPGA to
allow for multiplication in parallel.  Any information would be much
appreciated.

Thank you,

Erik Kobal, Cleveland State University



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