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Messages from 9400

Article: 9400
Subject: Re: Whats wrong with this method
From: Mike Treseler <tres@tc.fluke.com>
Date: Mon, 09 Mar 1998 10:46:49 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E355E48E9765868A8A5B2896
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Content-Transfer-Encoding: 7bit

Allan Redenbaugh wrote:
> 
> Given the following code for a control register where a single bit has to
> have
> a seperate async reset :
> (target device = Xilinx 4ke)
> 
> process ( strobe, reset, clear_bit0)
> 
> begin
> if reset = '0' then
>    cntl_reg <= DEFAULT_REG;
> elsif clear_bit0 = '1' then
>    cntl_reg(0) <= DEFAULT_REG(0);
> elsif strobe'event and strobe = '1' then
>    cntl_reg <= data;
> end if;
> end process;
> 
> I assign reset to GSR so I expect clear_bit0 to drive the reset line of a
> dff
> on bit 0 and the reset of the register bit to only have the GSR reset.
> 
> My synthesis tool (Leonardo) says that since I have nothing defined for the
> upper bits under the clear_bit0 condition it defaults to a preset which is
> not what I inteded.
> 
> I have pulled out bit 0 into its own process and everythings happy, I just
> don't
> understand why this method doesn't work.
> 
> Any ideas?
> 
> Thanks,
> Allan Redenbaugh
> Raytheon Systems

Try this:

process ( strobe, reset, clear_bit0)
 
begin
if reset = '0' then                  -- reset
    cntl_reg <= DEFAULT_REG;         -- default
    if (clear_bit0 = '1') then
       cntl_reg <= DEFAULT_REG_ALT;  -- alternate default
    end if;                              
elsif strobe'event and strobe = '1' then
    cntl_reg <= data;
end if;
end process;

-- overwriting should be ok since evaluation is at the end
of the process
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--------------E355E48E9765868A8A5B2896--

Article: 9401
Subject: Re: The case for free operating systems and EDA
From: "rk" <stellare@erols.com.NOSPAM>
Date: 9 Mar 1998 20:30:52 GMT
Links: << >>  << T >>  << A >>
Wen-King Su <wen-king@myri.com> wrote in article
<6e17at$4at@neptune.myri.com>...
: In a previous article "rk" <stellare@erols.com.NOSPAM> writes:
: 
: :wen:
: ;:                    And only multicomputers of some sort can provide
that
: :scaling
: ;: of computing power required.
: :
: ;rk:
: :not sure i understand/agree here.  if one can run logic simulations (not
: ;timing, different story) on a multicomputer (pick your favorite type) to
: :scale simulation performance, how would this logically differ from
running
: ;on a quick-turn or rapid asic prototype?  
: :
: ;thanks for the info and discussion,
: 
: With those, you are limited by what the physical test environment can
: check.  If you verify your PCI design by plugging a protptype into the
: PCI bus of a machine you happen to have, for example, you will get a very
: inadequate test coverage.

perhaps my misconception; thought with quick-turn some access was provided
to internal nodes.  as for a rapid prototype, it would be a 'complement' to
other test vectors and would allow far greater numbers of vectors to be
applied for design verification and make the test design process easier and
making up the difference with brute force.  i generally work with the
smaller devices, moving up to bigger ones, still not the super-big ones. 
some guys in our group are shooting for some pretty big ones, it will be
interesting to see how it works out.

as for testing, having a rapid prototype run in a system at speed is a
plus, even at the 50,00 -100,00 gate level, in my opinion.  a prototype,
while not a design tool (and some use it for that, blew my stack at work
the other day over that one), and not the sole verification tool, is a
valuable verification tool.  generating the test cases is hard and, of
course, error-prone.  and while i have some experience with pci, there are
some very good bus testers out there that pretty thoroughly run a design
around, again making a nice complement to simulations.  and, of course, see
my .sig at the bottom.

saw an interesting statistic today, for fpga designs, 50% are 8,000 gates
or more.  of course, the 8,000 gater is a popular size, so we can say that
> 50% of fpga designs are 8,000 gates or less.  this is quite different
than your application.  but a dos or a win or a linux pc environment can
work quite well and does.  for linux, though, need a good reason to switch
from win.  of course, loading new viewlogic on work 'puter today, makes one
think. ;)  (yeah, they did it to me again).

have a nice day!
 
--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------
 
Article: 9402
Subject: PDS,VHDL or ViewLogic SCH for Intel's 82C54
From: Romanovsky Sergey <rom@romserg.kiev.ua>
Date: Mon, 09 Mar 1998 20:41:30 -0800
Links: << >>  << T >>  << A >>
If anybody knows where I can take free
Intel 82C54 VHDL,PDS or ViewLogic sch,
please, answer.
Thanks.
Article: 9403
Subject: Re: LARGE SELECTION OF FPGA BOARDS & KITS
From: disappointed <never_again@that.com>
Date: Mon, 09 Mar 1998 21:39:37 -0800
Links: << >>  << T >>  << A >>
Never picks up the phone, doesn't ship products on time, doesn't offer
shipping refunds when shipments are late... why do business with APS?
Article: 9404
Subject: Re: The case for free operating systems and EDA
From: Rick Kwan <"rkwan"@lightsaber . c o m>
Date: Mon, 09 Mar 1998 22:40:33 -0800
Links: << >>  << T >>  << A >>
rk wrote:
> 
> misha:
> : There is a significant advantage of Linux over Windows concerning
> portables.
> : I was very surprised when I touched the processor inside my desktop when
> : it was running Linux. It was COLD. So was the power regulator. Under
> : Windows95 the processor is always hot, even when OSR2 System Monitor
> shows 1%
> : CPU utilisation for an hour. Same about NT.
> :
> : Of course, when CPU-intensive application runs under Linux, the processor
> : warms up. But for typing text on the portable Linux should give much
> longer
> : battery life.
> 
> interesting.  i haven't seen any of the rags that report on portables and
> battery life consider this.  it would make a good benchmark since a lot of
> people do x-country traveling.  now, the portables do have a lot of power
> savings features and do a bunch of stuff to extend battery life so the
> difference on the desktop pc may not equal difference on a lapdog.  but it
> would be interesting to see, for a portable, a comparison for running a
> simple text editor between:
> 

....snipped list...

Me again.  (thot I would give a rest for a while... :-)

I did see this effect written up about one or two years ago
in the "Linux Journal."  I thought that by now, commercial OS
vendors would have caught on.  As I recall, the article actually
measured temperature of the chip, and yes, it was significantly
cooler when running Linux (although I don't remember the word
"COLD" per se.)

Apparantly, Linux actually halts the CPU and waits for an interrupt
to revive it, while other operating systems wait on spinlocks.

(Now, if could only get my fan to go off when it isn't needed,
I'd have a really quiet and environmentally friendly machine!)

--Rick Kwan
Article: 9405
Subject: Re: The case for free operating systems and EDA
From: "rk" <stellare@erols.com.NOSPAM>
Date: 10 Mar 1998 14:23:02 GMT
Links: << >>  << T >>  << A >>
rick kwan:
: Apparantly, Linux actually halts the CPU and waits for an interrupt
: to revive it, while other operating systems wait on spinlocks.

rk:
and just how does it run the screen saver? ;)

rick kwan:
: 
: (Now, if could only get my fan to go off when it isn't needed,
: I'd have a really quiet and environmentally friendly machine!)

rk:
new pentium ii's have some sma
-- 
--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------rts built
into them.  not sure if it controls the fan, but i know it has a temp
sensor on the chip, can slow down clock freq. if it gets too hot.  i'll
look into fan control, lots of settings in the bios.

Article: 9406
Subject: ISPD-98 Advance Registration deadline !!TODAY!! (3/10)
From: ispd98@ee.iastate.edu (Symposium 98 Acct)
Date: 10 Mar 1998 17:51:51 GMT
Links: << >>  << T >>  << A >>
	INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN 1998
		   Embassy Suites, Monterey, CA
			  April 6-8, 1998

		 http://www.ee.iastate.edu/~ispd98

	***************************************************
	        ** HOTEL RESERVATION DEADLINE: Mar 9 **
	       ** Early registration deadline: Mar 10 **
	***************************************************

			  ADVANCE PROGRAM

The International Symposium on Physical Design provides a high-quality forum
for the exchange of ideas and results in critical areas related to the physical
design of VLSI systems.  This meeting evolved from the ACM/SIGDA Physical
Design Workshops held during the years 1987-1996. The first Symposium in 1997
was highly successful and drew such a large number of attendees that
registration had to be closed a month early. The scope of this symposium
includes all aspects of physical design, from interactions with behavior- and
logic-level synthesis, to back-end performance analysis and verification. 



				MONDAY, April 6


0915-0930       Welcome
			M. Sarrafzadeh, General Chair (Northwestern)
			D. F. Wong, Program Chair (UT-Austin)

0930-1030       Keynote Address 
		"Perspectives on Systems at 1 GHz and beyond"
		Dave LaPotin (IBM Austin Research Laboratory)

1030-1100       BREAK

1100-1230       Session 1:   Floorplanning and Placement
		Chairs: C.K. Cheng (UCSD) and Jochen Jess (Eindhoven)

		"On Wirelength Estimations for Row-Based Placement"
			A.B. Kahng, S. Mantik, I.L. Markov, A. Zelikovsky (UCLA)
		"Performance-Driven Soft-Macro Clustering and Placement by 
		 Preserving HDL Design Hierarchy"
			H.-P. Su, A.C.-.H. Wu, Y.-L. Lin (Tsing Hua)
		"Nostradamus: A Floorplanner of Uncertain Design"
			K. Bazargan, S. Kim, M. Sarrafzadeh (Northwestern)

 
1230-1430       Lunch (Pinot Noir Room)
                Special Address: "Impact of Web Technologies on EDA System
		Architectures"
			A. R. Newton (UCB)

1430-1600       Tutorial: "Timing Metrics for Physical Design of Deep
		Submicron Technologies " 
		Presenter:  L. Pileggi (CMU)
		Panelists:  J. Cong (UCLA)
			    S. Otto (Intel)
			    A. Yang (Washington)

1600-1630       BREAK

1630-1730	Special Address: "Moore's Law and Physical Design of ICs"
		  W. Maly (CMU) 

1730-1830       Session 2:   Interconnect Optimization
		Chairs: M. Alexander (Washington State) and
						Y.-L. Lin (Tsing Hua)

  		"Greedy Wire-Sizing is Linear Time"
			C.C.N. Chu, D.F. Wong (UT-Austin)
    		"An Efficient Technique for Device and Interconnect 
		 Optimization in Deep Submicron Designs"
			J. Cong, L. He (UCLA)

1900-2100       Dinner (Pinot Noir Room)
                Special Address:
		"Consorting with the Consortia: Cooperative Research
					 For Fun and Profit"
  		W. H. Joyner (SRC)
                   


				TUESDAY, April 7


0830-0930       Session 3:   Layout Methodologies for RF Circuits 
		Chairs:  M. Pedram (USC) and W. Dai (UCSC)

		"Device-Level Early Floorplanning Algorithms for RF Circuits"
			M. Aktuna, R.A. Rutenbar, L. R. Carley	(CMU)
		"A Layout Approach to Monolithic Microwave IC"
			A. Nagao, T. Kambe (SHARP); I. Shirakawa (Osaka)


0930-1030	Session 4: Framework and Benchmarks
		Chairs: D. Hill (Synopsys) and L. Jones (Motorola)

		"CHDStd--Application Support for Reusable Hierarchical
		 Interconnect Timing Views"
			S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, 
                        A. Chokhavtia (Sematech); D. Cottrell, D. Mallis
			(Silicon Integration Initiative); S. DasGupta,
			J. Morrell (IBM)
		"The ISPD Circuit Benchmark Suite"
			C.J. Alpert (IBM)
		

1030-1100       BREAK
1100-1230       Panel: "Given that SEMATECH is levelling the semiconductor
	                technology playing field, will corporate CAD (in
	                particular, PD) tools be an enabler/
	                differentiator of technology in the future?"
		Organizer: S. DasGupta (IBM)
		Panelists:
		B. Beers, IBM
		M. Khaira, Intel
		R. Abrishami, Fujitsu Microelectronics
		J. Hutt, Synopsys
		L. Scheffer, Cadence
		D. Guiou, Mentor Graphics
		V. Kulkarni, Avant!

  
1230-1330       Lunch (Atrium Court)

1330-1430       Session 5:  "PD for Manufacturability" 
		Chairs: M. Wiesel (Intel), R. Rutenbar (CMU)
		"Critical Area Computation--A New Approach"
			E. Papadopoulou (IBM), D.T. Lee (Northwestern)
		"Filling and Slotting: Analysis and Algorithms"
			G. Robins, A. Singh (Virginia); H. Wang (UCLA);
			A. Zelikovsky (Virginia)


1430-1530	Special Address: "Global Wires: Harmful?"
		R. Otten (Delft)

1530-1600	BREAK

1600-1645       Session 6: Poster Presentations 
		Chairs: S. Sapatnekar (Minnesota) and G. Robins (Virginia)
	
		"Partioning Using Second-Order Information and Stochastic-Gain
		 Functions"
			S. Dutt (UIC), H. Theny (Intel)
		"A Parallel Algorithm for Zero Skew Clock Tree Routing"
			Z. Xing, P. Banerjee (Northwestern)
		"On Convex Formulation of the Floorplan Area Minimization
			Problem"
			T. Chen, M. Fan (Georgia Tech)
		"A Pattern Matching Algorithm for Verification and Analysis 
		 of Very Large IC Layouts"
			M. Niewczas, W. Maly, A. Strojwas (CMU)
		"LIBRA--A Library-Independent Framework for Post-Layout
		 Performance Optimization"
			R. Huang (UCSB), Y. Wang (Avant!), K.-T. Cheng (UCSB)
		"Estimation of Maximum Current Envelope for Power Bus 
		 Analysis and Design"
			S. Bobba, I.N. Hajj (UIUC)
       		"New Efficient Algorithms for Computing	Effective Capacitance"
			S. Muddu (SGI)
		"Calculation of Ramp Response of Lossy 	Transmission Lines Using
		 Two-Port Network Functions"
			P. Heydari, M. Pedram (USC)
		"Switch-Matrix Architecture and Routing for FPDs"
			G.-M. Wu, Y.-W. Chang (Chiao-Tung)

1645-1745       Poster Session


1900-2200       Banquet (Rancho Canada Golf Club)




				WEDNESDAY, April 8


0830-1000       Session 7: Efficient Representation in Placement 
		Chairs: R. Otten (Delft) and C. Sechen (Washington)

		"Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed
		  Modules"
			H. Murata, E.S. Kuh (UCB)
		"Rectilinear Block Placement using Permutation-Pair"
			J. Xu, C.K. Cheng (UCSD)
		"Topology Constrained Rectilinear Block Packing for Layout
		Reuse"
			M. Kang, W. Dai (UCSC)


1000-1030       BREAK

1030-1200       Panel:  "Process development and its impact on Physical Design"
	   	Moderator: N. Sherwani (Intel)
	   	Panel members: J. Cong (UCLA)
			       D. Lapotin (IBM)
			       J. Rey (Cadence)

1230-1400       Lunch (Pinot Noir Room)

1400-1530      	Tutorial: "Why Clustering is the Key to Partitioning"
		Presenter: A. Kahng (UCLA)
		Panelists: C. Alpert (IBM)
			   G. Janac (Cadence)
			   J. Lillis (UIC)

1530-1700	Session 8: Routing Algorithms
		Chairs: J. Cong (UCLA) and J. Fishburn (Lucent)

		"Chip-Level Area Routing"
			L.-C. Liu, H.-P. Tseng, C. Sechen (Washington)
		"Routing Tree Topology Construction to Meet Interconnect
		 Timing Constraints"
			H. Hou (Iowa State), S. Sapatnekar (Minnesota)
		"Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips"
    			T. Stoehr, M. Alt (IBM); A. Hetzel (Bonn), J. Koehl (IBM)

1700            Symposium Closes

%%==========================================================================%%
%%                          Symposium Organization                          %%
%%==========================================================================%%

General Chair
       M. Sarrafzadeh (Northwestern) 
Past Chair
       A. B. Kahng (UCLA) 
Steering Committee
       J. P. Cohoon (Virginia) 
       S. DasGupta (IBM) 
       M. Marek-Sadowska (UC Santa Barbara) 
       B. Preas (Xerox PARC) 
       E. Yoffa (IBM) 
Technical Program Chair
       D. F. Wong (UT-Austin) 
Technical Program Committee
       M. J. Alexander (Washington State) 	C. K. Cheng (UC San Diego) 
       J. Cong (UCLA) 				W. W.-M Dai (UC Santa Cruz) 
       J. Fishburn (Lucent) 			D. Hill (Synopsys) 
       J. A. G. Jess (Eindhoven) 		L. Jones (Motorola) 
       S. M. Kang (UIUC) 			Y.-L. Lin (Tsing Hua) 
       M. Pedram (USC) 				R. Rutenbar (CMU) 
       C. Sechen (Washington) 			M. Wiesel (Intel) 
       T. Yoshimura (NEC) 
Publication Chair
       D. Hill (Synopsys) 
Panel Chair
       N. Sherwani (Intel) 
Local Arrangements Chair
       R.-S. Tsay (Axis Systems) 
Publicity Chair
       S. Sapatnekar (Minnesota) 
Treasurer
       S. Souvannavong 

Sponsors
       ACM Special Interest Group on Design Automation
       in cooperation with 
       IEEE Circuits and Systems Society and IEEE Computer Society 

Additional Support From:
   Avant! Corporation 
   Ambit Design Systems
   Cadence Design Systems
   Mentor Graphics
   Synopsys

%%==========================================================================%%
%%                   Hotel Accommodations and Travel                        %%
%%==========================================================================%%

ISPD-98 is being held at the Embassy Suites Monterey Bay in Monterey,
California, located on the beautiful Monterey Peninsula, two blocks from
the beach, at the intersection of Canyon Del Rey and Del Monte Boulevard.
The address is
	Embassy Suites Monterey Bay Hotel & Conference Center
	1441 Canyon Del Rey
	Seaside, California 93955
	Tel: (408) 393 1115
	Fax: (408) 393 1113
For hotel reservations, call (408) 393 1115 or (800)362 2779.

A block of rooms is being held for the nights of Sunday through Wednesday 
(April 5 through April 8).  Room rates are $125 per night for a single room
and $145 per night for a double room.  Any individual cancellations within 72
hours from the date of arrival will be billed for (1) night's stay, plus tax.

        +---------------------------------------------------------+
        |  Please make room reservations directly with the hotel  |
        |  at either 1-408-393-1115 or 1-800-362-2779, mentioning |
        |  ``ISPD'' to get the special rate.                      |
        +---------------------------------------------------------+

The number of rooms available at this rate is limited, and are only being 
held through March 9. Early room reservation is highly recommended.  

%%==========================================================================%%
%%                   ISPD-98 Advance Registration Form                      %%
%%==========================================================================%%

Name: _______________________________________________________

Company/University: _________________________________________

Responsibility/Title: _______________________________________

Address: ____________________________________________________

City: _______________________________ State: ________________

Country: ______________________ Postal Code: ________________

Phone: ________________________ Fax: ________________________

Email: ______________________________________________________

Food Choices:
      [  ] Vegetarian meals
      [  ] Non-vegetarian meals
      [  ] Either one is fine

                        Advance               Late 
                   (Through March 10)    (After March 10) 
ACM/IEEE Members       [  ]   $350           [  ] $425 
Non-Members            [  ]   $425           [  ] $500 
Full-Time Students     [  ]   $175           [  ] $225

Student ID is required if registering as a student.

ACM or IEEE Member No. _____________________________

Registration fee includes meals and Banquet.  The Banquet will be held at
the Rancho Can~ada Golf Club and ISPD will provide a bus service to the site.

Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/International Symposium on 
Physical Design''.  Payment may also be made with credit card (circle): 

         Mastercard             Visa             American Express 

Credit Card # _______________________________________________

Expiration Date: ______________ Total Payment: ______________

Name as it appears on credit card: __________________________

Signature: ___________________________ Date: ________________

Please mail or FAX (credit card only) your completed registration form to:

   ISPD-98 Symposium Registration 
   Sally Souvannavong, Treasurer 
   P.O. Box 395 
   Pullman, WA 99163-0395 
   
   FAX: 1-509-332-6118 

Email registration will not be accepted.  Cancellations must be in writing 
and must be received by March 24, 1998.  Questions concerning symposium 
registration should be directed to Sally Souvannavong at 1-509-334-3162, 
Email: ispd98@eecs.wsu.edu. 

Article: 9407
Subject: Digital FPGA Digital Designer opportunities => AZ
From: "Hi Tech Jobs" <clientserver@msn.com>
Date: Tue, 10 Mar 1998 10:10:00 -0800
Links: << >>  << T >>  << A >>
Princeton Information < www.princetoninformation.com > is seeking
Ten (10) Senior Digital Design Engineers............

Digital FPGA Hardware Engineer -High Speed Digital Modem Technology

Job Description:

You will participate in the design and development of a flexible
communications system breadboard utilizing FPGA's (ASIC) for
Motorola's Celestri (tm) Modem Technology development program.
These are specialized high-speed modems (Mbps) installed in satellites.

Celestri is a multi-year, $13 billion project that will provide
high-bandwidth
packet switching - connections (e.g., internet) in outer SPACE!!!

Celestial Data Communications for the 21st Century!!!

BS/MS in Electrical Engineering +4 to 6 years of experience required.
Familiarity with FPGA based design limitations and mitigation methods.
Willingness to accept responsibility & technical challenge
Ability to work independently and on a team
Focus on customer satisfaction

Location:  Phoenix/ Chandler,  AZ
Duration:  Full Time Salary and Temp to Permanent or out right contracting
Pay Rate: Open

See our Website: < www.princetoninformation.com >

Email your resume TODAY!!! => < clientserver@msn.com >

Princeton Information
1201 South Alma School #1125
Mesa, Arizona  85210
(602) 655-7600


























Article: 9408
Subject: Re: The case for Linux and EDA
From: yankee <yankee@yankee.com>
Date: Tue, 10 Mar 1998 13:06:55 -0600
Links: << >>  << T >>  << A >>
> Michael McNamara wrote:
  
>         But your theory assumes completely elastic demand.
> 
>         Something like 10% of Unix boxes (my guess) are used to run
> EDA tools. I will go out on a limb here: No matter how many quality
> EDA tools are ported to the intel platform (Linux or Win/NT), and no
> matter how low the price, you will see far less than 1/100 of 1% of
> the total number of PC's that will ever run EDA software.
> 

I have NO idea where you came up with that statistic. Are you in a cave?
>From where I sit, I can see a bank of PC workstations running Workview,
OrCad, MaxPlus, PSpice, etc. All indications are (and of the companies
that I visit) that the days of overpriced UNIX boxes are numbered. 


>         So, vendor XYZ figures they can sell 100 copies of their
> combination simulator, synthesis and place & route tool on UNIX in one
> year. They can change $100k for the package; so $10M total sales!
> 
>         Now if they port to the PC, and hence cut the price to $10k
> for the package, can they sell 1000 copies? Sorry, no. They may be
> able to sell 200 copies.. and hence only do $2M in sales.
 
Please explain your logic. My fellow engineers and I are baffled. I'm
assuming that you have some line of reasoning for these statistics, but
it's not obvious to us at all.
Article: 9409
Subject: Re: The case for Linux and EDA
From: "rk" <stellare@erols.com.NOSPAM>
Date: 10 Mar 1998 21:31:06 GMT
Links: << >>  << T >>  << A >>
mike: 

: 	Great theroy; and it applies quite well to word processors,
: spreadsheets and the like. 
: 
: 	But your theory assumes completely elastic demand. 

rk:
nope, not completely elastic.

mike: 
: 	Something like 10% of Unix boxes (my guess) are used to run
: EDA tools. I will go out on a limb here: No matter how many quality
: EDA tools are ported to the intel platform (Linux or Win/NT), and no
: matter how low the price, you will see far less than 1/100 of 1% of
: the total number of PC's that will ever run EDA software.

rk:
it would be interesting to know how many unix boxes and pc's have been sold
in the last three years; dunno the answer.  but one out of ten thousand is
a large number for pc's which have a huge volume.

mike: 
: 	So, vendor XYZ figures they can sell 100 copies of their
: combination simulator, synthesis and place & route tool on UNIX in one
: year. They can change $100k for the package; so $10M total sales! 
: 
: 	Now if they port to the PC, and hence cut the price to $10k
: for the package, can they sell 1000 copies? Sorry, no. They may be
: able to sell 200 copies.. and hence only do $2M in sales.
: 
: 	That is the problem.

rk:
first, practically speaking, if you have to spend $100k for a piece of s/w
(and then, say $15k a year for "maintenance") you will get a lot of people
who will just not do that.  and if they do, they will share the license,
huddled over a group of workstations in a "cae room" earmarked for this
purpose.  saw this model in '80s.  see this model in '90s.  and i'll give
you a hint, more than two people will be sharing that license.  and each
purchase will be carefully done.

if the software is very inexpensive then each engineer will get a copy to
run on his desktop.  save $, don't need extra computers (and the more
expensive unix ones).  don't need to find "cae room"  as space always seems
to be critical.  don't have to have those sign-up sheets which pop up from
time to time, every few years.

currently, at day job, i'm evaluating some new synthesizers to replace what
we have now, get more "quality of results," faster execution times, etc. 
but we all looked at the price tag.  our team would be able to afford, at
most, one copy.  if we could convince the boss to pay up the large amount
($40K per floating license) vs. our inexpensive tool, for this operation,
which was about $2k.  easy tradeoff.  everybody gets a copy on his desk for
the $2k since it will do the job good enough (and, ironically, easier to
run with adequate controls and less surprises - but it does have less
flexibility).  that's what happening on the win systems, a variety of
systems with differing capabilities with differing prices.  a market-driven
environment, to a certain extent.  and it won't let companies sit on their
butts, selling the same stuff for high prices year after year.  i see the
ambit ads, don't know what they charge, but they're slamming synopsys in
them.  very agressive.  they want business. and they can get it in two
ways: take away synopsys customers for price/performance/standards reasons
or be low enough in price to get other people into the business or just
sell multiple seats to make a better engineering environment.  perhaps
someone with some good info on ambit can comment.

the s/w market, whether for word processors or eda tools is non-linear, in
my opinion, and here's why i think so.  please comment.

moving a piece of s/w from unix to win or linux will save some $ but by
itself will do little and be a losing proposition if you intend to grow
volume and make more $ for a high-end tool.  the pc on the desk is, for
most companies a reality and will save costs in training, box maintenance,
etc.  but if you have, say, a $95,000 piece of s/w the number of licenses
bought will depend on how many people really need it and will tend to be
centralized and carefully thought out and optimized for the license, not
the engineer.  convenience for the engineer, who wants to work on his desk
top or in the lab, will be secondary.  now linux fans or people who travel
and need to carry their cpu cycles with them will mostly likely migrate
from unix to pc (linux or win) - zero net win there (pun intended).

lower cost s/w will have say more users but perhaps less total revenue. 
not as bad as you estimate, i would 'guess', but the principle is correct,
to a point.  for $2k, say, each engineer gets a copy on his desk, no
thought there.  sort of like buying pencils in the corporate environment. 
tool of the job.  $95k, that doesn't happen.  in between price, in between
sales.

but, when the cost gets low enough, people who would normally not even buy
the tools would get a set, EXPANDING the market.  that's what's happening
in fpgas now.  entry into the field is getting to be lower and lower cost. 
and the number of 'seats' seems to be expanding, based on personal
observations.  not just re-distributing expensive seats to cheaper ones. 
and that is the same principle as pc's and word processors.  for $4,000 or
so w/ no s/w and little performance (say mid-80s) to $1000 to $2000 for a
quite capable pc w/ lots of s/w, the market has exploded.  people who would
think that it would be nice to have a pc can now just go down to the kmart
or staples or circuit city or price club or local hole in the wall 'puter
shop and get one. and with a lot of demand, there is more competition, as
people want a bigger chunck of that pie.

same with eda.  you can get into eda for just a few k $.  and a lot of
vendors are giving away their software for free or just a few hundred
dollars, s/w that used to cost thousands.  and it's better and more capable
than before.  but there are a lot more users now.  that's not me talking,
that's the market and what's going on.

of course, i can sit here on my home pc with a moderate investment for a
small business and design chips and boards that are quite capable. 
couldn't do that 10 years ago and will not do that with $95,000 s/w no
matter whether it's unix or linux or win or dos or exec 8 or vms or mvs or
domain or whatever - this decision has absolutely nothing to do the os;
strictly price.  for a reasonable investment, this seat, and many others,
was created.

now, looking at day-job corporate environment, almost every design engineer
has some eda on his desktop.  most of these are win machines, shared with
typical office or laboratory tasks.  some are unix.  as s/w gets to be
better and cheaper sales go way up.  

moving a $95,000 piece of s/w to any os of favor doesn't really matter, few
will buy it that haven't already invested.


Article: 9410
Subject: Re: The case for Linux and EDA
From: Zoltan Kocsi <root@127.0.0.1>
Date: 11 Mar 1998 17:47:00 +1100
Links: << >>  << T >>  << A >>
"rk" <stellare@erols.com.NOSPAM> writes:

> systems with differing capabilities with differing prices.  a market-driven
> environment, to a certain extent.  and it won't let companies sit on their
> butts, selling the same stuff for high prices year after year.  i see the
> ambit ads, don't know what they charge, but they're slamming synopsys in
> them.  very agressive.  they want business. and they can get it in two
> ways: take away synopsys customers for price/performance/standards reasons
> or be low enough in price to get other people into the business or just
> sell multiple seats to make a better engineering environment.  perhaps
> someone with some good info on ambit can comment.

Hm. You can take a look at Symplicity's stuff. You can buy their synthesis 
for HP or Sun at AU$24k + 1 year compulsory maintenance. You can buy the
exact same thing for Win AU$12k apiece (no contract). 
Why ?

On the lower end:
Actel's tools (VHDL synthesis and P&R) for Sun: AU$3.4k 
For Win: AU$1.7k (or free from the net with limited choice of chips).

Or you can see Quicklogic:

Sun: AUD$3k contains P&R
Win: AUD$3k contains P&R, verilog simulator, editor and the Symplicity 
                     synthesis (verilog/VHDL).
					 
Motorola P&R for Win is free (they even send you the CD for free), for 
Sun it is not.

AFAIK others are not much different either.

Knowing that most of these tools are made under unix then ported to
Win I can't really see the reason for pricing the Win tools way 
below the unix ones unless Mr. Gates offers some compensation (I'm 
not accusing, I'm just wondering ...)

As for having a cheap engineering platform then Linux is just as adequate
as Win - it is even cheaper and more stable. In addition porting unix SW 
to Linux is uncomparably simpler than to Win. Still, Linux is not on the
EDA palette yet. 

Can you explain that ?

Zoltan

-- 
+------------------------------------------------------------------+
| Reply address antispammed. Use ZOLTAN-at-BENDOR-dot-COM-dot-AU   |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 9411
Subject: Re: Whats wrong with this method
From: Pierre Ragon <ragon@lucent.com>
Date: Wed, 11 Mar 1998 10:45:13 +0100
Links: << >>  << T >>  << A >>
There is nothing wrong.
The code is synthesizable.
Yet the behavior it describes is not so obvious.Assuming that
DEFAULT_REG is a constant,
IF reset = '1' and clear_bit0 = '1' then
cntl_reg(0) is set or reset depending on the value of DEFAULT_REG(0),
whereas cntl_reg(n DOWNTO 1) keeps its previous value no matter if a
clock edge occurs or not.

This is different of what could be achieved using a process of its own
for bit 0.
In this case,the process describing the upper bits behavior needs not
be triggered by clear_bit0 nor the elsif clear_bit0 = '1' condition
needs to be tested.
AS a consequence if reset = '1' and clear_bit0 = '1' and a clock edge
occurs the upper bits of cntl_reg gets a new value which is the value
of the corresponding upper bits of data.

Pierre RAGON
Lucent Technologies
Article: 9412
Subject: Xilinx M1.4 tools on DEC Alpha based NT PCs ?
From: JM <jm@nospam.net>
Date: Wed, 11 Mar 1998 11:31:45 -0500
Links: << >>  << T >>  << A >>
Hi,
    Was wondering if Xilinx has a DEC Alpha - based native M1.4 tools?
Running it on Intel Pentium II at 266Mhz with 256 MB memory takes
approx. 3-4 hrs for a XC4028ex based design. A DEC-Alpha based tool
would seriously cut down the run-time.
Just a suggestion while I wait for the tools to finish :-)


Article: 9413
Subject: Announcing: Open Design Circuits
From: reinoud@smaug.et.tudelft.nl (R. Lamberts)
Date: 11 Mar 1998 16:54:03 GMT
Links: << >>  << T >>  << A >>

We have set up a new web site and mailing list about a low cost open
development model for integrated circuits (chips:).  This development
model removes the barriers which, to this date, made 'open-source' chip
development impossible.  See:

  http://circu.its.tudelft.nl/

Summary
-------
Open Design Circuits are the chip design counterparts of Open Source
Software, with designs (sources) openly shared among developers and
users. The open-design circuit approach outlined here captures the true
advantages of open-source software, and applies them to hardware. It
avoids the large initial investments usually needed for hardware
development, and it allows for the rapid design sharing, testing, and
user feedback which are key to open-source software success.

The development process is based on open (internet) development, FPGA,
hardware re-use, and more...  Take a look, enter the discussion, or
even better: join the effort.

- Reinoud

Article: 9414
Subject: Re: SOS!! Big Urgent Problem
From: zhangy <zhangy@isee.zju.edu.cn>
Date: Thu, 12 Mar 1998 08:59:00 +0800
Links: << >>  << T >>  << A >>
Jacob W Janovetz wrote:
> 
> zhangy <zhangy@isee.zju.edu.cn> writes:
> 
> >Would you please help me if you could help me ?
> 
> >I use Altera Flex8K(8820QFP) for my PCB design. When I configure it with
> >a ByteBlaster download cable, Something strange happen, that is, After
> >successfully download my .sof file, the PCB works normally , but if I
> >then put the cable away from my socket, the PCB failed. What's wrong
> >with it? I ensured that the configure circuit in my PCB is no problem.
> 
> >Any info. is appreciated.
> 
> I don't know a heck of a lot about Altera, but perhaps there
> is a programming pin on the device which you aren't pulling high
> or something.  Therefore, when you remove the cable it resets
> the device.
> 
>    Cheers,
>    Jake
> 
> --
>    janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
>  University of Illinois | your eyes turned skyward, for there you have been,
>                         | there you long to return.     -- da Vinci
>         PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html

You are right. A programming pin of Altera named CONF_DONE is pulled
down when I remove the cable. However, I had attached a pull-high
resistor to  it. the volume of resistor is 1K. That is why I confused,
because it seems that the pull-high resistor is no use. Could you
interpret it? I DO ensure that the circult is right.
Article: 9415
Subject: Byteblaster
From: zhangy <zhangy@isee.zju.edu.cn>
Date: Thu, 12 Mar 1998 09:09:59 +0800
Links: << >>  << T >>  << A >>
Who knows the ByteBlaster circult?
Article: 9416
Subject: Re: ModelSim, Active-VHDL simulators
From: dave@aldec.com
Date: Wed, 11 Mar 1998 19:14:51 -0600
Links: << >>  << T >>  << A >>
In article <6dqc8o$ah9$1@news10.ispnews.com>,
	sam@palmnet.net (Steve
Mitchell) wrote:
> 
> Has anyone else out there evaluated Active-VHDL and
compared it to
> ModelSim?  There's been a thread going on about a
context-sensitive
> editor for ModelSim, which is integrated into
Active-VHDL, along with
> a nice testbench shell generator.  I've evaluated
both products, but
> not to the extent where I've imported post-route delays,
and only
> with designs under 15K gates.  ModelSim didn't seem much faster. 
From
> what I can tell Active-VHDL seems to be a much better deal, and costs
> much less.  Are there features of ModelSim that I'm missing that make
> it
a much better tool, worth going out to find another tool for editing
> and
test bench generation?	Thanks for any input on these tools.
> 
> Steve
Mitchell
> 
Steve,

Thought you might like to know, Aldec does have several
bench marks comparing
Active-VHDL with MTI on 100K plus designs.  If you are
interested in this
 information let me know.

The key element that
Active-VHDL really offers is a seamless environment
for entry, test bench
generation and simulation from on vendor.

David

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 9417
Subject: Re: LARGE SELECTION OF FPGA BOARDS & KITS
From: Richard Schwarz <aps@associatedpro.com>
Date: Wed, 11 Mar 1998 21:10:34 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------463A28A4055B81AE2E8C2AFD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I know exactly who this is. You requested us to delay a shippment and we
did. You then complained that UPS didn't ship to you correctly and wanted
a refund for shipping costs. We checked into the matter and they said you
received the package on time. I thought the matter was resolved but
perhaps it is not.--this was DEC/JAN time frame--

If you would like to discuss it further, I am certainly open to this, and
wish
to try and make you a happier customer. :-) I think the major mix up for
you
was the request you made to delay the product's shippment. I know how
schedules are and I know even getting a package one day letter than
expected
can be an issue, and we try to get the orders to our customers as fast as
we can
--or on a schedule that customers wants (in this case delayed) --. Please
email me and I will
do my best to try to further resolve the problem.



disappointed wrote:

> Never picks up the phone, doesn't ship products on time, doesn't offer
> shipping refunds when shipments are late... why do business with APS?



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


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--------------463A28A4055B81AE2E8C2AFD--

Article: 9418
Subject: Re: DES: beginner FPGA questions.
From: "H. Ploog" <hp@e-technik.uni-rostock.de>
Date: Thu, 12 Mar 1998 11:48:35 +0100
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> You should not need anywhere near 25k gates, provided you put the
> S-boxes in external EPROMs. The S-boxes are difficult to do - I don't
> think the XC4000 has wide enough RAM but I could be wrong.

Own of my students has mapped the DES algo into a XC4010 and
it will run with up to 10(+) MHz.
No need for external Eproms! One S-box takes about 10 CLBs.
Decryption or encryption is selectable by external pin without any
need to reload the S-boxes.

> SNIP
> You will then need a 56-bit comparator, for a (exact) known-plaintext
> attack, or something rather more complex if you just want to detect
> when the output is probably some human language (e.g. search for a
> ASCII character set across the 7 bytes).
> 
> A very interesting project.
> 
> SNIP

Try Michael J. Wiener : "Efficient DES Key Search"
Article: 9419
Subject: SOS!! Big Urgent Problem
From: zhangy <zhangy@isee.zju.edu.cn>
Date: Thu, 12 Mar 1998 20:29:38 +0800
Links: << >>  << T >>  << A >>
Would you please help me if you could help me ?

I use Altera Flex8K(8820QFP) for my PCB design. When I configure it with
a ByteBlaster download cable, Something strange happen, that is, After
successfully download my .sof file, the PCB works normally , but if I
then put the cable away from my socket, the PCB failed. What's wrong
with it? I ensured that the configure circuit in my PCB is no problem.

Any info. is appreciated.
Article: 9420
Subject: Altera Programmer with NT4
From: Richard Staley <r.j.staley@bham.ac.uk>
Date: Thu, 12 Mar 1998 17:16:48 +0000
Links: << >>  << T >>  << A >>
Does anyone know the secret for getting Max+plusII v8.21 to recognise
the programmer ( MPU6 ) when running under WindowsNT4.
It's visible and working with Windows 3.1! 

Something to do with device drivers?

Any help appreciated,

Richard Staley , Hardware Engineer.
Article: 9421
Subject: Re: The case for Linux and EDA
From: walk@mrcnext.cso.uiuc.edu (Todd Walk)
Date: 12 Mar 1998 17:25:41 GMT
Links: << >>  << T >>  << A >>
Zoltan Kocsi <root@127.0.0.1> writes:
>Hm. You can take a look at Symplicity's stuff. You can buy their synthesis 
>for HP or Sun at AU$24k + 1 year compulsory maintenance. You can buy the
>exact same thing for Win AU$12k apiece (no contract). 
>Why ?

The $12K Win package is a node-locked version.  For $24K you
can get a floating license version for Windows (same as the
unix versions).

					Todd Walk
					walk@mrcnext.cso.uiuc.edu

Article: 9422
Subject: Re: SOS!! Big Urgent Problem
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 12 Mar 1998 18:58:12 GMT
Links: << >>  << T >>  << A >>
zhangy <zhangy@isee.zju.edu.cn> writes:

>Would you please help me if you could help me ?

>I use Altera Flex8K(8820QFP) for my PCB design. When I configure it with
>a ByteBlaster download cable, Something strange happen, that is, After
>successfully download my .sof file, the PCB works normally , but if I
>then put the cable away from my socket, the PCB failed. What's wrong
>with it? I ensured that the configure circuit in my PCB is no problem.

>Any info. is appreciated.


I don't know a heck of a lot about Altera, but perhaps there
is a programming pin on the device which you aren't pulling high
or something.  Therefore, when you remove the cable it resets
the device.

   Cheers,
   Jake

--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 9423
Subject: PhD forum at DAC -- Submission deadline Reminder
From: soha@cs.washington.edu (Soha Hassoun)
Date: Thu, 12 Mar 1998 21:03:27 GMT
Links: << >>  << T >>  << A >>

Hi, 
The deadline for abstract submissions for the PhD forum at DAC is
this Friday, March 13.
 
Students within one to two years from completing their PhD thesis are
elgible to participate in the forum.  The submission requirements are:

    --  A one-page abstract of the thesis (not including figures or
	references, and not to exceed 750 words) 

    --  A university-approved thesis proposal, or a published paper 

More details (whose eligible, submission requirements, the format of
the forum, awards) are available at www.cs.washington.edu/homes/soha/forum/. 
A short description of the PhD forum at DAC is included below.
 
 
Thanks.
 
Soha Hassoun
soha@eecs.tufts.edu
---------------------------------------------------------------------------

The Ph. D. forum at DAC, sponsored by SIGDA, provides a structured way
of increasing interaction between academia and industry. The forum's
goals include: (a) providing graduate students with feedback on their
thesis work from other researchers (b) giving CAD and system companies
a chance to preview academic work in progress.

The forum consists of two sessions:

1. An open poster session, hosted by SIGDA during their member meeting
on Tuesday, June 16, 7-9 PM. All interested DAC attendees are invited
to attend. Illustrating their work via posters, students will describe
their work to interested audience.

2. A discussion session to be held on Wednesday, June 17, 6-7:30 PM,
during which students received detailed feedback about their work.

Students and researchers (from both industry and academia) are
encouraged to participate in the forum. Please visit the forum's web
page http://www.cs.washington.edu/homes/soha/forum/ for more details
on how you can participate in the forum.



Article: 9424
Subject: Re: The case for Linux and EDA
From: "rk" <stellare@erols.com.NOSPAM>
Date: 12 Mar 1998 21:29:10 GMT
Links: << >>  << T >>  << A >>
Zoltan Kocsi <root@127.0.0.1> wrote in article
<m390qhk9ln.fsf@tade.bendor.com.au>...
: "rk" <stellare@erols.com.NOSPAM> writes:
: 
: > systems with differing capabilities with differing prices.  a
market-driven
: > environment, to a certain extent.  and it won't let companies sit on
their
: > butts, selling the same stuff for high prices year after year.  i see
the
: > ambit ads, don't know what they charge, but they're slamming synopsys
in
: > them.  very agressive.  they want business. and they can get it in two
: > ways: take away synopsys customers for price/performance/standards
reasons
: > or be low enough in price to get other people into the business or just
: > sell multiple seats to make a better engineering environment.  perhaps
: > someone with some good info on ambit can comment.
: 
: Hm. You can take a look at Symplicity's stuff. You can buy their
synthesis 
: for HP or Sun at AU$24k + 1 year compulsory maintenance. You can buy the
: exact same thing for Win AU$12k apiece (no contract). 
: Why ?
: 
: On the lower end:
: Actel's tools (VHDL synthesis and P&R) for Sun: AU$3.4k 
: For Win: AU$1.7k (or free from the net with limited choice of chips).
: 
: Or you can see Quicklogic:
: 
: Sun: AUD$3k contains P&R
: Win: AUD$3k contains P&R, verilog simulator, editor and the Symplicity 
:                      synthesis (verilog/VHDL).
: 					 
: Motorola P&R for Win is free (they even send you the CD for free), for 
: Sun it is not.
: 
: AFAIK others are not much different either.
: 
: Knowing that most of these tools are made under unix then ported to
: Win I can't really see the reason for pricing the Win tools way 
: below the unix ones unless Mr. Gates offers some compensation (I'm 
: not accusing, I'm just wondering ...)
: 
: As for having a cheap engineering platform then Linux is just as adequate
: as Win - it is even cheaper and more stable. In addition porting unix SW 
: to Linux is uncomparably simpler than to Win. Still, Linux is not on the
: EDA palette yet. 
: 
: Can you explain that ?
: 
: Zoltan

rk:

that's the question and the pattern and what we've been discussing. 
according to synopsys, who is porting from unix --> win and not from unix
--> linux, it's because no customer demand for linux.  and someone posted
that "Mr. Gates" is offering help.  and, i believe, ports to linux from
unix will mostly transfer unix users to linux.  similar # of customers, two
platforms to support.  win can bring in new customers and there are a lot
more win machines.  and it seems that a lot of companies are doing unix
<--> win tool sets with compatible file formats.  i like being able to
trade schematics and databases between users on unix and win; that covers
most of the 'puters out there and think that offers flexibility for an
organization and way to have different platforms with differing
capbabilities (i.e., super-duper sparc down to portable laptop for the
mobile engineer who either travels, fae, etc.).  of course, a similar
argument can be made with pc/linux, but pc/win has a huge installed base,
and that's a big advantage, even if not as technically good.

i think the difference in price is based on competition.  there are lots of
low-end tools on win that are low cost or even free - you gave a good list.
 so, unless those tools are unusable you can't charge really high prices
for something 'better' since people won't buy them, unless only they can do
the job.  but with, say, actel supplying tools either free or for a
relatively modest update fee (for unlimited device selection) that are
reasonable and usable, it's hard to justify spending a lot of $ for a
'better' tool.



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