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Messages from 4650

Article: 4650
Subject: Re: Lattice ISP Question
From: Richard Staley <r.j.staley@bham.ac.uk>
Date: Tue, 26 Nov 1996 09:04:17 +0000
Links: << >>  << T >>  << A >>
Thanks to all who replied ,esp Ilpo , I now have the information needed.
Regards Richard.
Article: 4651
Subject: Re: Which Mentor Graphics synthesis tool?
From: andym@trend.demon.co.uk (Andrew Morley)
Date: Tue, 26 Nov 96 10:19:45 GMT
Links: << >>  << T >>  << A >>
In article <329433E2.2A3D@radar-sci.jpl.nasa.gov>
           jorge@radar-sci.jpl.nasa.gov "jorge" writes:

> Will MG continue to support autologic II?  Or, will they(MG) drop it all
> together since I here MG is now going to use EXEMPLAR's synthesis tools?

My understanding is that for FPGA use (you asked this in the FPGA newsgroup!) 
Mentor will be pushing you in the direction of a new product specifically for 
FPGAs (ALII was never too not on FPGA stuff anyway).  I dare way it will have 
some imaginative name like 'Autologic FPGA'.  That's unless they buy yet 
another company and change their mind!

Andrew
-- 
 -----------------------------------------------------------------------------
| Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.|
| email: andrew.morley@trendcomms.com  Phone +44 1628-524977        Bucks, UK.|
 -----------------------------------------------------------------------------

Article: 4652
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: tboydsto@su19a.ess.harris.com (Ted Boydston)
Date: 26 Nov 1996 13:24:53 GMT
Links: << >>  << T >>  << A >>
Mark.Sandstrom@martis.fi (Mark Sandstrom) writes:
: Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
: I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter
: what I try, all my I/O registers are mapped into the CLBs. I'm

I believe all that is required is not putting a reset on the flop.  A
coworker of mine uses this technique and says it works.


--
...__.....__...........................................................
..|  |...|  |...                   Ted L. Boydston IV                 .
__|  |___|  |...                                                      .
 _  /\  /\  _|__  Harris Corporation, GASD  email: tboydsto@harris.com .
_\/  \/__\/ |... PO BOX 94000, MS 102-4823 voice: (407) 729-7999      .
..|  |...|  |... Melbourne, FL  32902      fax  : (407) 729-2782      .
..|__|...|__|..........................................................                                                              
Article: 4653
Subject: Re: How to use Xilinx ?
From: timolmst@cyberramp.net
Date: Tue, 26 Nov 1996 13:32:27 GMT
Links: << >>  << T >>  << A >>
Steve Wiseman <steve@sj.co.uk> wrote:

>> I'm using Xilinx's XACT to design FPGA . I haven't any experience with Xilinx's
>> FPGA and have some problems . Hope you help me .
>> 
>> 1. When use VHDL
>>    When use VHDL to design a FPGA , how to assign the pin number ? I heard of
>>    it is disable to assign the pin nubmer without using schematic .Is it right ?

I don't use VHDL with Xilinx, but can't you write a constraints file
for the design? You can specify pin numbers there, and lock them.
RTB.



Article: 4654
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: samson@seic10a.erim.org (Joe Samson)
Date: 26 Nov 1996 10:04:49 -0500
Links: << >>  << T >>  << A >>
>Mark.Sandstrom@martis.fi (Mark Sandstrom) writes:
>: Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
>: I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter
>: what I try, all my I/O registers are mapped into the CLBs. I'm

>I believe all that is required is not putting a reset on the flop.  A
>coworker of mine uses this technique and says it works.

There are a few more criteria. I found that when I upgraded to a new version,
XBLOX wasn't moving as many flipflops into IOBs as the old version. I
E-mailed to the hotline and got this reply:

     	I believe I have found the cause of the non-IOB-optimization 
	with XBLOX 5.2.  The criteria has slightly changed from 
	5.0 ->5.2 for FF IOB optimization.  It turns out that it was 
	discovered that when X-BLOX pushed output FFs into IOBs that 
	were sourced by combinatorial logic, an additional level of 
	logic and/or an added net delay was causing extra setup delay 
	thus degrading performance.  It was decided that any FF sourced 
	either directly or indirectly (one or more buffers and/or 
	inverters between non-cominatorial source and D-pin) by 
	combinatorial logic would defaultly not be pushed into IOBs unless 
	otherwise specified.  It was decided that the STYLE=IOB attribute 
	on an X-BLOX component would forcebly specify to optimize the FF 
	into an IOB.  Unfortunatly there is no attribute to force 
	non-XBLOX created FFs.  This may only be done by expicitly 
	expressing to use an OFD instead od FD.

-- 
+===============================================================+
+ Joe Samson                               (313) 994-1200 x2878 +
+ Research Engineer, ERIM                                       +
+ P.O. Box 134001                         email samson@erim.org +
+ Ann Arbor, MI 48113-4001                                      +
+===============================================================+
Article: 4655
Subject: Re: FPGA TEST BOARDS
From: Andre Hergenhan <hergenhan@fzi.de>
Date: Tue, 26 Nov 1996 17:40:59 +0100
Links: << >>  << T >>  << A >>
jjfakas@erols.com wrote:
> =

> I am looking for a low cost FPGA test board which will run on an IBM PC=

> and will take a X4010 or X5010 FPGA. I am on a low budget and can't
> afford thousands of dollars. Does anyone know of such a beast? I alread=
y
> have the XILINX routing software and synthesis tools.
> =

> Thanks in advance,
> =

> Jim

-- =

Forschungszentrum Informatik (FZI)
Andr=E9 Hergenhan
Haid-und-Neu-Str. 10-14
D-76131 Karlsruhe
Phone:  ++49/721/9654-470
Fax:    ++49/721/9654-409
EMail:  hergenhan@fzi.de
Article: 4656
Subject: Re: How to use Xilinx ?
From: Jerry English <jenglish@harris.com>
Date: Tue, 26 Nov 1996 12:06:26 -0500
Links: << >>  << T >>  << A >>
I use the .cst file to assign pin numbers to signals.
The .cst file is used in ppr. 
The format is 
PLACE INSTANCE signal_name_pad: P desire pin number;
example
PLACE INSTANCE RESET_pad: P23;

I don't assign pin numbers in the VHDL enviroment.
cann't help with simulating, we use synopsys simulator.

regards

jerry english
Article: 4657
Subject: Re: Electronics question
From: Gareth Baron <EXTR.QBCGABA@mesmtpse.ericsson.se>
Date: Tue, 26 Nov 1996 09:26:54 -0800
Links: << >>  << T >>  << A >>
As far as I remember there are some equations that correlate the 
threshold to the aspect ratios some how.  If these are known parameters 
you may be able to correlate the aspect ratios to the threshold voltages 
and then to each other.  Unfortunately I haven't got my books to hand 
(I'm based in the UK but am currently working in Sweden).
-- 


Gareth Baron.

Email: gareth@trsys.demon.co.uk
Article: 4658
Subject: Re: How to use Xilinx ?
From: Steve Wiseman <steve@sj.co.uk>
Date: Tue, 26 Nov 1996 18:45:53 +0000
Links: << >>  << T >>  << A >>
Jerry English wrote:
> 
> I use the .cst file to assign pin numbers to signals.
> The .cst file is used in ppr.

Yes, this is fine for schematics. The only problem is that VHDL source
won't give you the reference you need. 

For the brave, VHDLDES also has a -iopad option, which claims to bind
iopads to the top level signals. I never got this to work, so stopped
trying. Has anyone had success?

  Steve
Article: 4659
Subject: ### Chipmaker URLs (almost 300!) and other resources for finding data sheets ###
From: Gray Creager <gcreager@scruznet.com>
Date: Tue, 26 Nov 1996 11:54:59 -0800
Links: << >>  << T >>  << A >>
I've been maintaining a comprehensive listing of semiconductor
manufacturer websites for more than a year. This is the same list that I
used to post to USENET for everyone to use, but now it's too big for
that. Many engineers find it useful (or at least all of the e-mail says
that it is)... but many other engineers don't know about it. I update it
several times a week and actively search for new URLs frequently. You
can view just the company URLs or the URLs with a brief company product
description. I think you'll find it helpful when searching for a
particular data sheet, etc...

Anyway, check it out...

http://www.scruznet.com/~gcreager/hello5.htm

-- 
Gray Creager (gcreager@smtpgate.xicor.com)
Applications Engineer
Xicor, Inc.
http://www.xicor.com
Article: 4660
Subject: WinEDA online eng. conf ends
From: Deborah Peel <reconfig@best.com>
Date: 26 Nov 1996 23:22:42 GMT
Links: << >>  << T >>  << A >>
After 13 weeks, WinEDA '96, the pioneering event into online conferencing
and exhibiting, will come to a close on November 29.  We thank our
participants (1000 plus) from around the world for joining in the
Conference!

There is now an Evaluation Form available at www.wedasite.com. If you
looked in on WinEDA we need your critique.

Please take a minute to rate WinEDA so that we can improve on the
overall concept, method and information resources for future events.
Your input can help shape Web conferencing and help us bring it to you
the way that you want it.

Thanks,
Stan Baker
Program Chairman
WinEDA '96



Article: 4661
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: hari@syzygy.xilinx.com (Hari Vattikota)
Date: 26 Nov 1996 23:49:57 GMT
Links: << >>  << T >>  << A >>

In article <32998FFF.1466@martis.fi>, Mark Sandstrom
<Mark.Sandstrom@martis.fi> writes:
|> Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
|> I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no
|> matter
|> what I try, all my I/O registers are mapped into the CLBs. I'm
|> describing the I/O registers in the VHDL description in a normal
|> D-flip-flop style. The flip-flops are controlled by the global reset
|> for
|> which I use the GSR net. 
|> 
|> I tell Synopsys:
|> 
|> set_register_type -exact -flip_flop OFD_F find (design,
|> stm4_out_reg)
|> Performing set_register_type on design 'stm4_out_reg'. 
|> 1
|> 
|> but the flip_flops synthesize into 'FDC's.
|> 
|> Thanks for any information that could help!
|> 
|> Mark


Please avoid global reset on the I/O flip-flops you want to infer

Hari
Article: 4662
Subject: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Tue, 26 Nov 1996 23:53:37 GMT
Links: << >>  << T >>  << A >>
=============================================================================

                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

   The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems.  All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium.  Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
 
   The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop.  Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:

    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:

    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

General Chair:               A. B. Kahng (UCLA and Cadence)
Past Chair:                  G. Robins (Virginia)
Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
                             W. W.-M. Dai (UC Santa Cruz) 
                             J. Frankle (Xilinx) 
                             D. D. Hill (Synopsys) 
                             M. A. B. Jackson (Motorola) 
                             J. A. G. Jess (Eindhoven)  
                             Y.-L. Lin (Tsing Hua) 
                             C. L. Liu (Illinois)
                             M. Marek-Sadowska (UC Santa Barbara)
                             M. Sarrafzadeh (Northwestern)
                             C. Sechen (Washington) 
                             K. Takamizawa (NEC)
                             M. Wiesel (Intel) 
                             D. F. Wong (Texas-Austin) 
                             E. Yoffa (IBM)

=============================================================================

Article: 4663
Subject: Programming the AT17C256
From: "Erwin Oertli" <oertli@inf.ethz.ch>
Date: 27 Nov 1996 08:22:55 GMT
Links: << >>  << T >>  << A >>
Our DATA/IO 2900 can program the AT17C65 and the AT17C128, but not the
AT17C256.

How are you programming the AT17C256?

Best regards
Erwin Oertli
Article: 4664
Subject: Re: Which Mentor Graphics synthesis tool?
From: Duncan Davis <duncan.davis@gecm.com>
Date: 27 Nov 1996 08:48:42 GMT
Links: << >>  << T >>  << A >>


My understanding is that MEntor have rationlised their synthesis groups 
and Exemplar will become the driving force behind MGCs three synthesis 
tools, Galileo, Leonardo and Autologic2.

Galileo is primarily aimed at low to med complexity FPGAs, Leonardo at 
med/high FPGAs and Low/med ASICs and AL2 at ASICs.


If you are an existing AL2 for FPGA customer you should be entitled to 
Galileo due to the loss of FPGA support in AL2 at release B2 assuming 
you have a maintenance contract. I would suggest you contact your local 
MEntor support office for clarification of your position.


As for libraries at B2 I don't believe there will be any FPGA support for 
AL2. 

Article: 4665
Subject: JEDEC file structure
From: "D. Hibbs" <mtx064@coventry.ac.uk>
Date: Wed, 27 Nov 1996 09:35:08 +0000
Links: << >>  << T >>  << A >>
Could anyone point me to the specification of the JEDEC file structure 
for programming GAL.

TIA

Dominic

Article: 4666
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: dietrich@krusty.htc.honeywell.com (Paul Dietrich)
Date: 27 Nov 1996 07:42:30 CST
Links: << >>  << T >>  << A >>
On 26 Nov 1996 23:49:57 GMT, Hari Vattikota <hari@syzygy.xilinx.com> wrote:
>
>In article <32998FFF.1466@martis.fi>, Mark Sandstrom
><Mark.Sandstrom@martis.fi> writes:
>|> Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
>
>Please avoid global reset on the I/O flip-flops you want to infer

Why should global set/reset be avoided?  The 4000e supports GSR in IOB
flip-flops.  I've used GSR in my designs and the flip-flops get merged into
IOBs.  It's true that the IOB flip-flops don't have another reset besides
GSR.
Article: 4667
Subject: WVoffice and ACTEL Design Series
From: Pasquale Corsonello <pascor@ccusc1.unical.it>
Date: Wed, 27 Nov 1996 18:18:05 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

--------------61A753756124
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi all,
I have WVoffice 7.1 and ACTEL Design Series 3.1. The development system
run on a PC-WIN95.

The Actel Designer accepts as input edif file from the CAE software.
If I try to use an EDIF netlist write from Workviewoffice EDIF
interfaces, the following errors occur when ACTEL Designer compile the
.edn file. 

*Error: c:\progetti\gest_rom\TESTACTEL.edn, line 27: cell DELAY has no
*contents and is not
*       defined in library C:\ACTEL/data/a1000/adl07.lib
*Error: c:\progetti\gest_rom\TESTACTEL.edn, line 43: cell NOT has no
*contents and is not defined
*       in library C:\ACTEL/data/a1000/adl07.lib
*Error: c:\progetti\gest_rom\TESTACTEL.edn, line 61: cell TRIBUF has no
*contents and is not
*       defined in library C:\ACTEL/data/a1000/adl07.lib
*Error: c:\progetti\gest_rom\TESTACTEL.edn, line 81: cell SIMBUF has no
*contents and is not
*       defined in library C:\ACTEL/data/a1000/adl07.lib
*Error: c:\progetti\gest_rom\TESTACTEL.edn, line 283: cell MUX41 has no
*contents and is not
*       defined in library C:\ACTEL/data/a1000/adl07.lib
*
*The import_netlist command failed ( 00:00:07 )


I'm sure that the problem is design-independently.
Can someone help me?

tank you in advance,

--------------61A753756124
Content-Type: text/plain; charset=us-ascii; name="attach.txt"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="attach.txt"

*********************************************************
*Pasquale Corsonello  Microelectronic Design Laboratory *
*Department of Electronic Computer Science and System   *
*University of Calabria                                 *
*Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY    *
*Tel:+39 984 494708 Fax:+39 984 494713                  *
*email:pascor@ccusc1.unical.it-corsone@nwdeis1.unical.it*
*********************************************************


--------------61A753756124--

Article: 4668
Subject: Re: FPGA TEST BOARDS
From: Gareth Baron <EXTR.QBCGABA@mesmtpse.ericsson.se>
Date: Wed, 27 Nov 1996 09:20:42 -0800
Links: << >>  << T >>  << A >>
Xilinx have one of these boards available.  I don't think it is that 
expensive.  I remember getting it with the PRO stuff a while ago (2 
years) so I'm not sure what they are offering now.  Give them a ring and 
see what they can conjur up for you.  You might even be able to get it 
free.

-- 


Gareth Baron.

Email: gareth@trsys.demon.co.uk
Article: 4669
Subject: Reconfigurable chip
From: Pasquale Corsonello <pascor@ccusc1.unical.it>
Date: Wed, 27 Nov 1996 18:21:08 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

--------------2B024D894686
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi all,
have anyone used XILINX chip to realize reconfigurable system?

Please contact me.

--------------2B024D894686
Content-Type: text/plain; charset=us-ascii; name="attach.txt"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="attach.txt"

*********************************************************
*Pasquale Corsonello  Microelectronic Design Laboratory *
*Department of Electronic Computer Science and System   *
*University of Calabria                                 *
*Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY    *
*Tel:+39 984 494708 Fax:+39 984 494713                  *
*email:pascor@ccusc1.unical.it-corsone@nwdeis1.unical.it*
*********************************************************


--------------2B024D894686--

Article: 4670
Subject: Re: FPGA TEST BOARDS
From: "Richard Schwarz" <aaps@erols.com>
Date: 27 Nov 1996 17:29:44 GMT
Links: << >>  << T >>  << A >>
Jim,

There is a XILINX FPGA test board available from APS which does exactly
what you want. It is very inexpensive and works with any 4000/5000 84 pin
plcc family chip. Its called the APS-X84 and sells for around 250.00. It
comes with a 5202 FPGA in it and has an 8255 chip on board, oscillators and
timers, and tons of IO connections.'
Check it out at http://www.erols.com/aaps, email to aaps@erols.com

Richard

jjfakas@erols.com wrote in article <3293E3AE.624E@erols.com>...
> I am looking for a low cost FPGA test board which will run on an IBM PC 
> and will take a X4010 or X5010 FPGA. I am on a low budget and can't 
> afford thousands of dollars. Does anyone know of such a beast? I already 
> have the XILINX routing software and synthesis tools.  
> 
> Thanks in advance,
> 
> Jim
> 
Article: 4671
Subject: Re: How to use Xilinx ?
From: Martin d'Anjou <mdanjou@nortel.ca>
Date: Wed, 27 Nov 1996 15:48:57 -0500
Links: << >>  << T >>  << A >>
Steve Wiseman wrote:
> 
> Jerry English wrote:
> >
> > I use the .cst file to assign pin numbers to signals.
> > The .cst file is used in ppr.
> 
> Yes, this is fine for schematics. The only problem is that VHDL source
> won't give you the reference you need.

With Synplify synthesizer, just add to your VHDL the attributes:

attribute xc_loc : string;
attribute xc_loc of SignalName : signal is "P56";

And SignalName is attached to pin 56.

Also also use the pins.cst for other VHDL designs and works fine.

Martin
-- 
| Martin d'Anjou                  | tel: (613) 765-3058                |
| Nortel                          | fax: (613) 763-9535                |
| P.O. Box 3511, Station C        | email: mdanjou@nortel.ca           |
| Ottawa, Ontario, CANADA  K1Y 4H7| My opinions, not Nortel's          |
| http://www.nortel.com/          | Mes opinions, pas celles de Nortel |
Article: 4672
Subject: Re: VHDL adder: how do I get at the carry bit?
From: chris.hart@iee.org (Chris Hart)
Date: Wed, 27 Nov 1996 21:21:27 GMT
Links: << >>  << T >>  << A >>
"Austin Franklin" <darkroom@ix.netcom.com> wrote:

>> I'm using Xilinx's Foundation for VHDL.
>> I'm trying to figure out how to change a 4 bit add to have a carry in
>> and carry out. (I can't find anything like this in my VHDL books).
>
>That would be real easy with a schematic!  ;-)
ha, ha, my sides are splitting ;->
>BTW...do the Foundation tools allow you to do simulation with full timing? 
>I heard that they don't...
Sorry I haven't got that far yet. I had a small excursion into timing
and it seemed to work ...
Chris Hart - chris.hart@iee.org

Article: 4673
Subject: SRAM Programming on the Altera NFX780
From: khorton@iquest.net (Kevin Horton)
Date: Thu, 28 Nov 1996 00:49:40 GMT
Links: << >>  << T >>  << A >>
I've been doing a little project on the Altera EPX780LC84-15.  I have it
working great (visit: http://www.iquest.net/~khorton/bankzill.htm for
details) but I'm having problems finding the programming spec. for this part.
The goal is to have a micro (80C85) program it on power-up so that changes 
and additions are simple to do without replacing the FPGA.

I've done several 'net searches and have come up empty-handed.  I visited the
Altera web page, and it's like the part has never existed; there are only
data sheets for their latest offerings.  

So, if anyone can tell me the basics on how to get the data into the part's
SRAM cells, I'd be appriciative.  BTW, I used the 'pengen' program to convert
the JEDEC file into the bit-stream required by the part; I just need to know
how to play with the TCK, TDI, TDO (output probably not required for 
programming), and TMS lines.

Article: 4674
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: jean_l@ulix.net (Jean Lachance)
Date: Thu, 28 Nov 1996 03:28:36 GMT
Links: << >>  << T >>  << A >>
Mark Sandstrom <Mark.Sandstrom@martis.fi> wrote:

>Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys?
>I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter
>what I try, all my I/O registers are mapped into the CLBs. I'm
>describing the I/O registers in the VHDL description in a normal
>D-flip-flop style. The flip-flops are controlled by the global reset for
>which I use the GSR net. 

>I tell Synopsys:

>set_register_type -exact -flip_flop OFD_F find (design, stm4_out_reg)
>Performing set_register_type on design 'stm4_out_reg'. 
>1

>but the flip_flops synthesize into 'FDC's.

>Thanks for any information that could help!

>Mark

Synopsys will not synthesize flip-flop into IOB, but only flip-flop in
CLBs. It is XBLOX that will move flip-flop into IOB if all
requirements of your device are met.

For XC4000E devices, flip-flops have now clock enable pins, and allows
(i think) the use of GSR.

Hope it help.


===========================================
Jean Lachance                 Tel   : 514-956-1010 ext 4072
IC Design Engineer           Fax   : 514-956-3384
Nortel                              Email : jean.lachance@nortel.ca
===========================================





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