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Problem solved: I have code on my website that synthesizes any multiplier (unsigned only) up to 32x32 into a Lucent FPGA. These are parallel multipliers based on binary adder trees and run like hell. 16x16 multiplier runs at 33.5 MHz in 1 Clock cycle. 80 MHz if you give it 4 cycles (pipelined). With 4 cycles of latency, the launch rate into the pipeline is 80 MHz. Of course, this kind of speed requires the fastest available FPGA, which is a Lucent 2T15A-7 Manual page for the multiplier is http://www.cam.org/~jqm/multiply.htm and my main page is http://www.cam.org/~jqm Oh, the code is somewhat gnarly VHDL-93, so you'll need a VHDL-93 compliant synthesis tool. I used Exemplar Galileo to synthesize, and Model Tech's Modelsim to simulate it. Std_Disclaimer: I work for Lucent. As an FPGA FAE, naturally. John McCluskey Lucent Technologies Ganapathy Subbaraman wrote: > Hello All (help needed !!!) > > We know that multiplying a 32bit by 32bit number requires 33 clocks when > we multiply bit by bit and shift the partial products. If we synthesize > this this will require some # of adders, say n(n-1) full adders or > n(n-2) full adders plus n half adders and n x n AND gates. Each adder is > a 1bit adder. This is parallel multiplication or known as array > multiplication. > > My Goal is to perform the same multiplication of 32bit by 32bit in > reduced cyle computation & less hardware. > > For Example: - If we need less hardware, then we need say 50clocks > - If we need more hardware, then we need say 16clocks > > The final solution is to find a multiplication algorithm that uses less > hardware & less computation time to find the result. Please when any of > you propose an algorithm for 32bit by 32bit multiplication, (In general > n-bit by n-bit) > > -specify the numbers of adders used & the type CSA, CLA, (RCA or CPA) > CSA -Carry Save Adder > CLA -Carry Look Ahead Adder > RCA -Ripple Carry Adder or Carry Propagate Adder > > -specify the numbers of shift registers or AND gates or multiplexers > used > -specify the numbers of clock cycles that will be used for the > computation. > > I donot know if this is silly but I will like to know if # of clock > cycles taken to compute the result can be equated to the propagation > delay. If so please explain. > > The tradeoff is in this priority > > 1. Hardware must be less > 2. Speed or computation time must be less > > This feedback will be used for hardware acceleration of RAID > calculations. > > All your feedback will be greatly appreciated, > With best regards - Subbu > My email is subbu@eng.adaptec.comArticle: 9451
Jeff Sampson wrote: > Just a quick question, > > If I dig through the Xilinx documentation long enough, will I find the > mapping of the setup ROM to the FPGA bits? In other words, could I > program these parts by hand? Bit by bit. > > It occurred to me that on one hand, it may be a big shift register > logically mapped to the internal bits. With the bits in each CLB always > mapped in the same order and all CLB are lined up in order, one after > another. On the other hand, the bits may be randomly mapped to allow easy > fabrication of the chip. > > I collected a handfull of parts and then found that the design software > would cost me thousands of dollars. You can by Foundation Base for $95 bucks. It contains all that you need for design. Schematic capture, simulation and Place and Route. > Alot of money considering I'm just > playing around. And yes, I have heard of a $250 limited useage package. > In particular I have XC2018, XC2064, XC3020 and XC3064 parts. > Now this is a problem. XC2ks are no longer supported also the versions of 3ks that you name are not in the new Foundation box. Now if one could find a Foundation Xact 6.01 then you would be all set. > So, is this info available? Or is this another one of those closely > guarded secrets? > Most closely guarded secrect!!! Xilinx has two concerns.1. Customers do not want their designs reversed engineered. If you know what the bit pattern does you have the design. 2. Xilinx's own position. If what the bit steam did to the part was known, making a drop in replacement part would be a lot easier. > Thanks, > > -- > Jeff Sampson Minneapolis, MN, USA > (Toshiba T6963 and EPSON/SMOS SED1330 LCD Controllers) > jsampson@pobox.com jsampson@citilink.com > http://www.pobox.com/~lcd_infoArticle: 9452
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end
Article: 9453Here is the answer you should have gotten from Xilinx. My solution to what you want to do is: If you want to modify the bits of a ROM in the bitstream, you need to do three things: 1) control the placement of the ROMs with location/relative location attributes, so you know where the bits in your microword, or what ever are, in terms of CLB ID. 2) when running makebits (xact 6) or bitgen (M1), have it output a .LL file. 3) write a program to patch your bitstream file based on the info in 1 and 2, and the new data you want to put in the ROM. ( you could ask also why Xilinx hasn't written such a program, given that this is NOT an uncommon request.) Here is a sample of what you get from the bitgen LL file: Revision 3 ; Created by bitgen M1.3.7 at Wed Dec 03 18:15:26 1997 ; Bit lines have the following form: ; <offset> <frame number> <frame offset> <information> ; <information> may be zero or more <kw>=<value> pairs ; Block=<blockname specifies the block associated with this ; memory cell. ; ; Latch=<name> specifies the latch associated with this memory cell. ; ; Net=<netname> specifies the user net associated with this ; memory cell. ; ; COMPARE=[YES | NO] specifies whether or not it is appropriate ; to compare this bit position between a ; "program" and a "readback" bitstream. ; If not present the default is NO. ; ; Ram=<ram id>:<bit> This is used in cases where a CLB function ; Rom=<ram id>:<bit> generator is used as RAM (or ROM). <Ram id> ; will be either 'F', 'G', or 'M', indicating ; that it is part of a single F or G function ; generator used as RAM, or as a single RAM ; (or ROM) built from both F and G. <Bit> is ; a decimal number. ; ; Info lines have the following form: ; Info <name>=<value> specifies a bit associated with the LCA ; configuration options, and the value of ; that bit. The names of these bits may have ; special meaning to software reading the .ll file. ; Bit 24 1 390 Block=P124 Latch=I1 Bit 36 1 378 Block=P126 Latch=I1 Bit 48 1 366 Block=P128 Latch=I1 yada yada yada Bit 22838 55 40 Block=CLB_R3C32 Rom=G:0 Bit 22860 55 18 Block=CLB_R1C32 Rom=G:9 Bit 22861 55 17 Block=CLB_R1C32 Rom=G:1 Bit 22862 55 16 Block=CLB_R1C32 Rom=G:0 Bit 22908 56 386 Block=CLB_R31C32 Rom=G:12 Bit 22910 56 384 Block=CLB_R31C32 Rom=G:5 Bit 22932 56 362 Block=CLB_R29C32 Rom=G:12 Bit 22934 56 360 Block=CLB_R29C32 Rom=G:5 Bit 22956 56 338 Block=CLB_R27C32 Rom=G:12 Bit 22958 56 336 Block=CLB_R27C32 Rom=G:5 Bit 22980 56 314 Block=CLB_R25C32 Rom=G:12 Bit 22982 56 312 Block=CLB_R25C32 Rom=G:5 Bit 23006 56 288 Block=CLB_R23C32 Rom=G:12 Bit 69734 168 152 Block=CLB_R12C30 Rom=F:4 Bit 69736 168 150 Block=CLB_R12C30 Rom=F:2 Bit 69746 168 140 Block=CLB_R11C30 Rom=F:4 Bit 69748 168 138 Block=CLB_R11C30 Rom=F:2 Bit 69758 168 128 Block=CLB_R10C30 Rom=F:4 Bit 69760 168 126 Block=CLB_R10C30 Rom=F:2 Bit 69770 168 116 Block=CLB_R9C30 Rom=F:4 Bit 69772 168 114 Block=CLB_R9C30 Rom=F:2 Bit 69784 168 102 Block=CLB_R8C30 Rom=F:4 Bit 69786 168 100 Block=CLB_R8C30 Rom=F:2 Note that the bit positions can change from one run to another, even if you lock the location of the ROM, because M1 wont let you lock the address pins. when it routes, it can do pin swaps on these signals, which radically changes the layout of the ROM in the bitstream. Good luck Philip Freidin In article <350a62aa.425772656@news.dial.pipex.com> ems@see_signature.com (ems) writes: > >maybe so, but it would be useful to have some more information; in >particular, the location of the bits that define the contents of a ROM >module. > >i had a design recently that included a microcoded controller. the >microcode was stored in a rom module, created via logiblox. with this >sort of design you have to change the rom contents occasionally, to >(a) make it work, and (b) carry out simulations, with simplified test >microcode. > >however, it seems that the only way you can do this is to recreate the >logiblox module with a different MEM file. this meant that i had to go >through the entire P&R procedure for each iteration, which could take >several hours. there was also the risk (admittedly small) that the >route would fail with new rom data. when i asked xilinx tech support >if there was a better way of doing this, the reply was (a) "why would >you want to change a rom?", and (b) "why don't you use a ram instead?" > >the best solution, of course, is to have a utility to edit the bit >file directly. i would have written this myself if the required >information hadn't been "a closely guarded secret". > >evan (ems@nospam.riverside-machines.com) >Article: 9454
You are right with regard to effort versus cost of ready made P&R software. But there are reasonable (if rather uncommon) cases where one might want this info. You may want to modify just a part of a design, e.g. the logic in a decoder. OTOH one can do that more elegantly using the RAM in a 4k device but then one needs to build in an interface for loading the new data, whereas the interface for the bitstream is already there. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9455
For registration information check out www.fccm.org.
The 6th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines
FCCM '98
Marriott at Napa Valley, Napa, California
14-17 April 1998
Preliminary Program
Tuesday 14 April 1998
----------------------------------------------------------------------------
7:00pm - 9:00pm
Registration and Reception
----------------------------------------------------------------------------
Wednesday 15 April 1998
----------------------------------------------------------------------------
8:30am - 10:00am
Session 1: Architectures I
----------------------------------------------------------------------------
Authors: T. Miyamori and K. Olukotun
Organization: Stanford University
Title: A Quantitative Analysis of Reconfigurable Coprocessors
for Multimedia Applications
Authors: C.A. Moritz, D. Yeung and A. Agarwal
Organization: MIT LCS
Title: Exploring Optimal Cost-Performance Designs for
Raw Microprocessors
Authors: C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt,
J. Arnold and M. Gokhale
Organization: National Semiconductor and Sarnoff Corp.
Title: The NAPA Adaptive Processing Architecture
----------------------------------------------------------------------------
10:00am - 11:00am
Coffee break and Poster Session
----------------------------------------------------------------------------
----------------------------------------------------------------------------
11:00am - 12:00pm
Session 2: Special Purpose Systems
----------------------------------------------------------------------------
Authors: S. Swanchara, S. Harper and P. Athanas
Organization: Virginia Tech
Title: A Stream-Based Configurable Computing Radio Testbed
Authors: A. Dollas, E. Sotiriades and A. Emmanonelides
Organization: Technical University of Crete
Title: Architecture and Design of GE1, a FCCM for
Golomb Ruler Derivation
----------------------------------------------------------------------------
12:00pm - 1:30pm
Lunch break
----------------------------------------------------------------------------
----------------------------------------------------------------------------
1:30pm - 3:00pm
Session 3: Architectures II
----------------------------------------------------------------------------
Authors: A. Ohta, T. Isshiki and H. Kunieda
Organization: Tokyo Institute of Technology
Title: New FPGA Architecture for Bit-Serial Pipeline Datapath
Authors: K. Nagami, K. Oguri, T. Shiozawa, H. Ito and R. Konishi
Organization: NTT Optical Network Systems Laboratories
Title: Plastic Cell Architecture: Towards Reconfigurable Computing
for General Purpose
Authors: S. M. Scalera and J. R. Vazquez
Organization: Lockheed Sanders
Title: The Design and Implementation of a Context Switching FPGA
----------------------------------------------------------------------------
3:00pm - 4:00pm
Coffee break and Poster Session
----------------------------------------------------------------------------
----------------------------------------------------------------------------
4:00pm - 5:00pm
Session 4: Applications I
----------------------------------------------------------------------------
Authors: R. Hudson, D. Lehn and P. Athanas
Organization: Virginia Tech
Title: A Run-Time Reconfigurable Engine for Image Interpolation
Authors: M. Shand and L. Moll
Organization: DEC
Title: Hardware/Software Integration in Solar Polarimetry
----------------------------------------------------------------------------
7:00pm - 10:00pm
Buffet dinner and demonstrations
----------------------------------------------------------------------------
Thursday 16 April 1998
----------------------------------------------------------------------------
8:30am - 10:00am
Session 5: Compilers
----------------------------------------------------------------------------
Authors: A.A. Duncan, D.C. Hendry, P. Cray
Organization: University of Aberdeen
Title: An Overview of the COBRA-ABS High Level Synthesis System for
Multi-FPGA Systems
Authors: D. Cronquist, P. Franklin, S. Berg and C. Ebeling
Organization: University of Washington
Title: Specifying and Compiling Applications for RaPiD
Authors: M.B. Gokhale and J.M. Stone
Organization: Sarnoff Corp.
Title: NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
----------------------------------------------------------------------------
10:00am - 11:00am
Coffee break and Poster Session
----------------------------------------------------------------------------
----------------------------------------------------------------------------
11:00am - 12:00pm
Session 6: Tools for Run Time Reconfiguration
----------------------------------------------------------------------------
Authors: S. Hauck, Z. Li and E. Schwabe
Organization: Northwestern University
Title: Configuration Compression for the Xilinx XC6200 FPGA
Authors: N. Shirazi, W. Luk and P.Y.K. Cheung
Organization: Imperial College
Title: Automating Production of Run-Time Reconfigurable Designs
----------------------------------------------------------------------------
12:00pm - 1:30pm
Lunch break
----------------------------------------------------------------------------
----------------------------------------------------------------------------
1:30pm - 3:00pm
Session 7: Module Generation
----------------------------------------------------------------------------
Authors: M. Chu, K. Sulimma, N. Weaver, A. DeHon, J. Wawrzynek
Organization: UCBerkeley
Title: Object Oriented Circuit-Generators in Java
Authors: O. Mencer, M. Morf and M. J. Flynn
Organization: Stanford University
Title: PAM-Blox: High Performance FPGA Design for Adaptive Computing
Authors: P. Bellows and B. Hutchings
Organization: Brigham Young University
Title: JHDL - An HDL for Reconfigurable Systems
----------------------------------------------------------------------------
3:00pm - 4:00pm
Coffee break and Poster Session
----------------------------------------------------------------------------
----------------------------------------------------------------------------
4:00pm - 5:00pm
Session 8: Applications II
----------------------------------------------------------------------------
Authors: P. Zhong, M. Martonosi, P. Ashar and S. Malik
Organization: Princeon University and NEC CCRL
Title: Accelerating Boolean Satisfiability with Configurable Hardware
Authors: A. Rashid, J. Leonard and W.H. Mangione-Smith
Organization: UCLA
Title: Dynamic Circuit Generation for Solving Specific Problem
Instances of Boolean Satisfiability
Friday 17 April 1998
----------------------------------------------------------------------------
8:30am - 10:00am
Session 9: Arithmetic
----------------------------------------------------------------------------
Authors: W. Ligon, S. McMillan, G. Monn, F. Stivers and K. Underwood
Organization: Clemson University
Title: A Re-evaluation of the Practicality of Floating Point
Operations on FPGAs
Authors: A. F. Tenca and M. D. Ercegovac
Organization: UCLA
Title: A Variable Long-precision Arithmetic Unit Design suitable for
Reconfigurable Coprocessor Architectures
Authors: S. D. Haynes and P. Y. K. Cheung
Organization: Imperial College
Title: A Reconfigurable Multiplier Array for Video Image Processing
Tasks, Suitable for Embedding in an FPGA Structure
----------------------------------------------------------------------------
10:00am - 11:00am
Coffee break and Poster Session
----------------------------------------------------------------------------
----------------------------------------------------------------------------
11:00am - 12:00pm
Session 10: Applications III
----------------------------------------------------------------------------
Authors: S. Singh and R. Sloys
Organization: Xilinx
Title: Accelerating Adobe Photo Using the XC6200 FPGA
Authors: K. Weiss, R. Kistner, A. Kunzmann, W. Rosenstiel
Organization: University of Karlsruhe and University of Tubingen
Title: Analysis of the XC6000 Architecture for Embedded System Design
--
Jeffrey M. Arnold jmarnold@znet.com
10686 Mira Lago Terrace Tel: 619-547-9257
San Diego, CA 92131 Fax: 619-547-9010
USA
Article: 9456On 14 Mar 1998 00:36:00 GMT, "rk" <stellare@erols.com.NOSPAM> wrote: >it goes on to say that the "pc-based quicktools plus 7.0 offers schematic >engry, p&r, timing analysis, and 3rd party tool interfaces." - available >for $495. the quickworks package for windows available for $2,995. > >not recommending anything but it is in line with this discussion about eda >tools, platforms, and markets and a data point. > >and note that the synplicity program is available for quite a bit less $ >with a lot of other eda capability too, for this environment. interesting. But, does this have something to do with the long standing relationship between Synplicity and Quicklogic. I wouldn't be surprised if Quicklogic had some involvement at the start-up and so lever appropriate access to the product at low (or possibly zero?) cost. I presume it'll only support QL devices, and won't be upgradeable to other vendors, will it? StuartArticle: 9457
rk: : >it goes on to say that the "pc-based quicktools plus 7.0 offers schematic : >engry, p&r, timing analysis, and 3rd party tool interfaces." - available : >for $495. the quickworks package for windows available for $2,995. : > : >not recommending anything but it is in line with this discussion about eda : >tools, platforms, and markets and a data point. : > : >and note that the synplicity program is available for quite a bit less $ : >with a lot of other eda capability too, for this environment. interesting. stu: : But, does this have something to do with the long standing : relationship between Synplicity and Quicklogic. I wouldn't be : surprised if Quicklogic had some involvement at the start-up and so : lever appropriate access to the product at low (or possibly zero?) : cost. : : I presume it'll only support QL devices, and won't be upgradeable to : other vendors, will it? rk: hi stu, dunno any more than basically what i posted, got it from ee times, just ran across it as a datapoint on how one can design with the same tool for an order of magnitude less $ than on another platform (how's that for delicate wording). i assume that that package will only support q-logic stuff, but don't really now. it sounds similar to the way viewlogic does a lot of business. big $ on unix, less for pc, way less if a silicon dealer oem's it, restricted to their devices. doesn't xilinx incorporate some synopsys tools at least than standard price? i think i remember hearing a blurb about that and saw some reference to synopsys on xilinx' www site: The Foundation Express System incoporates advanced synthesis technology from Synopsys into the Foundation Standard System providing push-button and constraint driven synthesis for VHDL and Verilog. i have some experience with synplicity, but i have not yet targeted the ql devices. my ql3025 design was done in a schematic. perhaps someone up on the q-logic curve could better answer your questions. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9458
>>>>>>>>> Crack for Xilinx software deleted by Archive OwnerArticle: 9459
This is a multi-part message in MIME format. --------------733CC5D50035A2854133574D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit For all the "uncommon" applications so far presented, a modification of the original source followed by an M1 or PPR run with the guide option would have addressed the situations. Standard, readable source, no long run times, consistent placement and timing results. There may be applications that warrant "going behind the scenes" but they are SO few and SO far between that MOST users should consider the "standard" approache(s) first. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, 908) 996-0817 FAX: (908) 996-0817 --------------733CC5D50035A2854133574D Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ed McCauley Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Ed McCauley n: McCauley;Ed org: Bottom Line Technologies Inc. email;internet: edmccauley@bltinc.com title: President x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------733CC5D50035A2854133574D--Article: 9460
Achim Gratz <gratz@ite.inf.tu-dresden.de> writes:
> Is there such a thing as a programmable analog switch matrix/crossbar?
> I find digital ones (Lattice, Aptix FPIC), analog muxes and complete
> switch boxes for measurement equipment, some for analog mixers, but
> both extremely expensive. I'd like to use these with a Zetex TRAC
> device for lab exercises, so fmax=4MHz, crosstalk -60dB, Ron
> uncritical if tightly distributed. Before I forget, programmable
> resitors/capacitors would be a boon, too although I could use analog
> muxes for these.
Thanks to all who replied either to this forum or by email.
The first thing I learned was that I had searched for the wrong term,
searches for "crosspoint" turned out to be much more successful.
Here's the chips that fitted my description:
Harris HA456 120MHz 8x8 video crosspoint switch
Analog Devices AD8116 200MHz 16x16 video crosspoint switch
Mitel MT8816 45MHz 8x16 analog switch matrix
Maxim MAX456 35MHz 8x8 video crosspoint switch
SGS Thomson M3493 50MHz 12x8 CMOS crosspoint
Of these, only the latter two seem to fit into my budget. It appears
that iCube FPID can also be used to route low-voltage analog signals,
there's an application note on www.iCUBE.com to that effect. The main
benefit would be a much higher port density than any of the above at a
very nice price, but the signal range is probably too small. Aptix
doesn't seem to sell their FPIC as a chip anymore.
Much to my embarassment I found out not much later that right here in
Dresden a programmable analog circuit complete with passive elements
has been developed. I'm waiting for the data sheet to arrive, here's
the WWW description:
http://www.imsdd.fhg.de/ext/produkt/ads2/fpad/info_asb101_e.html
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 9461In fact, under $5K would be nice, but that doesn't seem doable... Anyway, this is what we're looking to do: -- Simulate VHDL -- Synthesize VHDL -- Place and route designs for, say, Xilinx -- Possibly schematic capture, although I could readily live without it -- Operate under Windows NT All of the tools count on the FPGA vendor's P&R tool (e.g., Xilinx M1), so as long as the given synthesis package will work with it (EDIF seems to be the interface format), I'm happy. So far I've looked at Accolade's PeakVHDL/PeakFPGA and Aldec's ActiveVHDL/ActiveSynthesis. Accolade has a very attractive price but unfortunately crashes pretty readily during simulation (major, major drawback!). Aldec is on the higher end of (our) price scale, but it's certainly a contender. Who else should I be looking at? Thanks... ---Joel KolstadArticle: 9462
Don Husby wrote:
[snip]
> Several Followups: Debate on why Xilinx would keep such a thing secret
> { They're just big meanies
> They are protecting their customers from reverse engineers.
> They're protecting themselves from better tool writers.
> }
[snip]
> Mention that NeoCad once hacked xilinx bitfile format
> { they were bought by xilinx. }
If NeoCad did it, so could someone else, at any time. Perhaps a better
solution would be to encode the bitstream in a manner that could not
be broken easily (e.g., encryption techniques). Decoders for such bit
streams could probably easily fit in a small area of silicon on the
FPGA. Then, if Xilinx was not too worried about software competition,
they could release an inexpensive program that converts open-format bit
streams into encrypted bit streams, allowing hobbyists and grad.
students, etc. to make their own experimental utilities as needed.
Furthermore, the bit stream could be encrypted at such a level of
security as to allow such data files to be stored and transmitted in
insecure manners despite the fact that the application itself is
confidential.
--Jim
Article: 9463Hi, i would like to develop an one semester project with an FPGA. This project should make something with advantages when compared to microcontrollers/microprocessors such as working with multiple sensors.... does anybody has an idea? Thanks! Antonio Rosa p.s: please email the idea mail: arosa@mail.telepac.ptArticle: 9464
go to www.acte.no/freecore -- Naveed zhangy <zhangy@isee.zju.edu.cn> wrote in article <350735E7.1F79@isee.zju.edu.cn>... > Who knows the ByteBlaster circult? >Article: 9465
Joel Kolstad <Joel.Kolstad@Techne-Sys.Com> wrote:
>In fact, under $5K would be nice, but that doesn't seem doable...
>Anyway, this is what we're looking to do:
>
>-- Simulate VHDL
>-- Synthesize VHDL
>-- Place and route designs for, say, Xilinx
>-- Possibly schematic capture, although I could readily live without it
>-- Operate under Windows NT
>
>So far I've looked at Accolade's PeakVHDL/PeakFPGA and Aldec's
>ActiveVHDL/ActiveSynthesis. Accolade has a very attractive price but
>unfortunately crashes pretty readily during simulation (major, major
>drawback!). Aldec is on the higher end of (our) price scale, but it's
>certainly a contender.
Joel, if you're not too driven by quality of results and don't mind
being locked into one particular company's FPGA/CPLDs, I think most
of the biggies (Xilinx, Altera, etc.) offer some sort of hacked
yet virtually free software. If you want quality of results and
support on that design path, you'll have to fork out some $$$ for
the commercial simulators & synthesis tools. (Actually I'm surprized
that EDA software pricing is a big issue for you. Your company
will spend a whole hell of a lot more on your salary, your benefits,
your workstation, your office, and the sysadmin involved. Paying
$5,000 or $35,000 for EDA tools is chump change compared to the other
costs involved with serious electronics R&D -- not to mention the
loses your company goes through when you're spending your time
supporting cheap tools. There are no free lunches.)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 6000+ other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 9466Peter wrote: > You are right with regard to effort versus cost of ready made P&R > software. > > But there are reasonable (if rather uncommon) cases where one might > want this info. > > You may want to modify just a part of a design, e.g. the logic in a > decoder. OTOH one can do that more elegantly using the RAM in a 4k > device but then one needs to build in an interface for loading the new > data, whereas the interface for the bitstream is already there. > > Peter. > This level of modification is supported in the toolset supplied by Xilinx. Once you have a routed design (or if you just have an unrouted XNF file), you can edit it in the layout editor and very easily modify a CLB or any part of one. Likewise you can edit the routing in a manual or semi-automatic way. As someone else in this thread mentioned, you then have a poorly documented design. Your schematic says one thing and the chip contains another. Kinda like doing hand modifications to the EPROM image of the executable from a "C" program. You may know what you are doing, but will you remember what you did in a month or a year? Rick Collins redsp@yahoo.comArticle: 9467
Very Smart, seems to work. Bye bye dongle, at last. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9468
Joel, Which version of NT were you trying to run PeakVHDL on? I have been using PeakVHDL (4.21a) on NT4 + service pack3 for some time now and it is more stable than some of Microsoft's own products. As described in the service pack 3 readme file you have to reinstall the service pack each time you install a new application. Just a though, Hans. In article <350C5FBE.15FDF455@Techne-Sys.Com>, Joel.Kolstad@Techne-Sys.Com says... >So far I've looked at Accolade's PeakVHDL/PeakFPGA and Aldec's >ActiveVHDL/ActiveSynthesis. Accolade has a very attractive price but >unfortunately crashes pretty readily during simulation (major, major >drawback!). >Thanks... > >---Joel KolstadArticle: 9469
On Sun, 15 Mar 1998 09:10:23 -0500, Ed McCauley <edmccauley@bltinc.com> wrote: >For all the "uncommon" applications so far presented... i seem to have missed the other "uncommon" applications that were presented - i guess that this is down to my news server. > a modification of the original source followed by an M1 or PPR run with the > guide option would have addressed the situations. thank you. i'm sure that there will be some people reading this thread who have never used the M1 tools, and we shouldn't forget the importance of providing an answer which may appear to be obvious to anybody else. > Standard, readable source, no long run times, >consistent placement and timing results. option (A): several source revisions. several revision directories. several failed guided designs, each with its own potentially different placement and timing results. option (B): one source revision. one PPR run. one placement, one timing result. several MEM files, as required, which can be patched into a single bit file. > MOST users should consider the "standard" approache(s) first. it would be foolish to consider anything else first. evan (ems@nospam.riverside-machines.com)Article: 9470
thanks for the info. i'll try to give it a go when i get some time. evanArticle: 9471
>If NeoCad did it, so could someone else, at any time. Perhaps a better >solution would be to encode the bitstream in a manner that could not >be broken easily (e.g., encryption techniques). Decoders for such bit >streams could probably easily fit in a small area of silicon on the >FPGA. That's right, but a) the *encryption* algorithm would be present in Xilinx's tools b) there are firms who for say $20k-$100k will reverse engineer an entire ASIC and give you the netlist So it would be possible to reverse engineer not only the encryption (by disassembly of the P&R software) but also the silicon layout. One can only speculate how Neocad did it but disassembling the P&R tools would be the obvious starting point. IMO one can get very good security with a RAM-based FPGA. In most applications the FPGA is *not* performing some incredibly amazingly complex patented function, and it would be easier to do one's own design. And if the app is really sensitive then one can load the design into the device and have it battery-backed. Make sure there are no spikes around :) Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9472
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 9473
========================================================================
SUMMER STUDENT POSITION
Compilers for reconfigurable FPGA-based computing
Ricoh Silicon Valley will have a summer position for a talented graduate
student in computer science or electrical engineering to assist a small
team of hardware, software and algorithm specialists in research in
novel FPGA-based reconfigurable computing. The student will assist in
compiler development and testing for applications in parallel image pro-
cessing.
Background in the following areas is highly desirable:
* C/UNIX
* image processing algorithms
* compilers for digital signal processors
* gcc compilers
* SUIF (Stanford University Intermediate Format)
* parallel processing
The period of employment is somewhat flexible to meet the needs of
the
successful candidate, but is expected to begin in late May or early
June,
and end in late August or early Sepetember, 1998. Salary is
competitive
and commensurate with experience.
To apply:
Please send a (paper) cover letter, current transcript, names and
phone numbers and e-mail addresses of two people familiar with your
work, plus any supporting material (code, papers, projects) to:
Dr. David G. Stork
California Research Center
Ricoh Silicon Valley
2882 Sand Hill Road #115
Menlo Park, CA 94028-7820
(Please do not e-mail your application.)
We will attend FCCM'98 in Nappa Valley, CA April 15-17, and would be
happy to meet with applicants at that time.
The California Research Center of Ricoh Silicon Valley, Inc. is a small
lab focussing on information technologies for future office automation
environments, such as image compression, uses of the world wide web and
document technologies. The lab is very close to Stanford University and
in easy driving distance to San Francisco, San Jose, Santa Cruz, and
many Bay Area natural and cultural attractions.
Ricoh Silicon Valley is an equal-opportunity employer and encourages
qualified women and minorities to apply. Applicants must already be
qualified to work in the USA. Further information is available at:
http://www.crc.ricoh.com.
Specific questions can be addressed to: stork@rsv.ricoh.com.
========================================================================
Article: 9474Nick Hartl wrote: Most closely guarded secret!!! Xilinx has two concerns. 1. Customers do not want their designs reversed engineered. If you know what the bit pattern does you have the design. > 2. Xilinx's own position. If what the bit steam did to the part was > known, > making a drop in replacement part would be a lot easier. > This is really the same as 1. above, concern for our customers' intellectual property. The designer who created the FPGA-based design obviously knows what's going on in the design, and the GUI can show it in excruciating detail. Giving him/her the meaning of gezillion configuration bits adds no new information. Only the rip-off artist would profit... Somebody mentioned reverse engineering. Obviously, NeoCAD did it. But remember that they were ( are ) a bunch of very experienced engineers, and they spent a few dozen man-years ( "person-years" to be politically correct ) on their software effort. And they found out that it is not a viable stand-alone business. So, if you have the time and a few million dollars, and nothing better to do, you can do it. Otherwise it's much cheaper to buy the software.. Peter Alfke, Xilinx Applications
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