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Messages from 9125

Article: 9125
Subject: Re: Atmel SPROMs for Xilinx
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Mon, 23 Feb 1998 02:48:52 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
>
> Rick, there really is no problem. Just look at their data sheet. They
> use our nomenclature.
> If I remember right, they use our Vpp pin differently, and they tend to
> be slower than our parts, but that is no problem at 1 MHz configuration
> rate ( but may be a worst-case problem at 8 MHz)
> A long time ago, Atmel was also confused about the programming of the
> reset polarity, but that must have been resolved long time ago.
> 
> Enjoy their reprogrammability.

... and they need a faster Vcc ramp up.

Gerhard

-- 
on the air:    DK4XP
in the air:    D-8551
Article: 9126
Subject: Good book for FPGA starter?
From: ai123@FreeNet.Carleton.CA (Steven J. Tucker)
Date: 23 Feb 1998 01:51:14 GMT
Links: << >>  << T >>  << A >>

Does anyone have a suggestion for a really good tect on FPGA for a beginner?

I'm multistep process of going from code to a working device is not
 well explained in any software I have tried.  Also I would like a book
 that explains the difference between using VHDL and other methods or
 creating a device.

Steve
--
   * * *   Author of Imagic and APE - The Atari Peripheral Emulator!   * * * 
   * * *       Turn your 8-bit Atari into a powerhouse with APE!       * * *
  *  *  *         Ape Homepage: http://www.nacs.net/~classics         *  *  *
 !! Request my *FOR SALE* LISTING OF CLASSIC VIDEO GAME STUFF !! 2000+ Lines !!
Article: 9127
Subject: => AZ : Digital FPGA Design/Modem Tech => AZ
From: "Hi Tech Jobs" <clientserver@msn.com>
Date: Sun, 22 Feb 1998 23:37:07 -0800
Links: << >>  << T >>  << A >>
Princeton Information < www.princetoninformation.com > is seeking
Ten (10) Senior Digital Design Engineers............

Digital FPGA Hardware Engineer -High Speed Digital Modem Technology

Job Description:

You will participate in the design and development of a flexible
communications system breadboard utilizing FPGA's (ASIC) for
Motorola's Celestri (tm) Modem Technology development program.
These are specialized high-speed modems (Mbps) installed in satellites.

Celestri is a multi-year, $13 billion project that will provide
high-bandwidth
packet switching - connections (e.g., internet) in outer SPACE!!!

Celestial Data Communications for the 21st Century!!!

BS/MS in Electrical Engineering +4 to 6 years of experience required.
Familiarity with FPGA based design limitations and mitigation methods.
Willingness to accept responsibility & technical challenge
Ability to work independently and on a team
Focus on customer satisfaction

EMAIL your resume TODAY!!! ==> azjobs@usa.net

Location:  Phoenix/ Chandler,  AZ
Duration:  Temp to Permanent
Pay Rate: $55,000  => $85,0000

Also, Temp to Perm - "Try it you'll like it!"

See our Website: < www.princetoninformation.com >

Digital FPGA Hardware Designer - High Speed Digital Design - Modem
Technology

We have an opportunity for an individual who has done some complex Circuit
Board/FPGA design to work at a place where cutting edge technology is the
norm, and one of the very best design staffs in the country awaits.

This position is for someone who has between 4-10 years of high performance
custom circuit design under his/her belt.  You will be working on some of
the "neatest" projects you've ever seen, and will become a stellar hardware
designer for your efforts.

Some of the "buzz":  We are looking for High Speed Digital Designers, Modem
Technology development.......

Experience with PLD's, FPGA's (ASIC), complex designs (nothing
simple at this place), understands timings, etc...  Not a person who still
needs a lot of instruction, we are hoping to find an individual who can
stand alone and bring a project in from scratch to production.

Our client is located in Chandler, Arizona.

Salary will be very nice, they're not cheap, as
they're looking for the best we can bring in.

Please E-mail your resume TODAY===> azjobs@usa.net





























Article: 9128
Subject: FS: Universal device programmer
From: acooney@netcom.com (Alan Cooney)
Date: Mon, 23 Feb 1998 07:44:47 GMT
Links: << >>  << T >>  << A >>
E.E. Tools AllMax universal programmer (EPROMs, EEPROMs, serial
EEPROMs, PALs, GALs, PLDs, Flash, micros, tests logic ICs, etc.,
etc.) with AllMax+ parallel port upgrade.  Also has a separate
socket on top for testing DRAM and SRAM modules.  Works with your
parallel port *or* with an ISA card (both interfaces included).
Has a 48-pin DIP ZIF socket on top.  Includes programmer, parallel
port module, parallel port (Centronics) cable, PC card, ribbon
cable, power supply, manual, and software. In excellent electrical
and physical condition (works great, looks great).

I'm moving, and need the money more than the universal programmer.
Check out the features on the E.E. Tools website: www.eetools.com
(keep in mind that this is the equivalent of the Allmax+, since it 
has the parallel port interface included).

Asking price:  $425 (includes shipping/C.O.D.)

Article: 9129
Subject: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
From: Koenraad Schelfhout VH14 8993 <ksch@sh.bel.alcatel.be>
Date: Mon, 23 Feb 1998 08:53:19 +0100
Links: << >>  << T >>  << A >>
My first impressions with 8.2 compared to 8.11 :
  - results are somewhat better in case you have fitting problems
    (my case is a 10K20)
  - it runs somewhat slower

-- 

 Koenraad SCHELFHOUT

 Switching Systems Division          http://www.alcatel.com/
 Microelectronics Department - VH14     _______________
________________________________________\             /-___
                                         \           / /
 Phone : (32/3) 240 89 93                 \ ALCATEL / /
 Fax   : (32/3) 240 99 47                  \       / /
 mailto:ksch@sh.bel.alcatel.be              \     / /
_____________________________________________\   / /______
                                              \ / /
 Francis Wellesplein, 1                        v\/
 B-2018  Antwerpen
 Belgium
Article: 9130
Subject: Re: Atmel SPROMs for Xilinx
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 23 Feb 1998 08:44:47 -0800
Links: << >>  << T >>  << A >>
Gerhard Hoffmann wrote:

> Peter Alfke wrote:
> >
> > Rick, there really is no problem. Just look at their data sheet.
> They use our nomenclature.
> > If I remember right, they use our Vpp pin differently, and they tend
> to
> > be slower than our parts, but that is no problem at 1 MHz
> configuration
> > rate ( but may be a worst-case problem at 8 MHz)
>  
>
> ... and they need a faster Vcc ramp up.
>
> Gerhard
>  

Let me explain this fundamental problem in more detail:

During power-up and during reconfiguration, we strongly recommend that
all INIT pins be interconnected and also be used to reset the SPROM.
That takes care of any possible differences in the wake-up and internal
"housecleaning" times of the FPGA(s). INIT goes High when the last of
the FPGAs is ready, and the SPROM is being held reset as long as
possible.

But what if the SPROM power-on-reset is the longest in the system,
longer than that of any FPGA ? Then the interconnect of the INIT pins
doesn't help. The lead FPGA will start sending out CCLK, whether the
SPROM has finished its power-on routine or not.

That's what Gerhard was referring to. If Vcc rises slowly, the Atmel
SPROM may have the highest Vcc-detect threshold in the system, and thus
start its power-on-reset so late that the above mentioned disaster
occurs.

All such problems can, of course, be avoided by the use of a precision
Vcc-detect circuit for <$1 from specialists like Maxim, Linear, Dallas,
TI or Motorola.

Peter Alfke, Xilinx Applications
 

Article: 9131
Subject: MPEG video tutorial
From: "John Wiseman" <johnw@dmsl.hitachi.com>
Date: Mon, 23 Feb 1998 12:25:57 -0500
Links: << >>  << T >>  << A >>
I posted a recent MPEG video compression tutorial that I wrote
to my website at http://members.aol.com/johnw39038/index.htm
if you are interested.  There's also a couple of QEX articles on
DSP FIR filter implementations, and VHDL/FPGA chip design
as related to amateur radio applications.  Enjoy...

jw

========================================================
John Wiseman
Senior Researcher
Hitachi America, Ltd., Digital Media Systems Laboratory
Princeton, NJ
Email: johnw@dmsl.hitachi.com
Voice: (609)-520-0071 ext. 18  Fax: (609)-520-8953
Amateur Radio: KE3QG
========================================================


Article: 9132
Subject: Re: Mach211 fpga programming
From: William White <will@fpga.demon.co.uk>
Date: Mon, 23 Feb 1998 17:48:39 +0000
Links: << >>  << T >>  << A >>
The JEDEC U and E fields are optional fields in a JEDEC file and are not
part of the JEDEC-3C (JESD3-C) standard.

The E field allows special feature fuses that do not affect the logic
function of the device to be specified in JEDEC files. The E field reads
left to right for the purpose of checksum calculations.

In article <693cda$j1d$1@news.worldonline.nl>, Johan Kortenhoeven
<jkorten@worldonline.nl> writes
>Is there somebody who is familiar with the lines
>starting with an "E" is the programming file of a mach 211
>device.
>I am particular interested in the checksum calculations.
>
>
>
>

-- 
William White
Article: 9133
Subject: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
From: z80@ds.com (Peter)
Date: Mon, 23 Feb 1998 18:21:34 GMT
Links: << >>  << T >>  << A >>
Hello,

Sorry for the repost but nobody seems to know the answer to this
simple question.

I have been using Viewlogic 4 (DOS) and XACT6 PPR (DOS) for XC3000
designs.

I have been attaching the above attrobutes to nets in the circuit, to
force allocation to either Long Lines or to specify a maximum skew
time, respectively. These are described in the Xilinx Viewdraw/LCA
docs.

I have seen some strange problems, never present in the old APR, and
it has occurred to me that XACT6/PPR might be ignoring these net
attributes.

I know that the Xilinx preferred method today is timespecs, but this
is a nice simple way to do it.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 9134
Subject: Re: Correlation implementation...
From: nics@citr.removeme.itc.com.au (Nic)
Date: Tue, 24 Feb 1998 01:38:19 GMT
Links: << >>  << T >>  << A >>
In article <34F0C991.F60D0BBA@now-online.com>, e.kobal@now-online.com wrote:
>We are looking to implement signal arrival time detection using the
>correlation method.  Our design involves a steady stream of 8-bit
>samples at a sampling rate of 20 Msps.  Our pattern that we are
>attempting to match is 40 samples wide.  Now the problem we have arrived
>at is the following:  we need to perform a 40x8 bit matrix
>multiplication.  This is only the root of our design problem, since our

Is this not a classic application of the "FIR" filter? A 40 tap FIR is quite
possible to implement and much has been written on the subject. 20Msps should
be easy.  For information on the implementation of FIR filters
(using "proper" coefficients) see for instance the Altera website (look for
Application Note 73).

A DSP solution will be difficult, you would be hard pressed to get a result
in and out of the DSP in the 50nS you have available, let alone do a 40 tap
FIR.

>application is multichannel.  We are not sure whether our design would
>work best using a standard DSP, or whether we should use an FPGA to
>allow for multiplication in parallel.  Any information would be much
>appreciated.
>
>Thank you,
>
>Erik Kobal, Cleveland State University
>
Article: 9135
Subject: Re: Atmel SPROMs for Xilinx
From: "Martin Mason" <mtmason@ix.netcom.com>
Date: Mon, 23 Feb 1998 22:17:25 -0800
Links: << >>  << T >>  << A >>


Peter Alfke wrote in article <34F1A724.AFE62BD0@xilinx.com>...>
>That's what Gerhard was referring to. If Vcc rises slowly, the Atmel
>SPROM may have the highest Vcc-detect threshold in the system, and thus
>start its power-on-reset so late that the above mentioned disaster
>occurs.
>
>All such problems can, of course, be avoided by the use of a precision
>Vcc-detect circuit for <$1 from specialists like Maxim, Linear, Dallas,
>TI or Motorola.

Disaster! Disaster !  The sky is falling in!!!!

We have a specifically designed LOW POR threshold, very fast active from
POR and  additionally have a  READY pin on our 512K and 1M devices to
further simply system design.

But you don't have to believe me - we will let you decide for yourself by
happily shiping you a couple of FREE samples - for more details....

http://www.atmel.com/atmel/products/prod22.htm

Martin Mason
Atmel Corp.




Article: 9136
Subject: ┐Altera to Xilinx? ┐Max+Plus II to Foundation??
From: "EUG" <feviro@eug.upv.es>
Date: 24 Feb 1998 08:02:45 GMT
Links: << >>  << T >>  << A >>
Hi 

I'm working in Max+plus II of Altera and now I want change to Foundation of
Xilinx. 
Somebody knows some program to make that ??


Felip Vicedo Roman
Escuela Universitaria de Gandia
Universidad PolitÚcnica de Valencia
e-mail: feviro@eug.upv.es
Article: 9137
Subject: Galois field
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 24 Feb 1998 11:42:28 +0200
Links: << >>  << T >>  << A >>
Long ago someone sent a posting which included pesudorandom
number generators. That person represented a model and then
extended it to a Galois field. Do I remember correctly? If
yes, would you please tell some links, books etc?

Utku
Article: 9138
Subject: Re: AZ - JOB => Digital FPGA Design Engineers needed...........
From: ems@see.sig (E.M. Shattock)
Date: Tue, 24 Feb 1998 13:07:02 GMT
Links: << >>  << T >>  << A >>
This isn't a jobs newsgroup. The 'comp.lang' newsgroups aren't job
newsgroups, either.
I suggest that you download a current newsgroup list, and  look for
the word 'JOB'.
Article: 9139
Subject: Re: MPEG video tutorial
From: Sam Falaki <falaki@nospam.videotron.ca>
Date: Tue, 24 Feb 1998 14:15:02 GMT
Links: << >>  << T >>  << A >>
Very nice, well explained.  Thanks John.

Regards,

Sam

John Wiseman wrote:

> I posted a recent MPEG video compression tutorial that I wrote
> to my website at http://members.aol.com/johnw39038/index.htm
> if you are interested.  There's also a couple of QEX articles on
> DSP FIR filter implementations, and VHDL/FPGA chip design
> as related to amateur radio applications.  Enjoy...
>
> jw
>
> ========================================================
> John Wiseman
> Senior Researcher
> Hitachi America, Ltd., Digital Media Systems Laboratory
> Princeton, NJ
> Email: johnw@dmsl.hitachi.com
> Voice: (609)-520-0071 ext. 18  Fax: (609)-520-8953
> Amateur Radio: KE3QG
> ========================================================



Article: 9140
Subject: Survey - Proto Board for Xilinx FPGA
From: ecla@world.std.com (alain arnaud)
Date: Tue, 24 Feb 1998 14:21:49 GMT
Links: << >>  << T >>  << A >>


My company will shortly be respinning the prototype board for Xilinx FPGAs.
We are requesting your help in choosing the appropriate feature set.
Email your responses to arnaud@ecla.com

1. Board Form Factor
       Do you prefer 
                 (A) standalone board or 
                 (B) a board that plugs into a PC slot?

2. Bus Interface
       If PC size board, do you prefer 
                  (A) an ISA interface or 
                  (B) a PCI interface or 
                  (C) No interface, just power and ground.

3. Bus Interface Controller
       Do you require the board to incude:
                  (A) Separate PCI bus controller 
                  (B) Separate ISA bus controller
                  (C) the device should be able to drive the bus
                  (D) No bus controller

4. Xilinx FPGA
	Should the device be 
                  (A) directly soldered to the board or 
                  (B) to a small module that's plugged into a connector on
the board ?

5. If the device is on the board, which device would you prefer?

6. What package and pincount?

7. Should the board include a microcontroller? 
                  (A) Yes 
                  (B) No

8. What kind of connector should be used to bring out the IO?

9. How large should the wire-wrap area be?

10. The device will be able to be programmed through a serial prom. 
                  (A) Include a parallel Flash device?
                  (B) Include a jtag (boundary scan) connector
                  (C) Include a xchecker download/readback connector
                  (D) If a micro is on the board, should the micro be able
to program the device?


11. Other featgures or comments


Thanks for you help.

Alain Arnaud
arnaud@ecla.com

Article: 9141
Subject: Re: Correlation implementation...
From: John McCluskey <jqm@cam.org>
Date: Tue, 24 Feb 1998 11:13:49 -0500
Links: << >>  << T >>  << A >>


Nic wrote:

> In article <34F0C991.F60D0BBA@now-online.com>, e.kobal@now-online.com wrote:
> >We are looking to implement signal arrival time detection using the
> >correlation method.  Our design involves a steady stream of 8-bit
> >samples at a sampling rate of 20 Msps.  Our pattern that we are
> >attempting to match is 40 samples wide.  Now the problem we have arrived
> >at is the following:  we need to perform a 40x8 bit matrix
> >multiplication.  This is only the root of our design problem, since our
>
> Is this not a classic application of the "FIR" filter? A 40 tap FIR is quite
> possible to implement and much has been written on the subject. 20Msps should
> be easy.  For information on the implementation of FIR filters
> (using "proper" coefficients) see for instance the Altera website (look for
> Application Note 73).
>
> A DSP solution will be difficult, you would be hard pressed to get a result
> in and out of the DSP in the 50nS you have available, let alone do a 40 tap
> FIR.
>

Well, _maybe_ it's an FIR problem.  Signal arrival time detection is only
partlysolved by using an FIR filter, since peak detection on the output only
gives you
the arrival time to the nearest sample.  If you want subsample resolution, it's
much
easier to get the result by processing the data in the Fourier domain.   Signal
arrival type problems are very often a periodic process (it happens
periodically),
so you could use a DSP chip with appropriate data buffering hardware.   The
original poster is looking to find a 40 sample signal that arrives with an
unknown
periodic rate.  If the rate is low enough, and the location uncertainty is small,
then
a DSP processor could do the job.  On the other hand, an FIR correlator might
be appropriate if the search space is too much for a DSP chip.

I would submit that the original problem as posed is insufficiently specified to
determine an optimal solution.   Perhaps Mr Kobal can supply more information?
For example, is the signal being sought a binary sequence, or multivalued?

John McCluskey
Lucent Technologies


> >application is multichannel.  We are not sure whether our design would
> >work best using a standard DSP, or whether we should use an FPGA to
> >allow for multiplication in parallel.  Any information would be much
> >appreciated.
> >
> >Thank you,
> >
> >Erik Kobal, Cleveland State University
> >



Article: 9142
Subject: PLL design with Xilinx 4kseries
From: Neurotech@t-online.de (Neurotech GmbH)
Date: 24 Feb 1998 16:36:06 GMT
Links: << >>  << T >>  << A >>
Has anybody out there already done a completely digital PLL inside an FPGA
?
I have to do an XC4028EX and one part of it shall be a programmable PLL
with
an input clock of about 300kHz and an output of about 10Mhz. But sometimes 
I need exactly 9.998 MHz, sometimes 10.011 and so on, as precise as
possible.

Any idea ?
Holger Schuppan

Neurotech@T-Online.de
Article: 9143
Subject: Re: buft and bufe
From: John McDougall <"john_mcdougall[NO SPAM]"@geocities.com>
Date: Tue, 24 Feb 1998 14:28:29 -0500
Links: << >>  << T >>  << A >>

--------------0BE633ADE9983111DFB2A6B7
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Frank wrote:

> Can anybody tell me what's the difference between BUFT and BUFE in Aldec
> Foundation Series software? I use it to do design with Xilinx device.



--
************** Remove [ANTI_SPAM] to reply **************

BUFE is enabled when the E pin is high
BUFT is tristated when the T pin is high.

The only difference between the two is an inversion of the control pin.

--------------0BE633ADE9983111DFB2A6B7
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<HTML>
Frank wrote:
<BLOCKQUOTE TYPE=CITE>Can anybody tell me what's the difference between
BUFT and BUFE in Aldec
<BR>Foundation Series software? I use it to do design with Xilinx device.</BLOCKQUOTE>
&nbsp;
<PRE>--&nbsp;
************** Remove [ANTI_SPAM] to reply **************</PRE>
BUFE is enabled when the E pin is high
<BR>BUFT is tristated when the T pin is high.

<P>The only difference between the two is an inversion of the control pin.</HTML>

--------------0BE633ADE9983111DFB2A6B7--

Article: 9144
Subject: Re: Correlation implementation...
From: hgirard@nsicomm.com (H Girard)
Date: Tue, 24 Feb 1998 20:56:58 GMT
Links: << >>  << T >>  << A >>
Erik Kobal <ekobal@now-online.com> wrote:

>We are looking to implement signal arrival time detection using the
>correlation method.  Our design involves a steady stream of 8-bit
>samples at a sampling rate of 20 Msps.  Our pattern that we are
>attempting to match is 40 samples wide.  Now the problem we have arrived
>at is the following:  we need to perform a 40x8 bit matrix
>multiplication.  This is only the root of our design problem, since our
>application is multichannel.  We are not sure whether our design would
>work best using a standard DSP, or whether we should use an FPGA to
>allow for multiplication in parallel.  Any information would be much
>appreciated.

>Thank you,

>Erik Kobal, Cleveland State University

You seem to be looking for a soft decision correlation . We use fpga's
to do this . At that speed , I believe you are best to use fpga's.
Some old app notes by trw  (now Raytheon ) may still be available.

Henri 
hgirard@nsicomm.com

Article: 9145
Subject: Re: Correlation implementation...
From: hgirard@nsicomm.com (H Girard)
Date: Tue, 24 Feb 1998 23:30:17 GMT
Links: << >>  << T >>  << A >>
Erik Kobal <ekobal@now-online.com> wrote:

>We are looking to implement signal arrival time detection using the
>correlation method.  Our design involves a steady stream of 8-bit
>samples at a sampling rate of 20 Msps.  Our pattern that we are
>attempting to match is 40 samples wide.  Now the problem we have arrived
>at is the following:  we need to perform a 40x8 bit matrix
>multiplication.  This is only the root of our design problem, since our
>application is multichannel.  We are not sure whether our design would
>work best using a standard DSP, or whether we should use an FPGA to
>allow for multiplication in parallel.  Any information would be much
>appreciated.

>Thank you,

>Erik Kobal, Cleveland State University

Sounds like you are trying to do soft decision correlation . Some old
app notes by trw (now Raytheon) described this. We use fpga's.
You can email me for questions. 
H Girard
hgirard@nsicomm.com


Article: 9146
Subject: Re: Correlation implementation...
From: Jack Lai <jwlai@mmmpcc.org>
Date: Tue, 24 Feb 1998 18:12:58 -0600
Links: << >>  << T >>  << A >>
H Girard wrote:
> 
> Erik Kobal <ekobal@now-online.com> wrote:
> 
> >We are looking to implement signal arrival time detection using the
> >correlation method.  Our design involves a steady stream of 8-bit
> >samples at a sampling rate of 20 Msps.  Our pattern that we are
> >attempting to match is 40 samples wide.  Now the problem we have arrived
> >at is the following:  we need to perform a 40x8 bit matrix
> >multiplication.  This is only the root of our design problem, since our
> >application is multichannel.  We are not sure whether our design would
> >work best using a standard DSP, or whether we should use an FPGA to
> >allow for multiplication in parallel.  Any information would be much
> >appreciated.
> 
> >Thank you,
> 
> >Erik Kobal, Cleveland State University
> 
> Sounds like you are trying to do soft decision correlation . Some old
> app notes by trw (now Raytheon) described this. We use fpga's.
> You can email me for questions.
> H Girard
> hgirard@nsicomm.com
H Girard
Can you tell me what"s is app note numbers, and where can I get these
notes.

Jack Lai

Article: 9147
Subject: Leonardo/VHDL and pullups in FPGAs.
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 25 Feb 1998 00:46:06 GMT
Links: << >>  << T >>  << A >>
I just posted a note asking how to add pullups in Xilinx FPGAs.
Well, I think I have answered my own question, however, I'd like
to know your thoughts.  The problem is that I could not place
a pullup on an INPUT node.  (Leonardo wouldn't let me)  I am 
using direct port mapping to do this.

However, if I redefine the signal as an "inout" it works fine.
Although this isn't really what the signal is, I don't think
there is much harm in doing this.  Any thoughts?

   Cheers,
   Jake

--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 9148
Subject: Re: ┐Altera to Xilinx? ┐Max+Plus II to Foundation??
From: sam@palmnet.net (Steve Mitchell)
Date: 25 Feb 1998 04:21:14 GMT
Links: << >>  << T >>  << A >>
In article <01bd40fa$242ef220$52912a9e@cabezon>, feviro@eug.upv.es says...
>
>Hi 
>
>I'm working in Max+plus II of Altera and now I want change to Foundation of
>Xilinx. 
>Somebody knows some program to make that ??
>
>
>Felip Vicedo Roman
>Escuela Universitaria de Gandia
>Universidad PolitÚcnica de Valencia
>e-mail: feviro@eug.upv.es

The Exemplar synthesis tools allow you to specify an input technology
and an output technology to do such translations.  I've never done it,
but it looks like it should be fairly painless.  All disclaimers apply!

Steve Mitchell

Article: 9149
Subject: Re: Leonardo/VHDL and pullups in FPGAs.
From: sam@palmnet.net (Steve Mitchell)
Date: 25 Feb 1998 04:24:22 GMT
Links: << >>  << T >>  << A >>
In article <6cvpke$k62$1@vixen.cso.uiuc.edu>, janovetz@ews.uiuc.edu says...
>
>I just posted a note asking how to add pullups in Xilinx FPGAs.
>Well, I think I have answered my own question, however, I'd like
>to know your thoughts.  The problem is that I could not place
>a pullup on an INPUT node.  (Leonardo wouldn't let me)  I am 
>using direct port mapping to do this.
>
>However, if I redefine the signal as an "inout" it works fine.
>Although this isn't really what the signal is, I don't think
>there is much harm in doing this.  Any thoughts?
>
>   Cheers,
>   Jake
>
>--
>   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
> University of Illinois | your eyes turned skyward, for there you have been,
>                        | there you long to return.     -- da Vinci
>        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html

Check on the Xilinx web page for doing this.  I recall having seen an
app note on doing this within their help pages.

Steve Mitchell



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