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Hi Iam planning to port leon (open-source processor) in xilinx virtex-II chip, bypassing power PC. Still May it be possible to use the resources like ethernet transciever, audio codec available in the board. Can I use my own tool chain with rtos like uclinux, sparc-linux-gcc etc and run the code in leon ported in xilinx chip, development board. PrakashArticle: 100126
Hi, I just saw the following article that claims that Xilinx has unveiled a PCI Express starter kit based on Spartan-3 with a list price of $349. http://www.eetimes.com/news/design/showArticle.jhtml;jsessionid=O1GNQGAF2UNDAQSNDBECKH0CJUMEKJVN?articleID=184425812 This seems interesting, has anyone heard anything more about this board? (There does not seem to be any information on Xilinx' website.) /AndreasArticle: 100127
HI Andreas,
I have been to the SILICA seminar on low cost PCI a
couple of weeks back and we got to play with the first eight of the
production, the board was fairly basic and has some leds a bit of ram and a
S31000 plus a simple dac for Video, not much else really apart from the
xilinx PCIe core takes just over half the chip, but it does work had a
simple program running on the board in the LAB.
Board is produced by AVNET for XILINX.
REGARDS
"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message
news:e0t6el$l1j$1@news.lysator.liu.se...
> Hi, I just saw the following article that claims that
> Xilinx has unveiled a PCI Express starter kit based on Spartan-3
> with a list price of $349.
>
> http://www.eetimes.com/news/design/showArticle.jhtml;jsessionid=O1GNQGAF2UNDAQSNDBECKH0CJUMEKJVN?articleID=184425812
>
> This seems interesting, has anyone heard anything more about this
> board? (There does not seem to be any information on Xilinx'
> website.)
>
>
> /Andreas
Article: 100128Thank you very much for your useful tips! GuidoArticle: 100129
This avnet PCIe board was supposed to be using S3e and it had target date june 2005. looks like it is finally ready! there are WAU 8 boards made! maybe Avnet can make some more til june 2006 so the delay would be only 1 year. AnttiArticle: 100130
I start to wonder if there is something weird with my design. I use a spartan 3 (4k), vhdl, and I suspect the synthesizer takes too long time and I would like to compare with other users. My design was completely done (all phases) in about 40minutes on a reasonable new pc (P4 2.8GHz) with lot of RAM (2.75GB). The synthesis phase used about 30 of these minutes. I suspect that one of my blocks (cpu interface) could take very long time cause of some insanely long std_locic_vectors(2047:0) used for i/o area where 95% of the bits are optimized away. It's kind of hard to test without doing much work with the design. There is no swapping going on on the HD. How fast is yours? Any other experiences what causes synthesis to go slow? CheersArticle: 100131
Doh! I forgot to mention that my fpga is only ~20-30% full.Article: 100132
Hi,
At the seminar it was claimed that 1000+ boards were in production so we
will see when it is released.
REGARDS
"Antti" <Antti.Lukats@xilant.com> wrote in message
news:1144138241.151500.56140@i40g2000cwc.googlegroups.com...
> This avnet PCIe board was supposed to be using S3e and it had target
> date june 2005.
>
> looks like it is finally ready! there are WAU 8 boards made!
> maybe Avnet can make some more til june 2006 so the delay would be only
> 1 year.
>
> Antti
>
Article: 100133Paul Hartke a =E9crit : > John Williams' "Partial Reconfiguration on Xilinx Devices" email list is > another resource: > http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ > > The archive is available here: > http://www.itee.uq.edu.au/~listarch/partial-reconfig/ > > Denaice wrote: > > > > Does someone have a working design using an ICAP in Virtex-4 ? We are > > trying to send a difference-based partial bitstream to it by using > > GPIOs but it doesn't seem to work. (The bitstream is ok, it works in > > iMPACT by JTAG) I already know this list, but it doesn't answer my question...Article: 100134
prakash.na@gmail.com wrote: > Hi all, > Iam trying to develop an embedded mp3 player. I compiled...and > installed in linux(FC4) + pentium platform. Now I want to prototype in > xilinx development board. There are doubts like, > > 1)How can I estimate the processing power, fpu, memory, clock > frequency, RTOS, cache requirements, like whether they are required or > not, if so, how much. > > 2)Im thinking to use the leon processor (open source) instead of power > pc (hardcore) in the xilinx chip. If I port my own processor in xilinx, > could I be able to use the resources like ethernet transciever, audio > codec etc which are built in the board, connected to power pc > processor (like the software, device driver everything is designed with > a view of power PC.) Well, you need some schematic on how the external devices are conneced. Then you'd need a manual on these devices. The source for their drivers would help, otherwise you'd have to think a bit harder. > > 3)In the development boards, there is a flash prom for storing > configurations is available. Is it possible to use it as a place for > storing my boot code portion so that I can download the image from pc > and put it in RAM and run from the same. Usually, I'd expect that. ReneArticle: 100135
I want to create macro bus.
How I understood, it is necessary in FPGA Editor to add 2 SLICE
("EDIT->ADD").
Then to put together them between itself through node. But not clearly
what
outputs SLICE_1 is it necessary to conduct node from and on what
entrances
SLICE_2 ?
Article: 100136It isn't a silly price for a one off. Silica are the distributor in the UK but you will have to ask for a price and they may have a minimum order quantity. John Adair Enterpoint Ltd. - Home of Swinyard1. The DSP Virtex-4 module. http://www.enterpoint.co.uk "maxascent" <maxascent@yahoo.co.uk> wrote in message news:19-dnZ8TrsB0E7DZRVn_vA@giganews.com... >I would like to obtain a Virtex II Pro 20K part in FG676 package for > prototyping. I am in the UK and have seen the part on Digikey for around > $320. Does seem like a good price or does anyone know of a cheaper > alternative. Or would it be possible to get a one off sample? > > Cheers > > JonArticle: 100137
We are have reports similar to this from some of our customers. You should raise a a case with Xilinx. The more cases that are raised the more likely something will be done. Service pack 3 is out and supposed to be improving the situation but not totally. So if you don't have it I would recommend you try it and see if it improves. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board. http://www.enterpoint.co.uk "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message news:e0ta47$1c9$1@news.netpower.no... >I start to wonder if there is something weird with my design. I use a >spartan 3 (4k), vhdl, and I suspect the synthesizer takes too long time and >I would like to compare with other users. My design was completely done >(all phases) in about 40minutes on a reasonable new pc (P4 2.8GHz) with lot >of RAM (2.75GB). The synthesis phase used about 30 of these minutes. I >suspect that one of my blocks (cpu interface) could take very long time >cause of some insanely long std_locic_vectors(2047:0) used for i/o area >where 95% of the bits are optimized away. It's kind of hard to test without >doing much work with the design. > There is no swapping going on on the HD. > > How fast is yours? > > > Any other experiences what causes synthesis to go slow? > > Cheers > >Article: 100138
SP3 is already installed :) Still very slow. I did not see anything about speed improvement in the changes list. "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1144147793.54780.0@dyke.uk.clara.net... > We are have reports similar to this from some of our customers. You should > raise a a case with Xilinx. The more cases that are raised the more likely > something will be done. > > Service pack 3 is out and supposed to be improving the situation but not > totally. So if you don't have it I would recommend you try it and see if > it improves. > > John Adair > Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development > Board. > http://www.enterpoint.co.ukArticle: 100139
Hi folks, I have to speed up configuration of 2 FPGAs on existing board Virtex2Pro VP20 (master) S3-4000 they are wired only for serial config, to 64 macrocell PLD with connection to MMC card and Atmel Dataflash the PLD has also 12MHz clock. I assumed the fastest way of config would be using VP20 as master serial, setting config clock option to 26MHz and.. well doesnt seem to work at first I tried config from MMC card, by using 2 bitstremeams 'appended' eg vp20.bit + s3.bit this works so that both FPGAs release DONE but only VP20 releases GWE, the S3 stays in configured but not-started state. after using bitgen to embedded the s3 bitstream S3 also started to set GWE and both FPGAs configure ok and will become functional this same bitstream also works when used from dataflash while VP20 is in master serial mode with cfgclock = 4MHz as soon I as set the cfg clock option to anything higher then 4 (8 Mhz) then S3 still releases done, but VP20 sets "legacy input error" bit in status register. I cant belive that 8MHz is too fast for VP20 in master serial mode, so where is the trick? the slave FPGA that is getting passthrough data from VP20 does configure OK so I assume the signal integrity isnt the problem, also I would rather expect CRC error when the VP20 would see corrupted data? Any idea? new PCB isnt an option - the boards are made and are also somewhat functional the question is what can be done to get the serial clock boosted up AnttiArticle: 100140
John Larkin wrote: > On 3 Apr 2006 11:31:07 -0700, "Alan Nishioka" <alan@nishioka.com> > wrote: > > >John Larkin wrote: > >> I've highlighted a number of howlers in Black Magic. Half his stuff is > >> right and half is silly. If you know enough to tell the difference, > >> you don't need the book. > > > >Don't keep us in suspense! Where are the funny parts in Howard > >Johnson's book? > > > > It's at work. I'll post some tomorrow. > > > > >> His opinions on "return currents" are hilarious. > > > >Could you expand on this? > > > >As far as I can tell, his opinion on return currents is that you have > >to be as careful about the return current as you are for the, uh, > >forward current. Is this incorrect? (or is it an incorrect > >characterization of his opinion?) > > That is indeed his opinion, and it's goofy. He gives one example > somewhere of a board with two ground planes, with a signal trace going > from one surface layer to the opposite one through a via. He now > suggests that the "return current" can't get from one ground plane to > the other and gets confused or something. So he says to add *two* > ground-ground vias, straddling the signal via, to let the return > current find its way home. > > Has anybody actually, ever, done anything this silly? The power and > ground planes of a multilayer board are massively coupled by the > dielectric capacitance. There's typically thousands of times more > plane-plane capacitance than the C of an entire signal trace. The > whole mess is equipotential as far as any tiny trace-capacitance > currents can influence things. The trace doesn't care if it's > "referenced to" its "original" ground, to another ground, to a power > pour, whatever. It's all just one big AC ground. > > HoJo also recently showed a picture of some spark gap corona that > supposedly illustrated return currents, and Phil Hobbs pointed out (in > s.e.d) that the sparks were in the wrong places. Phil and I were > competing to lowball-bid to anybody willing to buy our copies of Black > Magic. > > Phil's book, on the other hand, is astonishing. Which book would that be?Article: 100141
On 2006-02-19, Sylvain Munaut <com.246tNt@tnt> wrote: > >> Osnet wrote: >>>Does anyone know if MontaVista Linux or other distributions support SMP >>>in Virtex-II Pro and Virtex-4? Thanks. > > Paul Hartke wrote: >> No, the PowerPC405 caches in the current Xilinx FPGAs are not cache >> coherent and so do not support SMP. >> > > I don't really get the relation between the two facts ... The OS could > enforce coherency in software, by forcing a cache flush during task > switching I think ... This cannot handle threaded applications running on multiple CPUs since they will share the same memory. If you do not have any threaded applications it might work. The biggest problem for the original poster is however that the multiprocessor support in the Linux kernel itself is designed on the principle that the memory system is cache coherent. Rewriting all of that is going to be non-trivial to say the least. The best you can hope for in this case is to run two copies of the Linux kernel, one on each processor. /AndreasArticle: 100142
Hi, I have just received the XUPV2P board and trying to install the adept software to program it but the problem I seem to experience is the installer is interrupted and requires a restart. Originally I thought the problem stems from using the service pack 2 for Windows 2000 and old version of the installer so I have upgraded my machine with service pack 4 and the latest windows installer 3.1 but that doesn't seem to make any difference as the installation still get interrupted. I was wondering if anyone has experience this problem before. Cheers PaulArticle: 100143
Can some have the material ahout the power design in fpga,and how to estimate the power in fpga,as I know the flash based and antifuse based fpga have the low power,but the design require reconfiguration.And have some other reason,we must use the sram based fpga,cyclone and spartan 3e has the low power,and I didn't konw how to estimate the power in the project,and the power only I can use is in 300mw.Can someone give some advice?Article: 100144
John Larkin wrote: > That is indeed his opinion, and it's goofy. He gives one example > somewhere of a board with two ground planes, with a signal trace going > from one surface layer to the opposite one through a via. He now > suggests that the "return current" can't get from one ground plane to > the other and gets confused or something. So he says to add *two* > ground-ground vias, straddling the signal via, to let the return > current find its way home. > > Has anybody actually, ever, done anything this silly? The power and > ground planes of a multilayer board are massively coupled by the > dielectric capacitance. There's typically thousands of times more > plane-plane capacitance than the C of an entire signal trace. The > whole mess is equipotential as far as any tiny trace-capacitance > currents can influence things. The trace doesn't care if it's > "referenced to" its "original" ground, to another ground, to a power > pour, whatever. It's all just one big AC ground. > > HoJo also recently showed a picture of some spark gap corona that > supposedly illustrated return currents, and Phil Hobbs pointed out (in > s.e.d) that the sparks were in the wrong places. Phil and I were > competing to lowball-bid to anybody willing to buy our copies of Black > Magic. > > Phil's book, on the other hand, is astonishing. > > John I don't have simply the opinion that the return current has problems when switching layers, I know the return current has problems when switching layers. The distributed capacitance in 4-mil spaced power/ground plane combinations is only about 240 pF/in^2. While going from an outside layer to the inside layer involves a large percentage of the current staying on the 240 pF/in^2 power/ground plane pair near that signal, a switch from top layer to bottom layer involves the total switch of return current between outside reference planes at *significantly* lower distributed capacitance. If there are no decoupling caps (for power/ground sitch) or ground-to-ground vias nearby (for ground/ground switch) there WILL BE crosstalk between nearby signals. This is basic transmission theory, no black magic. The only silly thing is that the idea is dismissed so easily. I admit to having some trouble grasping the issue over a decade ago when I first had to worry about detailed, high speed board design but I got over my confusion. What gets to be really amazing is when you're used to looking at signals on a scope and the rise/fall of a signal is very crisp but the logic level that follows is a regular mess; I say "regular" because I was "used to" seeing the signal all over the place when probing my wire wrap fixtures or poorly designed boards. Once a "good" board is brought to the scope, the "rock solid" behavior of the signals not only at the transition but in the logic levels before and after is impressive to the eye of one used to the flailing voltages. Return currents switching between planes with no local route to make the switch DOES cause crosstalk and EMI. I have no doubt; I believe it's not a matter of "faith" but of physicas.Article: 100145
robert bristow-johnson wrote:
> Roger Bourne wrote:
> > Thank you rbj
> > But I am looking for a set of equations for a CASCADED structure of
> > biquad filters.
>
> Roger, the information provided is for exactly that.
>
> > I.E.
> > If the biquad 2nd order (chebychev) IIR filters form a cascaded higher
> > order IIR filter structure, as to obtain a very sharp & immediate
> > response at the cutoff frequency, how would the filter coeffcients of
> > one filter be related to the other filters? I know from online applets
> > that for a 4x2nd order filter, that all 4 filters are different.
> >
> > Can you advise me?
>
> OK, "4x2nd order" means N = 8.
>
> perhaps i should have subscripted each pole pair:
>
> p_n = -cos(theta)*sinh(phi) +/- j*sin(theta)*cosh(phi)
>
> where phi = (1/N)*arcsinh(1/e)
>
> { pi/N*(n + 1/2) 0 <= n < N/2 N even
> and theta = {
> { pi/N*(n) 0 <= n < N/2 N odd
>
> note that for N odd, p_0 represents a single purely real and negative
> number. (no conjugate.)
>
>
> a pole at
>
> p_n = -cos(theta)*sinh(phi) + j*sin(theta)*cosh(phi)
>
> will have a counterpart reflected on the negative real axis on the
> s-plane:
>
> p_n* = -cos(theta)*sinh(phi) - j*sin(theta)*cosh(phi)
>
> which is the complex conjugate. so for one 2nd order stage:
>
> H(s) = 1 / (1 - s/p_n)(1 - s/p_n*)
>
> = |p_n|^2 / (s - p_n)(s - p_n*)
>
> = |p_n|^2 / (s^2 - 2*Re{p_n}*s + |p_n|^2)
>
> this is for normalized s where the "significant frequency" (which is
> normalized to w=1) is the bandedge of the passband where the ripple
> ends and the gain just begins to dive toward 0.
>
> you can easily work out what 2*Re{p_n} and |p_n|^2 is. that's your
> first "assignment."
>
> then use the BLT substitution explicitly provided in the audio EQ
> cookbook (at the bottom of the page), and you'll get the biquad stage
> in the z-plane.
>
> that's advice. i ain't gonna design if for you, but i'm sure there is
> someone listening in that would be happy to take your money to do it.
> :-)
>
> r b-j
The equations look rather daunting, but I'll take a crack at them.
However, I want to ask you again this question:
Q: The equations ARE for a cascaded structure of biquad 2nd order
(chebychev) IIR filters, Rigth ?
The reason why I am asking you the question is that upon scanning the
equations, I cannot seem to locate the different DCgains of the
individual biquad filters in the cascade structure on the analog set of
equations...According to my intuition, it is the fact that some of the
filters (in the cascacded structure) start to attenuate sooner (than
other filters) and the fact that some of the filters have a positive
DCgain and others negative DCgain and the fact that some (almost all)
of the filters have some kind of shaping (underdamping) about them THAT
we observe on the output of the cascaded structure a very sharp &
immediate & steady reponse at the intended cutoff frequency (or maybe a
little bit higher than the intended higher frequency). I know, from
online-applet experience, that for N=8, the 4 filters obtained were all
different and gave a great output response.
However, I have faith that it is my newbieism that is probably the
center of the misunderstanding.
I also want to confirm the following:
Is the basic procedure for obtaining coeffcients the following (at
least for analog-prototype equivalent filters, Chebbychev, Cauer,
Butterworth....):
1. Obtain Filter Analog Equation
2. Go through some normalization process of the analog equation
3. Perform the Bilinear Transform
-Roger
Article: 100146Hello: I have been using system ACE Compact Flash for configuration with a V2PRO system. I saw that one can use a microdrive device instead of a compact flash device. Given that Compact Flash just uses a standard IDE interface, couldn't one just replace the compact flash with a standard IDE header and use a standard Harddrive? -EliArticle: 100147
On 4 Apr 2006 05:20:18 -0700, "rickman" <spamgoeshere4@yahoo.com> wrote: >John Larkin wrote: >> On 3 Apr 2006 11:31:07 -0700, "Alan Nishioka" <alan@nishioka.com> >> wrote: >> >> >John Larkin wrote: >> >> I've highlighted a number of howlers in Black Magic. Half his stuff is >> >> right and half is silly. If you know enough to tell the difference, >> >> you don't need the book. >> > >> >Don't keep us in suspense! Where are the funny parts in Howard >> >Johnson's book? >> > >> >> It's at work. I'll post some tomorrow. >> >> > >> >> His opinions on "return currents" are hilarious. >> > >> >Could you expand on this? >> > >> >As far as I can tell, his opinion on return currents is that you have >> >to be as careful about the return current as you are for the, uh, >> >forward current. Is this incorrect? (or is it an incorrect >> >characterization of his opinion?) >> >> That is indeed his opinion, and it's goofy. He gives one example >> somewhere of a board with two ground planes, with a signal trace going >> from one surface layer to the opposite one through a via. He now >> suggests that the "return current" can't get from one ground plane to >> the other and gets confused or something. So he says to add *two* >> ground-ground vias, straddling the signal via, to let the return >> current find its way home. >> >> Has anybody actually, ever, done anything this silly? The power and >> ground planes of a multilayer board are massively coupled by the >> dielectric capacitance. There's typically thousands of times more >> plane-plane capacitance than the C of an entire signal trace. The >> whole mess is equipotential as far as any tiny trace-capacitance >> currents can influence things. The trace doesn't care if it's >> "referenced to" its "original" ground, to another ground, to a power >> pour, whatever. It's all just one big AC ground. >> >> HoJo also recently showed a picture of some spark gap corona that >> supposedly illustrated return currents, and Phil Hobbs pointed out (in >> s.e.d) that the sparks were in the wrong places. Phil and I were >> competing to lowball-bid to anybody willing to buy our copies of Black >> Magic. >> >> Phil's book, on the other hand, is astonishing. > >Which book would that be? "Building Electro-Optical Systems." Begins with quotes by Richard Feynman and Otto von Bismarck. Classy all the way through. JohnArticle: 100148
On Tue, 04 Apr 2006 13:31:38 GMT, John_H <johnhandwork@mail.com> wrote: >John Larkin wrote: >> That is indeed his opinion, and it's goofy. He gives one example >> somewhere of a board with two ground planes, with a signal trace going >> from one surface layer to the opposite one through a via. He now >> suggests that the "return current" can't get from one ground plane to >> the other and gets confused or something. So he says to add *two* >> ground-ground vias, straddling the signal via, to let the return >> current find its way home. >> >> Has anybody actually, ever, done anything this silly? The power and >> ground planes of a multilayer board are massively coupled by the >> dielectric capacitance. There's typically thousands of times more >> plane-plane capacitance than the C of an entire signal trace. The >> whole mess is equipotential as far as any tiny trace-capacitance >> currents can influence things. The trace doesn't care if it's >> "referenced to" its "original" ground, to another ground, to a power >> pour, whatever. It's all just one big AC ground. >> >> HoJo also recently showed a picture of some spark gap corona that >> supposedly illustrated return currents, and Phil Hobbs pointed out (in >> s.e.d) that the sparks were in the wrong places. Phil and I were >> competing to lowball-bid to anybody willing to buy our copies of Black >> Magic. >> >> Phil's book, on the other hand, is astonishing. >> >> John > >I don't have simply the opinion that the return current has problems >when switching layers, I know the return current has problems when >switching layers. The distributed capacitance in 4-mil spaced >power/ground plane combinations is only about 240 pF/in^2. While going >from an outside layer to the inside layer involves a large percentage of >the current staying on the 240 pF/in^2 power/ground plane pair near that >signal, a switch from top layer to bottom layer involves the total >switch of return current between outside reference planes at >*significantly* lower distributed capacitance. Planes are shorted by their parallel-plate capacitance, as well as any additional vias and bypass caps. For, say, a 1 ns risetime edge, the amount of pcb plane that matters is in the ballpark of a square foot... tens of nanofarads. And within that square foot or so, there are going to be LOTS of bonus vias and bypasses. A couple of pF per inch of trace capacitance sees this structure as a dead short. Proper planes are equipotential as close as doesn't matter. The entire plane structure is the "return path." If your planes *aren't* HF equipotential to 100 mV or less, you've screwed up a number of things. If they are, a signal can't distinguish between them as "reference planes." >If there are no >decoupling caps (for power/ground sitch) or ground-to-ground vias nearby >(for ground/ground switch) there WILL BE crosstalk between nearby >signals. Of course: there's always crosstalk between nearby signals. >This is basic transmission theory, no black magic. Words, not theory. Theory needs numbers. >The only silly thing is that the idea is dismissed so easily. I admit >to having some trouble grasping the issue over a decade ago when I first >had to worry about detailed, high speed board design but I got over my >confusion. > >What gets to be really amazing is when you're used to looking at signals >on a scope and the rise/fall of a signal is very crisp but the logic >level that follows is a regular mess; I say "regular" because I was >"used to" seeing the signal all over the place when probing my wire wrap >fixtures or poorly designed boards. Once a "good" board is brought to >the scope, the "rock solid" behavior of the signals not only at the >transition but in the logic levels before and after is impressive to the > eye of one used to the flailing voltages. > >Return currents switching between planes with no local route to make the >switch DOES cause crosstalk and EMI. I have no doubt; I believe it's >not a matter of "faith" but of physicas. This gadget accepts an OC-3 optical payload, phase-locks to it, picks out triggers, and generates eight delays of up to two seconds each, with 1 ps resolution. Relative jitter between channels is around 3 ps RMS, and between two separate boards around 6. It has a uP, optical receiver, a PLL, two FPGAs, and all sorts of nasty stuff, including a bunch of Eclips Lite ecl, running mostly in PECL mode, where the ecl logic reference is +5V. It was laid out entirely with disregard for return current paths. http://www.highlandtechnology.com/DSS/V880DS.html JohnArticle: 100149
Hello,
Recently I bought an Ethernet Module from your web-site. I have used
the
recommended vhdl file (dpimref.vhd) to test this Ethernet Module. I
placed
the code that is used for the leds and buttons in comment because they
are
not available on the Ethernet Module.
When I download this design to a Xilinx Virtex II pro development board
and
I use the communication software from you web-site the communication
doens't
always go without errors.
The writing to the FPGA works perfect, but when I want to read from the
FPGA
sometimes I read out the address of the register where I want to read
instead of the data of that register
Example: I write to the FPGA at register 0x01 the value 0x08. When I
want to
read from register 0x01 I read 95% of the times 0x08 but the other 5% I
read
out 0x01 with is the address.
I have asked the suport of digilent inc what I can do about this and
they repleyed
Before building the Dpimref logic in ISE:
1. In Project Navigator, right-click on "Synthesize-XST"
(in the Process View Tab) and select "Properties"
2. Click the "HDL Options" tab
3. Set the "FSM Encoding Algorithm" to "None"
This is the trick when I use ISE
but where can I set this option in the EDK?
Greets
Mich
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